Tasks vs. Functions — When to Use Which

// ── Function: compute even parity of an 8-bit byte ──────────────
function automatic logic calc_parity (input logic [7:0] data);
    return ^data;    // XOR-reduce: 1 if odd number of 1s
endfunction
 
// ── How to CALL a function — used as part of an expression ───────
logic parity_bit;
parity_bit = calc_parity(tx_byte);         // RHS of assignment
 
if (calc_parity(rx_byte) != rx_parity_in)  // inside a condition
    $error("Parity error!");
 
assign parity_out = calc_parity(data_bus); // continuous assignment — legal!
 
// ── Function: priority encoder ───────────────────────────────────
function automatic logic [2:0] priority_enc (input logic [7:0] req);
    priority_enc = 3'b000;                 // default return value
    for (int i = 7; i >= 0; i--)
        if (req[i]) priority_enc = i[2:0];
endfunction
 
// ── Function inside always_comb — completely safe ────────────────
always_comb begin
    encoded_out = priority_enc(request_bus);  // zero-time call inside RTL
end

// ── Task: drive an APB write transaction ──────────────────────────
task automatic apb_write (
    input  logic [31:0] addr,
    input  logic [31:0] data,
    output logic        err   // multiple return values via output ports
);
    // Tasks CAN contain timing controls
    @(posedge clk);                    // wait for clock edge ← legal in task
    psel  = 1; paddr = addr; pwrite = 1;
    @(posedge clk);                    // setup phase
    penable = 1; pwdata = data;
    @(posedge clk);                    // access phase
    err = pslverr;
    psel = 0; penable = 0;
endtask
 
// ── How to CALL a task — always a standalone statement ───────────
logic write_err;
apb_write(32'h4000_0000, 32'hABCD_1234, write_err);
// ← NOT inside an expression. A task call stands alone on its own line.
 
// ── Task: wait for N clock cycles ────────────────────────────────
task automatic wait_cycles (input int n);
    repeat(n) @(posedge clk);
endtask
 
// ── Task: stimulus sequence ───────────────────────────────────────
initial begin
    wait_cycles(5);                           // wait 5 clocks
    apb_write(32'h0, 32'hFF, write_err);      // drive transaction
    wait_cycles(10);                          // wait more
end

// ════ FUNCTION CALLS — used inside expressions ════════════════════
 
// ① Assignment RHS
parity = calc_parity(data);
 
// ② Condition in if/while
if (is_one_hot(req_bus)) $display("valid");
 
// ③ Continuous assign
assign encoded = priority_enc(request);
 
// ④ Inside $display / $error format string args
$display("CRC = %h", compute_crc(payload));
 
// ⑤ Port connection
adder  u_add (.a(mask_bits(raw_a)), .b(b), .sum(sum));
 
// ⑥ Array index
lut_out = lut[hash_fn(key)];
 
 
// ════ TASK CALLS — always a complete statement ═════════════════════
 
// ① Standalone statement in initial/always
apb_write(32'h0, 32'hFF, err_out);         // ← semicolon ends the statement
 
// ② Chained in a sequence
reset_dut();
wait_cycles(10);
apb_write(32'h1000, 32'hA, err_out);
 
// ③ Inside fork-join for parallel execution
fork
    drive_master();    // runs concurrently
    monitor_slave();   // runs concurrently
join
 
// ❌ WRONG: calling a task inside an expression
// parity = apb_write(addr, data, err);  ← task, not function — compiler error
 
// ❌ WRONG: calling a function as a statement expecting side-effects-only
// calc_parity(data);  ← legal syntax but result is discarded — waste
// ✅ If you want a function with no return use: void'(calc_parity(data));

// ════ WRONG: timing control inside a function ════════════════════
function automatic logic [31:0] read_reg_bad (input logic [11:0] addr);
    @(posedge clk);          // ❌ COMPILE ERROR: event control not allowed
    return regfile[addr];    //    in a function
endfunction
 
// ════ FIX ①: Convert to a task (if timing is truly needed) ═══════
task automatic read_reg_good (
    input  logic [11:0] addr,
    output logic [31:0] rdata
);
    @(posedge clk);          // ✅ legal in task
    rdata = regfile[addr];
endtask
 
// Usage:
logic [31:0] val;
read_reg_good(12'h00C, val);   // task call — standalone statement
 
 
// ════ FIX ②: Remove timing if it wasn't actually needed ══════════
function automatic logic [31:0] read_reg_comb (input logic [11:0] addr);
    return regfile[addr];    // ✅ pure combinational — no timing needed
endfunction
 
// Usage (as expression):
assign reg_out = read_reg_comb(reg_addr);  // ✅ zero time, RTL-safe

// ════ USE function WHEN ═══════════════════════════════════════════
// ✔ Computing a value to use in an expression
// ✔ No timing controls needed (#, @, wait)
// ✔ Called inside assign, always_comb, if condition, port, array index
// ✔ The code is combinational / synthesisable
// ✔ You want to call it inside an assertion property
 
// Examples: calc_parity(), crc8(), gray2bin(), is_one_hot(), priority_enc()
 
 
// ════ USE task WHEN ══════════════════════════════════════════════
// ✔ Waiting for clock edges, events, or delays
// ✔ Driving a bus transaction (APB, AHB, AXI, I2C, SPI...)
// ✔ Generating stimulus sequences
// ✔ Returning multiple values (via output / ref ports)
// ✔ Forking parallel activities
// ✔ The code is testbench-only (not for synthesis)
 
// Examples: apb_write(), wait_cycles(), reset_dut(), send_packet()
 
 
// ════ SPECIAL CASES ══════════════════════════════════════════════
// Need no return AND no timing?
function automatic void log_event (input string msg);
    $display("[%0t] %s", $time, msg);   // void function — no return value
endfunction                              // called as void'(log_event("boot"));
 
// Need timing AND return a value?
task automatic read_and_check (input addr, output logic [31:0] data,
                                output logic ok);
    @(posedge clk);          // ← task handles the timing
    data = regfile[addr];    // ← output port acts as return value
    ok   = (data != '0);
endtask

// ════ MISTAKE 1: Calling a task inside a function ════════════════
function automatic void bad_fn();
    wait_cycles(5);    // ❌ wait_cycles is a task — illegal inside function
endfunction
// ✅ FIX: convert the outer function to a task
task automatic good_task();
    wait_cycles(5);    // ✅ task can call task
endtask
 
 
// ════ MISTAKE 2: Calling a task inside always_comb ═══════════════
always_comb begin
    apb_write(addr, data, err);  // ❌ task in always_comb: timing violation
end
// ✅ FIX: use only functions inside always_comb
always_comb begin
    parity = calc_parity(data);  // ✅ function call: zero-time, safe
end
 
 
// ════ MISTAKE 3: Using a task where a function is expected ════════
assign out = apb_write(addr, data, err);  // ❌ task in continuous assign
// ✅ FIX: apb_write should be a task called in initial/always, not assign
 
 
// ════ MISTAKE 4: Expecting a task to return a value ══════════════
task automatic get_data (input addr);
    return regfile[addr];   // ❌ tasks cannot return values with 'return'
endtask
// ✅ FIX: use output port
task automatic get_data (input addr, output logic [31:0] rdata);
    @(posedge clk); rdata = regfile[addr];   // ✅ output port carries result
endtask

// ── Pattern 1: Parameterized parity with synthesis-safe function ──
function automatic logic parity #(parameter int W=8) (input logic [W-1:0] d);
    return ^d;   // XOR-reduce: synthesizes to a log₂(W)-level XOR tree
endfunction
 
always_comb tx_parity = parity #(32)(tx_data);  // 32-bit parity in hardware
 
// ── Pattern 2: Gray code to binary (used in FIFO pointer sync) ───
function automatic logic [7:0] gray2bin (input logic [7:0] g);
    logic [7:0] b;
    b[7] = g[7];
    for (int i = 6; i >= 0; i--)
        b[i] = b[i+1] ^ g[i];
    return b;
endfunction
 
always_comb rd_ptr_bin = gray2bin(rd_ptr_gray);  // FIFO async domain crossing
 
// ── Pattern 3: Saturating add (avoids overflow) ───────────────────
function automatic logic [7:0] sat_add (input logic [7:0] a, b);
    logic [8:0] wide = {1'b0,a} + {1'b0,b};
    return wide[8] ? 8'hFF : wide[7:0];
endfunction
 
always_comb result = sat_add(accum, delta);  // overflow → clamp at 0xFF
 
// ── Pattern 4: One-hot check (used in assertions) ─────────────────
function automatic logic is_one_hot (input logic [7:0] v);
    return (v != 8'h00) && ((v & (v-1)) == 8'h00);  // power-of-2 check
endfunction
 
// In RTL assertion:
assert property (@(posedge clk) bus_active |-> is_one_hot(grant))
    else $error("Grant not one-hot: %b", grant);
 
// ── Pattern 5: CRC-8 function (used in protocol checksum RTL) ─────
function automatic logic [7:0] crc8_update (
    input logic [7:0] crc_in, data_byte);
    logic [7:0] tmp = crc_in ^ data_byte;
    for (int i = 0; i < 8; i++)
        tmp = tmp[7] ? (tmp << 1) ^ 8'h07 : (tmp << 1);
    return tmp;
endfunction
 
always_ff @(posedge clk) begin
    if (valid) crc_reg <= crc8_update(crc_reg, rx_byte);  // pipelined CRC
end
 
// ── Pattern 6: AXI address decode (mutually exclusive regions) ────
function automatic logic [1:0] axi_decode (input logic [31:0] addr);
    if      (addr inside {[32'h0000_0000:32'h0FFF_FFFF]}) return 2'b00; // BOOT ROM
    else if (addr inside {[32'h1000_0000:32'h1FFF_FFFF]}) return 2'b01; // SRAM
    else if (addr inside {[32'h4000_0000:32'h4FFF_FFFF]}) return 2'b10; // Peripherals
    else                                                  return 2'b11; // Error
endfunction
 
always_comb slave_sel = axi_decode(awaddr);  // zero-time decode in comb logic

module tb_soc;
    logic clk = 0, rst_n;
    logic [31:0] awaddr, wdata, rdata;
    logic        awvalid, awready, wvalid, wready, bvalid, bready;
    logic        arvalid, arready, rvalid, rready;
    int          pass_cnt=0, fail_cnt=0;
 
    // ── ① Clock generator ────────────────────────────────────────
    always #5 clk = ~clk;
 
    // ── ② Reset generator task ───────────────────────────────────
    task automatic apply_reset(input int cycles = 8);
        rst_n = 0;
        repeat(cycles) @(posedge clk);
        rst_n = 1;
        @(posedge clk);  // settle after release
    endtask
 
    // ── ③ AXI write transaction task ─────────────────────────────
    task automatic axi_write(
        input  logic [31:0] addr, data,
        output logic [1:0]  bresp
    );
        fork
            begin : aw_phase
                awaddr = addr; awvalid = 1;
                @(posedge clk iff awready); awvalid = 0;
            end
            begin : w_phase
                wdata = data; wvalid = 1;
                @(posedge clk iff wready); wvalid = 0;
            end
        join
        bready = 1;
        @(posedge clk iff bvalid);
        bready = 0;
    endtask
 
    // ── ④ AXI read transaction task ──────────────────────────────
    task automatic axi_read(
        input  logic [31:0] addr,
        output logic [31:0] data
    );
        araddr = addr; arvalid = 1;
        @(posedge clk iff arready); arvalid = 0;
        rready = 1;
        @(posedge clk iff rvalid);
        data = rdata; rready = 0;
    endtask
 
    // ── ⑤ Scoreboard check task ──────────────────────────────────
    task automatic check(
        input logic [31:0] got, expected,
        input string         test_name
    );
        if (got === expected) begin
            $display("[PASS] %s: got=%h", test_name, got); pass_cnt++;
        end else begin
            $error("[FAIL] %s: got=%h exp=%h", test_name, got, expected);
            fail_cnt++;
        end
    endtask
 
    // ── ⑥ Handshake wait with timeout task ───────────────────────
    task automatic wait_valid(ref logic sig, input int timeout=100);
        fork
            begin : wait_proc @(posedge clk iff sig); end
            begin : timeout_proc repeat(timeout) @(posedge clk);
                $fatal(1, "Timeout waiting for signal");
            end
        join_any
        disable fork;
    endtask
 
    // ── Main test sequence ────────────────────────────────────────
    initial begin
        logic [31:0] rd_val; logic [1:0] bresp;
 
        apply_reset();                                  // ① reset
        axi_write(32'h4000_0000, 32'hCAFE_BABE, bresp); // ② write
        axi_read (32'h4000_0000, rd_val);               // ③ readback
        check(rd_val, 32'hCAFE_BABE, "Reg readback");   // ④ verify
 
        $display("DONE: pass=%0d fail=%0d", pass_cnt, fail_cnt);
        $finish;
    end
endmodule

Function call — zero time
Time     T=100     T=100     T=100
clk      posedge   ─────     ─────
caller   ──────────fn_call──continues   ← All at same T=100 (same delta)
parity             computed  available  ← Instantaneous result
 
Task call — time advances
Time     T=100     T=110     T=120     T=130
clk      posedge   posedge   posedge   posedge
caller   ──────────task_call─────────────────resumes
task               start→@clk→@clk→@clk→done
bus sigs           setup──────enable──done
          Caller suspended during T=100→T=130. Other processes can run.

// ── Concurrent task calls via fork-join ──────────────────────────
// Each task runs as a separate simulation process
initial begin
    apply_reset();
 
    fork                         // Launch two tasks in parallel
        drive_master_a();        // ← starts at same simulation time
        drive_master_b();        // ← starts at same simulation time
    join                         // wait for BOTH to complete
    $display("Both masters done");
end
 
// ── CRITICAL: tasks must be automatic for this to work safely ────
// If drive_master_a and drive_master_b are static, they share local vars
// → race condition on temp variables, non-deterministic test results
task automatic drive_master_a();
    int beat;           // ← automatic: each call gets own copy
    for (beat = 0; beat < 10; beat++) begin
        @(posedge clk);
        master_a_data = beat;
    end
endtask
 
// ── The $strobe trick: view task output AFTER it settles ──────────
task automatic timed_check(input logic [31:0] expected);
    @(posedge clk);
    // $display at posedge: sees PRE-NBA value of FF outputs
    $display("(display) dout=%h", dut.dout);   // may show old value!
    // $strobe at posedge: sees FINAL settled value (post-NBA)
    $strobe("(strobe)  dout=%h", dut.dout);    // correct: use this
    if (dut.dout !== expected)
        $error("Mismatch: got %h exp %h", dut.dout, expected);
endtask