Yield Challenges

Reticle Size Limits established a boundary: a conventional monolithic die must fit inside one lithographic exposure field. That answers can this be patterned? — and it is the wrong question to stop on, because most large designs never get near that boundary. They stop growing long before it, for a reason that has nothing to do with geometry. A die can fit the field with room to spare, be entirely manufacturable, and still be a product nobody should build. This chapter is about the mechanism behind that: manufacturing yield, and specifically how it behaves as die area grows. Once you can reason about it, the two constraints stop blurring together — the exposure field decides where the ceiling is, and yield decides whether approaching it was ever sensible.

1. Not Every Printed Die Works

Start with the physical reality, before any definition or equation.

A wafer that has been through a modern fab is not perfect. Across hundreds of processing steps — deposition, patterning, etch, implant, polish — imperfections occur. A particle lands where it should not. A pattern prints slightly wrong. A layer varies in thickness. Most of these are harmless. Some land somewhere consequential and leave a circuit that does not behave as designed.

Now hold two dies side by side, fabricated on the same wafer, in the same process, on the same day. One is small. The other is much larger. Nothing about the manufacturing differs — the same defects, at the same rate, are scattered across the same silicon.

The difference is how much silicon each die occupies. The larger die covers more area, so more of what lands on that wafer lands inside it. The small die can sit in the gaps between problems; the large one has fewer gaps to sit in.

A die is a target. The more area one die occupies, the more opportunities it has to intersect a defect that ruins it.

That is the whole intuition, and everything that follows is a way of making it precise. Notice what it does not depend on: not on the process being bad, not on the design being careless, not on approaching any lithographic boundary. It follows purely from a large object being more likely to be hit than a small one.

2. What Yield Actually Means

With the intuition in place, the vocabulary is easy — and worth being precise about, because these terms get used loosely and the distinctions carry the argument.

• Gross dies (or candidate dies) — how many complete dies fit on one wafer at all. This is pure geometry: wafer size and die size, nothing else.
• Good dies — the subset that pass test and can become products.
• Die yield — the fraction that survive: good dies ÷ candidate dies.

Two kinds of failure sit behind that fraction, and they behave differently:

• Catastrophic (random-defect) failures — a physical defect breaks the circuit: a short, an open, a structure that did not form. This is the failure mode that scales with area, and it is the one this chapter is about.
• Parametric failures — the die works logically but misses a required electrical target: it does not reach the required frequency, or leaks too much, or misses a voltage specification. These trace mostly to process variation rather than to discrete defects. Parts that miss the top target but meet a lower one are often sold as a lower-speed part — the practice called binning — so "fails" and "worthless" are not the same thing.

Real yield accounting in a fab is considerably more layered than this — it separates line yield, wafer yield, die yield, and assembly and test yield, and it tracks them by product, layer, and defect type. The simplified picture — good dies over candidate dies, dominated by random defects that scale with area — is not the whole truth, but it is the part that drives the architectural argument, and it is enough to reason correctly here.

3. Defect Density

To connect area to yield we need a way to describe how "dirty" a process is, independent of what is being built on it. That is defect density, usually written D₀: the expected number of yield-killing defects per unit area, conventionally per cm².

Read it as a rate, not a count. D₀ = 0.1 per cm² does not mean every square centimetre contains one tenth of a defect — defects are discrete. It means that on average, across a large amount of silicon, you expect about one such defect per ten square centimetres. Any individual die either contains one or does not.

Three qualifications keep this honest, and skipping them is how people end up with wrong conclusions:

• Real defects are not uniformly and independently scattered. They cluster — a particular tool, chamber, or process excursion tends to damage a region of a wafer rather than sprinkling failures evenly. Wafer edges typically behave worse than centres. This matters more than it sounds, and §5 returns to it.
• D₀ is not a constant. It falls as a process matures, which is why a node's yield early in its life differs substantially from the same node's yield years later. Quoting a defect density without saying which process, at what maturity is meaningless.
• What counts is critical area, not raw die area. A defect only kills a die if it lands somewhere consequential and is large enough to matter. Defect-sensitivity depends on layout — how densely packed the wires are, where the spacing is tightest. Yield modelling accounts for this through critical area rather than the full die area. Two dies of the same size and different layouts do not have identical defect sensitivity.

None of that changes the direction of the effect, which is why a simplified model is still useful: whatever the details, more area means more exposure.

4. A Simplified Model — and Its Health Warning

The standard first-order model treats defects as randomly and independently scattered at uniform density. Under that assumption, the number of defects landing in a die of area A follows a Poisson distribution, and yield is the probability that a die contains zero of them:

Y ≈ e^(−D₀A)

where Y is die yield, D₀ is defect density per unit area, and A is die area (in matching units — if D₀ is per cm², then A is in cm²).

The physical reading is direct. The product D₀A is the expected number of defects per die. Grow the area, and that expected number grows proportionally — but yield is the probability of getting none, and that probability decays exponentially. Area rises linearly; the chance of a clean die falls exponentially. That mismatch is the entire problem.

5. A Worked Example

Numbers make the shape visible. Everything below is hypothetical — chosen to be arithmetically clean, not to represent any real process, node, or company. Real defect densities are closely held and vary enormously with process maturity.

Take a hypothetical D₀ = 0.1 defects/cm² and compare three dies on that same process. Remember 100 mm² = 1 cm².

Now look at what doubling actually did. Going from 200 mm² to 400 mm² did not halve the yield — 81.9 % did not become 41 %. It became 67 %. The relationship is neither "half" nor merely "somewhat worse", and there is an exact way to say what it is:

Under this model, doubling the die area squares the yield.

Check it: 0.819² = 0.670, and 0.819⁴ = 0.449. That falls straight out of the exponential — e^(−2D₀A) = (e^(−D₀A))². It is worth internalising because it replaces a vague sense that "yield gets worse" with a precise mental operation. A die at 90 % yield, doubled in area, lands near 81 %; doubled again, near 66 %. Each doubling multiplies by the original fraction again, so the decline accelerates exactly where designs are most ambitious.

6. The Second Penalty: Fewer Candidates to Begin With

Yield is only half of why large dies hurt. There is a second, entirely separate mechanism, and conflating the two is a common error.

A larger die means fewer candidate dies fit on the wafer at all. This is geometry, not defects — it would be true on a hypothetically perfect process with zero defects.

A 300 mm wafer has an area of about 70,700 mm². Dividing by die area gives an upper bound of roughly 353 candidates at 200 mm², and roughly 88 at 800 mm². Treat those as ceilings rather than counts: rectangles do not tile a circle, and dies straddling the wafer edge are incomplete and unusable — edge loss that hurts proportionally more as dies get bigger, because a large die is more likely to overhang.

The two penalties then compound, because they multiply:

good dies ≈ candidate dies × yield

Carrying the same hypothetical numbers through: the 200 mm² die yields on the order of 353 × 81.9 % ≈ 289 good dies from a wafer, while the 800 mm² die yields on the order of 88 × 44.9 % ≈ 39. Four times the area per die, but roughly seven times fewer good dies — because the geometric penalty and the defect penalty stack. And the same wafer, costing the same to process, produced both outcomes.

7. Reticle Limit and Yield Limit Are Different Questions

This is the connection back to the previous chapter, and it is the distinction most worth carrying into an interview.

• The exposure-field constraint asks: can this die be patterned at all? It is geometric and binary. A die either fits within the field or it does not.
• The yield constraint asks: of the dies we manufacture, what fraction are usable? It is statistical and continuous. There is no threshold — it degrades smoothly as area grows.

Because yield degrades continuously, it starts hurting immediately and never stops. A design at half the reticle field is already paying: fewer candidates per wafer, a lower defect-free fraction, more silicon consumed per shipped part. Nothing announces that a line has been crossed, because no line has been. The cost simply climbs.

This is why the honest answer to "why don't chips just get bigger?" leads with yield rather than lithography. Most designs stop growing because it stopped paying, not because it became impossible. The exposure field is the hard backstop behind that; yield is the pressure teams actually feel.

8. Partitioning Changes the Unit of Manufacturing Risk

Here is where a manufacturing statistic starts arguing for an architecture.

Consider one large die holding several substantial regions. If a critical, unrepairable defect lands anywhere in it, the whole die is lost — including every region that came out perfectly. The functioning parts cannot be recovered and sold, because they were manufactured as one inseparable object. The die is the unit of risk, and a big die makes that unit expensive.

Now suppose the same design is built as several smaller dies, fabricated separately. A defect in one die destroys that die. The others were manufactured independently and are unaffected. Two things improve at once: each die is individually smaller, so each has a higher defect-free probability; and a loss is now contained to one piece instead of scaling with the whole design. Partitioning does not reduce the defect rate — it changes what a single defect costs you.

That is a genuine argument, and it is one of the real economic motivations behind multi-die design. It is also, on its own, an incomplete one — and the incomplete version is a weak answer.

A multi-die product introduces costs the monolithic one never had:

• Assembly and packaging yield. Placing several dies into one package is itself a process with its own failure rate. Losing an assembly can mean losing every die in it — including good ones.
• Known-good die (KGD). Before committing dies to an expensive package, you want confidence that each is functional. That means testing at the die level, to a higher standard than a die destined for a simple package would need. Chiplet economics assumes tested-good components; it does not work by packaging untested dies and hoping.
• Interconnect and package cost. Advanced substrates, interposers, or bridges cost real money, and the die-to-die interfaces consume area and power on every die they connect.
• Extra test. More components and a package-level integration step mean more test insertions.

So the accurate statement is narrow: splitting a design into smaller dies improves the die-level manufacturing economics, and moves some of the recovered value into assembly, test, and packaging. Whether the total is better depends on the design, the volumes, and the packaging technology available. Chiplets are an engineering tradeoff, not a yield trick.

9. Why This Matters in Real Engineering Work

• SoC architects treat die area as an economic parameter, not just a floorplan number. "How big is this die?" is a question about cost per shipped part, and it belongs in early scoping rather than late physical design.
• Physical-design engineers influence manufacturability through layout density, spacing, redundancy, and memory repair structures — all of which affect how sensitive a design is to defects. Be careful with the causality: they do not control fab defect density. They control how much of the design is vulnerable to it.
• RTL engineers inherit the partition. Once yield and area economics argue for splitting a design, the resulting boundaries define module ownership, interface protocols, latency budgets, and clock and reset domains — decisions that show up directly in the source.
• Verification engineers face a changed scope. Several independently developed dies mean several verification targets plus a new integration problem at the interfaces between them, where the risk concentrates.
• DFT, product, and test engineers move to the centre of the argument. Wafer test, binning, failure analysis, and known-good-die screening determine whether a multi-die product is viable at all — KGD is a test problem before it is an architecture benefit.

10. Common Misconceptions

11. Understanding Check

12. Summary

A fabricated wafer carries defects at some rate set by the process, and those defects do not care how the wafer is divided. A die is a target: the more area one die occupies, the more likely it is to contain a defect that ruins it. That is the whole mechanism, and the vocabulary follows from it — gross dies is geometry, good dies is what you can sell, and yield is the fraction connecting them.

The simplified Poisson model, Y ≈ e^(−D₀A), makes the shape precise: D₀A is the expected number of defects per die, and yield is the probability of getting none. Because that decays exponentially, doubling the die area squares the yield — with a hypothetical D₀ = 0.1/cm², 200 mm² yields about 81.9 %, 400 mm² about 67.0 %, and 800 mm² about 44.9 %. Treat the model as a way to understand the direction and shape of the effect, not as a production forecast: real defects cluster, which makes the pure Poisson form pessimistic, and refinements such as Murphy's model and the negative-binomial model with a clustering factor exist precisely because of that.

A second, independent penalty compounds it: a larger die means fewer candidate dies fit on the wafer at all, which is pure geometry made worse by edge loss. Since good dies ≈ candidates × yield, the two multiply — in the same hypothetical example, a four-times-larger die produced roughly seven times fewer good dies from an identically priced wafer.

This is a different constraint from the previous chapter's. The exposure field asks can this be patterned and answers yes or no; yield asks what fraction survive and answers with a number that gets worse continuously. That continuity is why yield binds first for most real designs. And it is why partitioning changes the unit of manufacturing risk: a defect in one small die destroys that die rather than the entire system. That argument is real but incomplete — assembly yield, known-good-die testing, packaging, and interconnect cost all move onto the balance sheet the moment a product becomes multi-die.

13. What Comes Next

Yield tells you how many fabricated dies survive. It does not tell you what a surviving one costs, and that is the question a product actually has to answer:

• 1.4 — Cost-Scaling Problems — combining die size, wafer cost, process complexity, the mask set and other fixed engineering expense, test, and volume into the number that decides whether a design ships: cost per good die.

Yield is one input to that calculation, and this chapter deliberately stopped short of the rest. Browse the full path on the UCIe tutorials index.