Cost-Scaling Problems

The last three chapters each described a pressure without pricing it. Scaling stopped delivering its benefits as a bundle; the exposure field caps how large a conventional die can be; and Yield Challenges showed that a die well inside that cap already loses candidates and survivors as it grows. All three end in the same place — this is getting more expensive — and none of them says by how much, or against what. This chapter closes that gap. It builds the path from a processed wafer to the number a product actually lives or dies by: cost per good die, and then the costs that sit beyond even that. The goal is not to make you an accountant. It is to stop you from using five different quantities as if they were one.

1. The Intuition That Stopped Being Reliable

Almost every engineer carries some version of this:

Smaller transistors mean more transistors per wafer, so a newer node makes chips cheaper.

For a long stretch that was not merely plausible — it was true, repeatedly, and it built the industry. Cost per transistor fell generation after generation, and betting on the next node was among the most reliable economic bets in engineering. It deserves respect rather than a dismissal.

What has changed is that it is now an incomplete argument rather than a wrong one. It reasons about one quantity — transistors per unit area — and concludes about a different one: what a finished, working, saleable product costs. Between those two sit the processed wafer, how much of it each die consumes, how many of those dies work, what the mask set and the engineering programme cost before a single unit ships, how many units eventually ship, and what test and packaging add afterwards. Density is an input to that chain. It is not the answer to it.

2. Five Quantities That Are Not the Same Number

These get used interchangeably in conversation, and every serious misconception in this chapter comes from that. Separate them once.

• Cost per wafer. What it costs to run one wafer through the manufacturing flow — the equipment time, materials, and process steps for every layer. It is paid per wafer, and it does not care how you chose to divide that wafer into dies.
• Gross die cost. A conceptual halfway number: wafer cost ÷ gross candidate dies. It answers "what did the silicon under one die footprint cost?" — and it is not what a working part costs, because it ignores that some of those candidates do not work.
• Cost per good die. wafer cost ÷ good dies per wafer. This is the first number with real meaning, because a die that fails test cannot be sold and its share of the wafer is simply lost. It is still only the manufacturing cost of bare silicon.
• Cost per transistor. Historically the headline figure for scaling progress, and genuinely useful for comparing process technologies. But a product does not ship transistors. Cost per transistor can improve while cost per good die and total product cost both rise.
• Total product cost. What it actually costs to put a finished part in a customer's hands: the good die, plus wafer probe and final test, packaging and assembly, any substrate or interposer, assembly yield loss, and the amortised share of everything spent before production began.

Each is a legitimate quantity. The error is sliding between them mid-argument — quoting an improvement in the first or fourth and concluding something about the fifth.

3. From Good Dies to Cost per Good Die

The previous chapter already established the denominator, so there is no need to rebuild it:

good dies ≈ gross candidate dies × yield

Recall why each term punishes a large die independently. Gross dies falls because a bigger rectangle simply fits fewer times into a fixed circle, made worse by edge loss where dies overhang the wafer boundary — pure geometry, true even on a hypothetically perfect process. Yield falls because a larger die presents more area to random defects, and it does so exponentially in area rather than proportionally.

Now add the numerator. Wafer processing cost is incurred per wafer, essentially independent of how that wafer was diced. So:

manufacturing cost per good die ≈ wafer processing cost ÷ good dies per wafer

and substituting the relation above:

≈ wafer processing cost ÷ (gross dies × yield)

4. A Worked Example

Every number below is hypothetical, chosen for clean arithmetic. They are not measurements of any process, node, or company, and no real wafer price or yield figure appears anywhere in this chapter.

Take two designs on the same hypothetical process, so the wafer costs the same to run either way. Say a wafer costs $10,000 to process — an illustrative round figure.

Work it through: 300 × 0.80 = 240, and $10,000 ÷ 240 = $41.67. Then 75 × 0.40 = 30, and $10,000 ÷ 30 = $333.33.

The structure is the lesson. Four times the die area produced eight times the cost per good die, and the factor of eight decomposes exactly:

• 4× fewer candidates — geometry, because a 4× larger rectangle fits a quarter as often.
• 2× lower yield — defect exposure, because more area means less chance of being clean.
• 4 × 2 = 8× fewer good dies, from an identically priced wafer.

Another way to see the same thing: Design A consumes 300 × 200 ÷ 240 = 250 mm² of processed wafer per good die, while Design B consumes 75 × 800 ÷ 30 = 2000 mm² — eight times the silicon per shipped part.

Note that the yield figures are not arbitrary. Chapter 1.3's model says doubling area squares the yield, so a design at 80 % scaled to 4× area lands at 0.80⁴ = 41 %, which is what the rounded 40 % represents. The example is consistent with the previous chapter rather than a fresh invention.

5. The Numerator Moves Too

Everything so far has attacked the denominator. But wafer processing cost is not fixed across technology generations either, and this is the step beyond the previous chapter.

Manufacturing at a leading-edge node is more involved than at a mature one: more process steps, more complex lithography and patterning strategies, more masks in the set, tighter control requirements, and extremely capital-intensive equipment whose cost is recovered through what it produces. The direction is not controversial — advanced-node wafers are more expensive to process than mature-node wafers.

Two disciplined statements follow, and the discipline matters:

• Cost per transistor can still improve while cost per wafer rises. These are compatible: if density improves by more than wafer cost does, the cost of a unit of logic falls even as the wafer gets pricier. This is why "the newest node is more expensive" and "the newest node is cheaper per transistor" can both be true, and why arguing about which one is the truth is a category error.
• But the product pays for wafer area, not for transistors. If a design's area does not shrink proportionally with the density improvement — because the architecture grew, or because parts of it do not scale well — then a more expensive wafer is being divided among a similar number of dies, and cost per good die rises regardless of what happened per transistor.

What I will not do here is attach numbers. Real wafer prices, mask-set costs, and per-node cost multipliers are commercially sensitive, vary by customer, volume, and agreement, and are widely misquoted. The qualitative structure above is what you can reason with; a number you cannot source is worse than no number.

6. The Cost Before Unit One — NRE and Volume

Everything so far is recurring cost: spend it again for every wafer. Semiconductor products also carry a large non-recurring engineering (NRE) cost — spent once, before a single unit ships, and paid whether the product sells one unit or ten million.

Conceptually NRE covers the design itself, functional verification, physical implementation and closure, the mask set, IP licensing and design enablement, silicon bring-up and validation, and for many products the software and firmware work needed to make the part usable. Companies classify these differently and not everyone counts the same things as NRE — the label matters less than the property that defines it:

Fixed cost does not shrink with volume. It gets divided by it.

The simplified model is exactly that division:

NRE per shipped unit ≈ total NRE ÷ shipped volume

Take a hypothetical $100 million programme — again an illustrative figure, not a claim about any real design:

The silicon is identical in both rows. The manufacturing cost per good die is identical. The product economics are not remotely the same — a hundredfold difference from volume alone. This is why the same architecture can be obviously correct for one company and obviously wrong for another, and why "is this design good?" is an incomplete question without "at what volume?"

It also explains why NRE rising at advanced nodes matters so much. Published academic cost modelling reports that moving across several generations reduced logic area substantially while design NRE rose several-fold over the same span — the two moved in opposite directions. A higher fixed cost raises the volume a product must reach before it makes sense at all, which quietly excludes lower-volume products from the leading edge regardless of whether they would benefit technically.

7. One Process for Every Function — and the Reuse Question

Chapter 1.1 established that different functions benefit unevenly from an advanced node. Here is the economic consequence of that, which is sharper than the technical one.

A monolithic die is manufactured on one process. Every block on it therefore inherits that process's economics — its wafer cost, its mask set, its design rules — whether or not that block gains anything in return. Dense digital logic typically gains substantially. Other functions, including memory arrays, analog and mixed-signal circuits, and high-speed I/O and PHYs, generally gain less, because their area and behaviour are governed more by matching, voltage headroom, and physical interface requirements than by logic density.

State that carefully. It does not mean those functions cannot be built at advanced nodes — they routinely are — nor that they never improve. The defensible claim is narrower: different functions do not necessarily receive the same cost-per-function benefit from the most advanced available process, so committing all of them to one process means some blocks pay leading-edge cost for a return that does not justify it.

Reuse compounds this. With a monolithic design, the die is the unit of reuse. A product family wanting several compute configurations, several I/O capabilities, or different accelerator mixes generally needs new integrated designs or variants — and each variant carries its own share of design, verification, and mask cost. A modular, die-level approach can change which pieces must be redesigned and which existing designs and masks can be carried across products, so fixed cost is amortised over a family rather than a single product.

Be careful with that claim too. It does not follow that a chiplet approach automatically reduces NRE. A multi-die programme adds its own engineering: interface design and verification, integration and assembly development, package design, and validation of combinations. What changes is the structure of the fixed cost and what it can be spread across — not a guarantee that the total falls.

8. Manufacturing Cost Is Not Product Cost

Cost per good die is bare silicon. A finished part still owes wafer probe and final test — real equipment time per unit, and more of it for a part with demanding coverage requirements — plus packaging, assembly, any substrate, interposer, or bridge, and the yield lost during assembly itself.

That last item is where the tempting conclusion breaks. Someone who has understood the previous chapter will reason: smaller dies yield better, so chiplets must be cheaper. The first half is right and the inference is not, because a multi-die product adds terms the monolithic one never had:

• Die-to-die interface area and power. Every die needs PHY and controller logic to talk to its neighbours. Academic analyses note that inter-die communication carries higher area and power overhead than intra-die communication, and that the total silicon area of a chiplet system exceeds its monolithic counterpart because of those interfaces and duplicated infrastructure. You buy back yield and spend some of it on area.
• Package and interconnect cost. Advanced substrates, interposers, and bridges are not free, and published modelling puts chiplet packaging cost meaningfully above the monolithic equivalent, with bonding yield a dominant contributor.
• Assembly yield. Note where it sits in the cost structure quoted in §3: assembly yield divides the whole bracket. A failed assembly can destroy every die in it, including good ones — which is precisely why known-good-die screening exists, and why it means more test, not less.
• Latency, bandwidth, and power across the boundary. A crossing that used to be an on-die wire now costs something to traverse.

So the honest formulation, and the one this module is built to produce:

Chiplets change the cost equation. They do not automatically lower it.

Published cost-modelling work supports both halves of that: it reports substantial cost reductions from technology heterogeneity in favourable cases, while also stating plainly that the potential benefits of disaggregation are not always realised and depend strongly on how the system is partitioned. Whether the total improves is a design-specific question, not a slogan.

9. Why This Matters in Real Engineering Work

• SoC architects set most of this before RTL exists. Die area, process choice, how the product family is segmented, and what gets reused are architectural decisions with direct manufacturing-cost consequences — and they are hard to revisit later.
• RTL engineers should internalise that a block is not free. More functionality means more gates, state, memory, and interfaces, and eventually more area. When economics force a partition, those boundaries become interfaces the RTL has to define and honour.
• Verification engineers own a large share of NRE. Verification is one of the biggest engineering investments in a programme, which is what makes a proven, reusable block or interface economically valuable rather than merely convenient — the cost avoided is fixed cost, and fixed cost is what volume has to absorb.
• Physical-design engineers determine whether the economic assumptions survive contact with implementation. Area growth during closure, memory structure, power delivery, and floorplan decisions all move the die size the whole cost model was built on.
• DFT, test, and product engineers control terms that sit outside the die-yield equation entirely: test coverage and test time, binning strategy, and known-good-die screening. On a multi-die product these stop being downstream concerns and become part of whether the architecture works economically at all.

10. Common Misconceptions

11. Understanding Check

12. Summary

Five quantities that get spoken as one: cost per wafer, paid per wafer regardless of dicing; gross die cost, which assumes every die works; cost per good die, which counts only survivors; cost per transistor, historically the headline for scaling and not what a product ships; and total product cost, which adds test, packaging, assembly, and amortised fixed cost. Most bad reasoning in this area is a slide between two of them.

The manufacturing chain is short. good dies ≈ gross dies × yield from the previous chapter, and then cost per good die ≈ wafer cost ÷ (gross dies × yield). A larger die attacks that denominator twice and independently — fewer candidates by geometry, fewer survivors by defect exposure — so cost per good die rises faster than area alone implies. In the hypothetical example, 4× the area gave 4× fewer candidates and half the yield: 8× the cost per good die from an identically priced wafer. Take the mechanism from that, not the multiplier.

The numerator moves too. Advanced nodes cost more per wafer, which is compatible with cost per transistor still improving — the two are different ratios, and only one of them is what a product buys. And beyond recurring cost entirely sits NRE: design, verification, implementation, masks, and bring-up, spent before unit one and divided by shipped volume. A hypothetical $100M programme is $10,000 per unit at 10,000 units and $100 at a million. The same silicon; incomparable economics.

Two structural consequences set up everything that follows. A monolithic die makes every block inherit one process's economics, even blocks that gain little from it. And it makes the die the unit of reuse, so a product family tends to need new integrated designs rather than recombined pieces. Both push toward partitioning — while chiplets change the cost equation rather than automatically lowering it, because die-to-die interfaces, packaging, assembly yield, and known-good-die testing all move onto the balance sheet the moment a product becomes multi-die.

13. What Comes Next

Four chapters have now each supplied one pressure against the ever-larger monolithic die: scaling benefits that no longer arrive together, a lithographic ceiling, yield that degrades with area, and economics that punish area twice over while fixed costs demand volume. Each was presented on its own. The obvious next question is what they do collectively, and whether the problems with monolithic integration are only about cost:

• 1.5 — Monolithic-SoC Limitations — the structural problems of putting an entire system on one die, beyond the manufacturing and economic pressures covered so far.

That is the chapter that assembles the case rather than adding to it. Browse the full path on the UCIe tutorials index.