The Moore's-Law Slowdown

For roughly four decades, a semiconductor architect facing a hard problem had one reliable answer: wait for the next process node. Transistors got smaller, more of them fit in the same area, and the resulting chip was — near enough — faster, lower-power, and cheaper per function than the one before it. That single expectation shaped how systems were designed. You built one large die, put everything on it, and trusted the next node to pay for the next generation's ambition. That expectation is no longer safe. Not because transistors stopped shrinking — density still improves — but because the bundle of benefits that used to arrive together has come apart. This chapter is about that unbundling, because everything the rest of this curriculum covers (chiplets, packaging, die-to-die links, and eventually UCIe itself) is a response to it. Skip it, and UCIe looks like an arbitrary specification. Understand it, and UCIe reads as the industry's answer to a problem you can see forming.

1. The Bargain That Used to Hold

Start with what "scaling" actually bought, because the popular summary compresses four distinct effects into one word.

Shrinking transistor dimensions gave engineers four things at once:

• More transistors per unit area — you could put more function on the same silicon.
• Faster switching — smaller devices with shorter channels switch more quickly, so higher clock frequencies were reachable.
• Lower energy per switching event — a smaller device drives less capacitance, and operating voltages could be reduced alongside the dimensions.
• Falling cost per transistor — more transistors came out of each processed wafer, so the price of a unit of logic fell generation over generation.

Those four are related — they all follow from making things smaller — but they are not the same effect and they do not have to arrive together. For a long time they did, which is why the whole bundle got informally filed under one name. The slowdown this chapter describes is not the death of the first item. It is the progressive decoupling of items two, three, and four from item one.

2. What Moore's Law Actually Says — and What It Does Not

Gordon Moore's 1965 observation, refined in 1975, was about the number of components economically integrated on a single chip roughly doubling on a regular cadence — an observation about integration density and the economics of manufacturing it, not a law of physics and not a promise about delivered system performance.

That distinction matters more than it sounds. Precision here is what separates an engineer from someone repeating a slogan:

• Transistor count vs transistor density. Count is how many transistors a particular product has. Density is how many fit per unit area. A chip can gain count by growing larger — which costs money and, as the next chapter shows, runs into a hard physical ceiling — without any density improvement at all. Moore's observation is fundamentally about density-driven economics.
• Performance vs frequency. Delivered performance is work completed per unit time on a real workload. Frequency is one input to that. More transistors can be spent on caches, wider issue, more cores, or accelerators — none of which improve performance unless the workload can use them.
• Power scaling. Whether the additional transistors can all be operated at full speed within a fixed power and thermal budget is a separate question from whether they fit. §3 is entirely about that question.
• Cost scaling. Whether the cost per transistor falls depends on wafer cost, process complexity, defect density, and the fixed engineering cost of designing at that node — not on density alone.

Moore's Law is a density-and-economics trend. It was never a guarantee that each generation makes a whole chip faster, cooler, and cheaper. For a long stretch it looked like one because a second, separate scaling relationship was quietly doing that work — and that relationship is the one that broke first.

3. Dennard Scaling and the Power Problem

The reason the shrink used to feel free is a scaling relationship described by Robert Dennard and colleagues in 1974. Its intuition, stripped of the device physics: if you scale a transistor's physical dimensions down and scale the supply voltage down by a comparable factor, then the power consumed per unit of chip area stays roughly constant even though there are now far more transistors in that area. You get more devices, running faster, in the same power envelope. That is the "free lunch" the industry lived on.

Why voltage is the pivotal term is visible in the dominant power component for switching logic:

P_dynamic ∝ C × V² × f

Read physically: every time a gate switches, it charges and discharges capacitance C through a supply of V volts, and this happens f times per second. The energy per switching event scales with the square of the voltage, so voltage is the strongest lever in the expression. Halving V, all else equal, cuts dynamic power to roughly a quarter. That quadratic term is precisely what paid for higher frequency and higher device counts at the same time — you could afford to raise f because V² was falling.

Two things eroded that.

Supply voltage stopped scaling as aggressively. A transistor's supply voltage cannot be reduced indefinitely without reducing its threshold voltage — roughly, the voltage at which it turns on — and the device must still switch reliably and quickly. But lowering the threshold voltage makes the device leak more when it is nominally off. That leakage (or static) power is consumed continuously, whether or not anything is switching, and it is not paid for by doing useful work. Dynamic power and leakage therefore pull in opposite directions: pushing voltage down to save dynamic power pushes leakage up. The industry hit a regime where voltage scaling slowed sharply, and with it the V² discount.

Power density became the binding constraint. With V no longer falling in step with dimensions, packing more, faster-switching transistors into the same area raises the power dissipated per square millimetre. A chip must get that heat out through its package and cooling solution, and that path has a fixed budget. Once power density hits the cooling limit, you can no longer operate everything on the die at full speed simultaneously — the limit is thermal, not logical.

The industry's visible response, in the mid-2000s, was to stop chasing single-thread frequency and spend the extra transistors on multiple cores and parallelism instead. That was a rational move: more cores at a moderate clock can deliver more total throughput within a fixed power budget than one core clocked as high as physics and cooling allow. But it moved the burden onto software — parallel work only helps if the workload is parallel — and it made the disconnect explicit. From that point on, "more transistors" and "proportionally more delivered performance" were formally different things.

4. The Economics Changed Too

If power were the only issue, the answer might still be "take the next node and accept a modest gain." The second force is economic, and it applies even to teams whose designs are not power-limited.

Leading-edge manufacturing has become substantially harder, and difficulty translates into cost across several independent axes:

• Process complexity. Modern devices are three-dimensional structures with tightly controlled materials and many more processing steps than earlier planar generations. More steps means more equipment time, more variability to control, and more opportunity for defects.
• Lithography complexity. Printing features far smaller than the exposure wavelength required increasingly elaborate techniques — resolution-enhancement methods, and splitting one layer across multiple exposures (multi-patterning). Extreme-ultraviolet lithography relieves some of this at the cost of very expensive tooling. Either way, the per-layer cost of patterning has risen.
• Mask and NRE cost. A design at a leading node needs a mask set for its many layers, and that cost is paid up front, before a single good part ships. The higher this fixed cost, the more volume a product needs before it is economically sensible at all.
• Design and verification effort. More transistors mean more logic to design, integrate, and verify. Verification effort does not scale linearly with gate count — state space grows far faster than area, and the schedule cost of closing coverage on a very large SoC is a first-order project risk.
• Physical-design closure. Timing, power, IR-drop, and signal-integrity closure on a very large die is iterative and slow. Each turn of the loop consumes engineering time and compute, and the loop gets longer as the die grows.

None of this means advanced nodes are a bad deal. For the right function — dense, high-activity digital logic in a high-volume product — a leading node is still clearly worth it. What changed is that the deal is now conditional. Cost per transistor may fall at a new node, but total product cost also includes the mask set, the design and verification programme, and the yield on a large die. Any of those can dominate. The reflexive answer "newest node, therefore cheaper" stopped being reliable.

5. Not Every Function Benefits Equally

The fourth force is the one that most directly sets up the rest of this curriculum, and it is the piece newcomers usually miss.

A modern SoC is not a uniform sea of logic. It contains functions with genuinely different implementation characteristics:

• Dense digital logic — CPU cores, GPU shaders, accelerator datapaths — is where advanced-node density and speed pay off most directly. This is the classic beneficiary of scaling.
• Memory arrays such as SRAM are area-critical and are built from carefully engineered bit cells rather than ordinary standard-cell logic. Their area scaling has, in recent generations, been widely reported to lag behind logic scaling — so the fraction of the die spent on memory tends to grow even as logic shrinks.
• Analog and mixed-signal circuits depend on device matching, voltage headroom, and noise behaviour rather than on raw switching density. A smaller geometry with a lower supply voltage does not automatically improve them, and can make some of them harder to design.
• High-speed I/O and PHYs are dominated by driver strength, electrical interfaces to the outside world, and physical bump and pad structures. They occupy area that is set largely by those physical requirements, not by logic density.

Put those together and the conclusion is uncomfortable for the monolithic model: if you build one die at one process node, you have chosen a single technology for every function on it. Whichever node you pick, some blocks get a technology that is a poor fit — you either pay leading-edge cost for functions that gain little from it, or you hold back functions that would have gained a lot.

Note carefully what this does not say. It does not say analog "cannot" be built at advanced nodes, or that memory has stopped scaling. Both claims would be too strong. The defensible statement is narrower and sufficient: the benefit of moving to a leading-edge node is uneven across the functions in a large system, and that unevenness has grown.

6. From Scaling Pressure to Architectural Pressure

Here is the causal chain in one view. Read it as pressure accumulating, not as a single failure.

The chain ends at a question, and the change in the question is the whole point. The monolithic-scaling era asked: how much more can we fit on one die? The pressures above force a second, different question alongside it: which technology should each function be implemented in, and how do we then compose those pieces into one system?

That is a shift from technology scaling — improve the system by moving it to a better process — to architectural scaling — improve the system by changing how it is decomposed and integrated. Both still matter. The point is that architects now need both levers, where one used to be enough.

An architect reasoning this way is really recording an intent per function, well before any RTL is written:

// Conceptual — an architect's partitioning intent, not synthesisable code.
// The monolithic-era question was only "does it fit on one die?".
// The added question is "which technology suits each function?".
typedef struct {
  string function_name;    // e.g. "cpu_cluster", "sram_pool", "ddr_phy"
  string scaling_benefit;  // how much this function gains from a newer node
  string node_preference;  // leading-edge vs a mature, lower-cost process
} partition_intent_t;

The struct is a thinking aid, not a deliverable. What matters is that the columns exist at all: once a design records different technology preferences for different functions, a single die at a single node can no longer satisfy all of them, and the system has to be composed some other way.

7. Two Ideas Worth Keeping

Everything above condenses into two statements. If you retain nothing else from this chapter, retain these.

First: Moore's Law is a density trend, not a guarantee. More transistors per unit area does not entail a chip that is automatically faster, cooler, and cheaper. Density, delivered performance, power, and cost are four separate quantities. They moved together for a long time, and they no longer reliably do.

Second: when scaling benefits become uneven and expensive, the design question changes. Architects stop asking only how much more can we fit on one die and start asking where should each function be built, and how do we compose the result. That is a different kind of optimisation, and it operates on system structure rather than on process technology.

8. Common Misconceptions

9. Why This Matters in Real Engineering Work

This is not background reading. Each of the pressures above lands on a specific engineering decision.

• SoC architects must decide what stays on one die and what does not. That decision is now driven by cost per function and technology fit as much as by logical grouping — and every boundary drawn creates an interface with real latency, bandwidth, and power cost that must be budgeted up front.
• RTL engineers feel partitioning directly. A boundary that used to be an on-chip bus connection becomes a link with different timing and flow-control characteristics. Where you place a partition determines which paths cross it, how much buffering is needed, and how the design's clocking and reset behave around it.
• Verification engineers inherit a changed verification boundary. Blocks that were once verified together inside one integration environment may now be developed and verified separately, with a defined interface as the contract between them. That elevates interface-level verification, and it means integration bugs move to the boundary rather than disappearing.
• Physical-design engineers are affected by die size at every step. Timing and power closure on a very large die is a longer, more iterative process, and die size interacts directly with yield. Partitioning changes the closure problem rather than removing it — each piece gets easier while a new inter-die budget appears.
• Packaging and system engineers move from being downstream of architecture to being part of it. If a system is composed of several dies, packaging determines what interconnect density and reach are achievable, which in turn constrains what partitions are viable at all.

The common thread: once a system may be composed from more than one die, the decomposition itself becomes an engineering artefact — one that has to be designed, budgeted, verified, and closed like any other.

10. Understanding Check

11. Summary

Transistor scaling once delivered four benefits together — higher density, faster switching, lower energy per switching event, and falling cost per transistor — and that bundle made "move to the next node" a reliable answer to almost any system-level problem. Moore's observation described the first of those: integration density and the economics behind it, not a promise about delivered performance, power, or total product cost.

The bundle came apart in stages. Dennard-era voltage scaling weakened, and since dynamic power follows C × V² × f, losing the quadratic voltage discount meant more transistors switching faster now raise power density directly — while pushing voltage lower raises leakage instead. Power density met a fixed cooling budget, frequency flattened, and the industry spent extra transistors on parallelism, formally separating "more transistors" from "proportionally more performance". Manufacturing and design economics also hardened: process and lithography complexity, mask and NRE cost, verification effort, and physical-design closure all rose, so cost per transistor became only one term in a much larger total. And the remaining benefit is uneven — dense digital logic gains most, while memory arrays, analog, and high-speed I/O gain considerably less, which is a problem specifically because one monolithic die commits every function to one process node.

The result is a change in the question architects ask. Alongside how much can we fit on one die, they must now ask where should each function be built, and how do we compose the pieces. That is architectural scaling rather than technology scaling — and it is the pressure that eventually produces multi-die systems, chiplets, and the die-to-die interconnect problem UCIe was created to solve. Note the ordering carefully: UCIe is not a response to the scaling slowdown itself. It answers the connectivity and interoperability problem that appears once decomposition is already on the table.

12. What Comes Next

Scaling economics explains why architects want an alternative to one ever-larger monolithic die. It does not yet explain what stops them from simply building that larger die anyway. That is the next chapter's job:

• 1.2 — Reticle Size Limits — the hard physical ceiling on how large a single die can be manufactured, and what it means for the scope of one SoC.

From there, the module works through the remaining pressures one at a time — yield behaviour on large dies, cost scaling, the structural limits of the monolithic SoC, multi-die systems, and finally the chiplet approach itself — before any UCIe layer is named. Browse the full path on the UCIe tutorials index.

For a closely related piece of engineering reasoning in a different domain — a shared model that ran out and forced an architectural change rather than a faster version of the same thing — see Why AXI Exists on-chip, and Evolution of System Interconnects at the system level.