156Total chapters
28Modules
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Chiplet economics first
Moore's-Law slowdown, reticle limits, yield, cost — the engineering forces that produced chiplets before a single UCIe layer is named. The mental model the rest of the curriculum rides on.
Interview-ready depth
A dedicated interview module plus per-chapter interview weighting — streaming protocol, CXL-over-UCIe, flow control, link training, architecture tradeoffs, silicon-bring-up debug.
Design → verify → debug
Link / Protocol-engine / Adapter / PHY RTL pipelines, SVA / UVM verification, compliance, and trace-driven silicon debugging — the full engineering loop for a UCIe link.
UCIe Complete Curriculum
Your Learning Roadmap
156 chapters · 28 modules — chiplet interconnect — protocol / adapter / PHY layers and link training.
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Module 1
Why Chiplets Exist
1.1The Moore's-Law SlowdownPlanned1.2Reticle Size LimitsPlanned1.3Yield ChallengesPlanned1.4Cost-Scaling ProblemsPlanned1.5Monolithic-SoC LimitationsPlanned1.6Multi-Die SystemsPlanned1.7The Chiplet RevolutionPlanned
Module 2
Chiplet Architecture Foundations
2.1What Is a Chiplet?Planned2.2Compute ChipletsPlanned2.3IO ChipletsPlanned2.4Memory ChipletsPlanned2.5Accelerator ChipletsPlanned2.6Packaging FundamentalsPlanned2.7System PartitioningPlanned
Module 3
Why UCIe Exists
3.1Proprietary Die-to-Die LinksPlanned3.2The Interoperability ProblemPlanned3.3Industry StandardisationPlanned3.4The UCIe ConsortiumPlanned3.5The Ecosystem VisionPlanned
Module 4
UCIe Architecture Overview
4.1The UCIe Mental ModelPlanned4.2UCIe Layered ArchitecturePlanned4.3The UCIe Protocol StackPlanned4.4Link StructurePlanned4.5Die-to-Die Communication FlowPlanned
Module 5
The UCIe Stack
5.1The Protocol LayerPlanned5.2The Adapter LayerPlanned5.3The Physical LayerPlanned5.4Layer ResponsibilitiesPlanned5.5Layer InteractionsPlanned
Module 6
Package Architecture
6.1Organic SubstratesPlanned6.2Silicon InterposersPlanned6.3Intel EMIBPlanned6.42.5D PackagingPlanned6.53D PackagingPlanned6.6Advanced Packaging ConceptsPlanned
Module 7
UCIe PHY Fundamentals
7.1The Role of the UCIe PHYPlanned7.2Electrical SignallingPlanned7.3Lane ConceptsPlanned7.4Link WidthsPlanned7.5ClockingPlanned7.6Signal IntegrityPlanned
Module 8
Link Initialisation
8.1UCIe ResetPlanned8.2Link DiscoveryPlanned8.3Link TrainingPlanned8.4Link CalibrationPlanned8.5End-to-End Bring-Up FlowPlanned8.6Link StatesPlanned
Module 9
The Streaming Protocol
9.1The Streaming ModelPlanned9.2Streaming Packet TransportPlanned9.3Streaming OrderingPlanned9.4Streaming ReliabilityPlanned9.5Streaming Flow ControlPlanned
Module 10
PCIe Over UCIe
10.1PCIe Tunneling Over UCIePlanned10.2PCIe Packet TransportPlanned10.3Endpoint ConnectivityPlanned10.4Host-Side IntegrationPlanned
Module 11
CXL Over UCIe
11.1Why CXL MattersPlanned11.2Memory Expansion Over CXLPlanned11.3Cache Coherency Over CXLPlanned11.4CXL Transport on UCIePlanned11.5CXL-over-UCIe IntegrationPlanned
Module 12
Data Flow Through UCIe
12.1Request FlowPlanned12.2Response FlowPlanned12.3Data FlowPlanned12.4Transaction LifecyclePlanned12.5End-to-End Data-Flow ExamplesPlanned
Module 13
Flow Control
13.1Credit-Based Flow ControlPlanned13.2Buffer ManagementPlanned13.3BackpressurePlanned13.4Congestion HandlingPlanned13.5Throughput OptimisationPlanned
Module 14
Reliability and Error Handling
14.1Error DetectionPlanned14.2Error RecoveryPlanned14.3Retry MechanismsPlanned14.4Link RobustnessPlanned14.5Fault ManagementPlanned
Module 15
UCIe Performance
15.1Per-Lane / Per-Module BandwidthPlanned15.2Latency AnatomyPlanned15.3ScalabilityPlanned15.4Package-Level PerformancePlanned15.5Throughput AnalysisPlanned
Module 16
Coherency Concepts
16.1Shared Memory Across ChipletsPlanned16.2Cache Coherency in ChipletsPlanned16.3Chiplet-Level CoherencyPlanned16.4UCIe and CHIPlanned16.5UCIe and CXLPlanned
Module 17
Memory Systems
17.1Memory ChipletsPlanned17.2Memory ExpansionPlanned17.3Near-Memory ComputePlanned17.4HBM IntegrationPlanned17.5Future Memory ArchitecturesPlanned
Module 18
AI and Accelerator Systems
18.1AI ChipletsPlanned18.2Accelerator FabricsPlanned18.3Heterogeneous ComputePlanned18.4Large-Package SystemsPlanned
Module 19
UCIe RTL Design Thinking
19.1Link ArchitecturePlanned19.2Protocol EnginesPlanned19.3Adapter DesignPlanned19.4UCIe BufferingPlanned19.5Flow-Control LogicPlanned19.6Reusable UCIe IPPlanned
Module 20
UCIe Verification
20.1Protocol VerificationPlanned20.2Link VerificationPlanned20.3UCIe AssertionsPlanned20.4UCIe ScoreboardsPlanned20.5UCIe Functional CoveragePlanned20.6UVM Architecture for UCIePlanned20.7UCIe Compliance TestingPlanned
Module 21
UCIe Debugging
21.1Link Bring-Up FailuresPlanned21.2Training FailuresPlanned21.3Flow-Control BugsPlanned21.4Credit IssuesPlanned21.5Throughput IssuesPlanned21.6Protocol ViolationsPlanned21.7UCIe Silicon DebugPlanned
Module 22
UCIe in Real Products
22.1Intel Chiplets on UCIePlanned22.2AMD Chiplets on UCIePlanned22.3AI Accelerators on UCIePlanned22.4Data-Centre ProcessorsPlanned22.5Future SoCsPlanned
Module 23
UCIe vs Other Interconnects
23.1UCIe vs PCIePlanned23.2UCIe vs Proprietary D2DPlanned23.3UCIe vs Infinity FabricPlanned23.4UCIe vs NVLinkPlanned
Module 24
Future of Chiplet Computing
24.1Open Chiplet EcosystemsPlanned24.2The Chiplet Marketplace VisionPlanned24.3Modular Semiconductor DesignPlanned24.4Future ArchitecturesPlanned
Module 25
UCIe Interview Mastery
25.1What Is UCIe?Planned25.2Why Chiplets?Planned25.3The UCIe LayersPlanned25.4The Streaming ProtocolPlanned25.5CXL Transport on UCIePlanned25.6UCIe Flow ControlPlanned25.7Architecture TradeoffsPlanned25.8Senior VerificationPlanned25.9Senior DebuggingPlanned25.10Product IntegrationPlanned
Module 26
Real Industry Case Studies
26.1AMD EPYC Case StudyPlanned26.2Intel Meteor Lake Case StudyPlanned26.3AI Accelerator PackagesPlanned26.4HBM-Based SystemsPlanned26.5Multi-Die SoCsPlanned
Module 27
UCIe Design-Review Checklist
27.1Architecture Review ChecklistPlanned27.2RTL Review ChecklistPlanned27.3Verification Review ChecklistPlanned27.4Performance Review ChecklistPlanned27.5Integration Review ChecklistPlanned27.6Debug Review ChecklistPlanned27.7Interview Review ChecklistPlanned
Module 28
UCIe Misconceptions Engineers Have
28.1“UCIe Replaces PCIe”Planned28.2“UCIe Is Only a PHY”Planned28.3“Chiplets Are Always Cheaper”Planned28.4“UCIe Automatically Provides Coherency”Planned28.5“Packaging Is Separate from Architecture”Planned28.6“UCIe Is Only For CPUs”Planned