Why Chiplets?

Chapter 25.1's answer rested on one sentence of background: dies stopped getting bigger. This chapter is that sentence as its own question — and it is asked more often, because it is harder to fake.

1. The One-Sentence Model

"Why chiplets?" is an economics question wearing a physics costume. The physics sets a hard ceiling; the economics is what actually forced the change — and a candidate who only knows the physics gives an answer that collapses on the first follow-up.

The tell is immediate. "Moore's Law is slowing" is what most candidates say, it is not wrong, and it does not answer the question asked — because a slowing cadence explains why chips got more expensive, not why splitting one die into four is the response (§4).

2. What This Chapter Owns

25.1 taught the shape of an answer and this chapter does not repeat it. What is new is the argument itself — three independent reasons (§5), the arithmetic that makes the strongest one concrete (§6–§7), and the costs a senior candidate volunteers unprompted (§10).

3. What You Can Safely Assert

4. Why "Moore's Law Is Slowing" Fails

It is true, it is relevant, and on its own it loses you the question. Here is exactly how.

CANDIDATE:    "Moore's Law is slowing down, so the industry moved to chiplets."
 
INTERVIEWER:  "Slowing how? And why does that lead to splitting a die rather
               than just... making a smaller chip, or waiting for the next node?"
 
CANDIDATE:    [no answer, because the claim was a headline, not an argument]

Three properties.

The follow-up is obvious and standard. Any interviewer who asks this question has heard "Moore's Law" fifty times and has a prepared next question, so the phrase is closer to a trap than an answer.

The claim is also imprecise. "Slowing" conflates several distinct things — density scaling, cost-per-transistor, power scaling — and being asked which one you mean is a bad moment if you have not decided.

And crucially, it does not imply chiplets at all. A slowing cadence is equally consistent with "chips get more expensive and we accept that" — so the argument is missing its middle (§5).

5. Three Independent Reasons

The strong answer has three legs, and the point is that they are independent: any one would push toward chiplets, and all three apply at once.

Four readings.

Reason 1 is a wall, not a slope. It is the cleanest thing to say because it admits no argument: beyond it you cannot build the chip at all, whatever your budget.

Reason 2 is the one that does the most work in practice, because it bites well before the wall — and it is the one you can make quantitative aloud (§6), which is what separates a memorised answer from an understood one.

Reason 3 is the one most candidates omit, and it is the reason chiplets are attractive even for designs that would fit comfortably on one die. It also sets up §9's follow-up.

And their independence is the answer to §4's interviewer. "Why not just make a smaller chip?" — because reason 3 says you would still want to split it, and reason 2 says you would still be paying for area you did not need.

6. The Yield Argument, Properly

This is the part you should be able to do aloud. Symbolic, because the real numbers are not yours to quote (§3).

ILLUSTRATIVE MODEL — the standard simple form. Numbers are ASSUMED, chosen
to make the arithmetic legible. Do not present these as real figures (§3).
 
  Simple Poisson yield model:      Y  =  e^(-D x A)
 
    D = defect density (defects per unit area)
    A = die area
 
  Take a large monolithic die:     A = 4 units
  Assume a defect density where:   D x A = 1.0  for the whole die
 
    Y_monolithic = e^(-1.0)  =  0.37     -> ~37% of dies good
 
  Now split the SAME total area into four chiplets of A = 1 unit each.
  Each has one quarter of the defect exposure:
 
    Y_chiplet    = e^(-0.25) =  0.78     -> ~78% of chiplets good
 
  So per unit of good silicon, the chiplet approach yields roughly
  TWICE as much.
 
  THE HONEST CAVEAT — and say it:
    You need all four chiplets to work to build one product, so naively
    0.78^4 = 0.37, the same number. The gain is NOT arithmetic magic.
    It comes from three things:
      1. you can TEST and BIN chiplets before assembly and discard bad
         ones cheaply, instead of discarding a whole large die
      2. a defect costs you a SMALL die, not a large one
      3. you can harvest partially-good die by binning down

Five readings, and the caveat is the most important part.

The 0.78⁴ = 0.37 observation is the follow-up you will be asked, and a candidate who has not thought about it is caught flat. Volunteering it yourself is a strong move — it shows you did not just memorise "small dies yield better."

The real gain is known-good-die testing: you discard a bad small die for the cost of a small die, rather than losing a large one at the very end.

Binning matters too. A large monolithic die with one defective core may be unsellable or heavily downgraded; a chiplet design discards one small die and keeps the rest.

The model is deliberately the simple Poisson form. Real yield models are more elaborate, and saying "the simple model is Y equals e to the minus D A" is exactly right — it signals you know it is a model.

And the exponent is what makes the argument. Yield falls exponentially in area, so the penalty is not linear — which is why "just make it a bit smaller" is not a strategy (§9).

7. A Worked Ninety-Second Answer

SCRIPT — ~200 words, ~90 seconds. Three legs, one caveat, one consequence.
 
  "There are three separate reasons, and they all landed around the same
   time.
 
   The first is a hard physical limit: there's a maximum area a single
   exposure can pattern, so there's a ceiling on how big one die can be.
   Past that you physically can't build it.
 
   The second is yield, and this is the one that bites earliest. Yield
   falls exponentially with die area — the simple model is e to the minus
   defect-density times area. So a very large die has a poor yield, and
   the loss when you scrap one is large. If you split the same function
   into smaller dies you can test them individually, throw away a small
   bad die cheaply instead of a big one, and bin around defects.
 
   The third is that not every block wants the same process. Dense logic
   benefits a lot from a leading node; analog and I/O generally don't, so
   paying leading-node cost for them is wasted.
 
   Put together, you split the design into chiplets in one package. But
   that immediately creates a new problem — the dies have to talk to each
   other — and that's the interconnect problem UCIe addresses."
 
  [STOP.]

Four things this script does deliberately.

It never says "Moore's Law." Not because the phrase is wrong, but because the three concrete reasons are strictly better and leave nothing for §4's follow-up to attack.

It puts yield second and marks it as the one that bites earliest — which is both true and the leg you can defend quantitatively if pushed.

It says "the simple model is", which frames it correctly as a model (§3) and invites a quantitative follow-up you are prepared for (§6).

And the last sentence hands over the interconnect problem, which is the natural bridge if this is a UCIe interview — you have set up your own next question (25.1 §12).

8. Follow-Up — "Why Not Just Make Smaller Monolithic Chips?"

The standard second question, and it is a good one.

And the answer that closes it: "Because the requirement is a fixed amount of function, not a fixed area. If you need that much silicon, your options are one big die or several small ones — and several small ones test better, bin better, and let you put each function on the process it actually wants."

That sentence contains all three legs (§5) and is roughly fifteen seconds.

9. Follow-Up — "So Why Isn't Everything Chiplets?"

The question that separates candidates who learned the argument from those who understand the trade — and volunteering the costs before being asked is stronger still.

And the closing sentence: "So it's a trade. If a boundary carries a lot of tightly-coupled traffic, splitting there can cost more than the yield saves — which is why partitioning is an architecture decision, not a manufacturing one."

That single sentence is the strongest thing in this chapter's material, because it shows you understand chiplets as a tradeoff rather than as a trend.

10. Junior, Mid, Senior

Two readings.

The senior row that matters most is "the costs." Anyone can list reasons chiplets are good; volunteering why they are not always good shows the candidate has weighed it rather than absorbed it.

And "framed as a hard wall" is a small thing with real signal. A candidate who says "past that you physically cannot build it" has understood the reticle limit is categorical, not economic — which is a distinction the imprecise answer never makes.

11. Sentences That Reveal a Gap

And the third row is the most instructive. It sounds like understanding, it is the natural conclusion from "small dies yield better," and it is arithmetically wrong — which is why §6 puts the caveat in the chapter rather than leaving it to be discovered in an interview.

12. If They Hand You a Pen

One curve, two marks, twenty seconds.

  yield
    1.0 |*
        |  *
        |     *                 Y = e^(-D*A)
        |        *
        |           *  *
        |                 *  *  *
    0.0 +--------------------------------  die area
         ^small        ^large      ^reticle limit
         chiplet       monolithic  (a WALL, not a slope)

Three properties.

The exponential shape is the whole argument. Draw the curve, mark a small die and a large one, and the steepness makes the point without a number.

Mark the reticle limit as a vertical wall, separate from the curve — because it is a different kind of constraint (§5), and showing that you distinguish them is worth more than the curve alone.

And do not label the axes with values (§3). "Defect density times area" on the exponent is enough; putting numbers on it invites a question about numbers you cannot source.

13. Follow-Ups You Have Invited

And the last row is the best hook in the chapter. "When would you not split?" invites the chattering-boundary answer — a dependent control loop across a die boundary that no buffer depth repairs — which is a genuinely senior thing to be able to describe.

14. The Second Quantitative Leg — Cost Per Transistor

§6 makes the yield argument concrete. This is the other number you should be able to reason about aloud, and it is the one that actually retires "Moore's Law" as a phrase.

ILLUSTRATIVE reasoning. No wafer, mask or process cost is quoted (§3) —
the SHAPE is the argument.
 
  Historically, each new node gave you:
      more transistors per unit area           (density)
    AND
      a lower cost per transistor              (economics)
 
  Those are TWO different things, and they used to arrive together.
 
  What changed is that density kept improving while cost per transistor
  improved much less — because a leading node brings:
      higher wafer cost
      more mask layers
      more expensive lithography steps
      longer, more complex process flows
 
  So: you can still put more transistors on a die.
      You just stop saving money by doing it.
 
  THE CONSEQUENCE, and this is the sentence that matters:
      If cost per transistor is roughly flat, then putting a block on the
      newest node has to be justified by PERFORMANCE, not by cost. And
      for blocks that gain little from the node — analog, I/O, some SRAM
      — that justification does not exist.
 
      That is reason 3 (§5), derived rather than asserted.

Four readings.

This is what people mean when they say Moore's Law is slowing — and saying it this way is strictly better, because it names which of the two trends decoupled (§4's imprecision problem, solved).

It derives reason 3 rather than stating it. Process affinity stops being a preference and becomes an economic consequence: if the node no longer pays for itself, you only put things there that need it.

It is also the answer to "why not wait for the next node?" (§8). The next node does not restore the coupling — so waiting does not solve the problem you have.

And it needs no numbers at all. "Density kept improving, cost per transistor didn't" is one sentence, is defensible (§3), and does more work than any figure you could quote.

15. A Worked Exchange

The follow-up chain, because this question is rarely asked alone.

INTERVIEWER:  "Why did the industry move to chiplets?"
 
YOU:          [§7's script — three reasons, ~90 seconds]
 
INTERVIEWER:  "You said yield falls exponentially. Show me."
 
YOU:          "The simple model is Y equals e to the minus D times A —
               defect density times area. So if a big die has D-times-A of
               about 1, that's e-to-the-minus-1, roughly 37 percent. Split
               the same area into four, each one sees a quarter of the
               exposure: e-to-the-minus-quarter, about 78 percent.
 
               But I should be careful — you need all four to build the
               product, and 0.78 to the fourth is 0.37 again. So the win
               isn't the arithmetic. It's that you can test and bin the
               small dies before assembly, so a defect costs you a small
               die instead of a large one, and you can harvest partial
               parts."
              [-> §6, including the caveat, volunteered]
 
INTERVIEWER:  "Good. So why isn't everything chiplets?"
 
YOU:          "Because splitting isn't free. A wire becomes a transport
               crossing — you pay latency twice per round trip, you pay
               energy, you add packaging and test cost, and every boundary
               becomes an interface you have to verify.
 
               The case where it really hurts is a tightly-coupled control
               loop. If two blocks exchange a small dependent update every
               cycle and you put a die boundary between them, the loop time
               becomes the throughput — and no amount of buffering fixes it,
               because buffering only helps when there's independent work
               to overlap."
              [-> §9, and 24.3 §9's chattering boundary, named]
 
INTERVIEWER:  "So how do you decide where to split?"
 
YOU:          "It's an architecture decision, not a manufacturing one. I'd
               want to measure the candidate boundary in a prototype first —
               traffic volume, but more importantly how dependent it is. If
               the maximum outstanding count is one, nothing can be issued
               while a response is in flight, and that boundary shouldn't be
               split whatever the node argument says."
              [-> 24.3 §10-11, a genuinely senior answer]

Four readings.

Every turn was invited. "Yield falls exponentially" invited the derivation; "it's a trade" invited "so how do you decide?" — the strongest question in the chain, and you asked for it.

The caveat was volunteered, not extracted (§6). That is the single highest-value move in the exchange: the interviewer was going to ask about 0.78⁴, and pre-empting it converts a potential stumble into a demonstration.

The last answer is the one that reads as senior, and notice its shape: it names a measurement rather than a rule of thumb. "Maximum outstanding of one" is concrete, testable and specific — which is what distinguishes an architect's answer from a summary.

And no number was quoted that could be wrong. The only figures are from the illustrative model, explicitly framed as one.

16. Analogies That Work, and Ones That Do Not

Two properties.

The glass analogy is the best one available, because it carries the mechanism rather than just the conclusion: you cut small, you inspect, you discard the bad pieces cheaply — which is exactly §6's caveat in everyday terms.

And the modularity analogy is the trap. It is the most natural thing for a software-background interviewer to reach for, and agreeing with it costs you §9 — the whole point is that in silicon a module boundary is nearly free and a die boundary is not.

17. If the Interviewer Pushes Back

Sometimes they will disagree, occasionally to see what you do.

Three properties.

Concede the true part first, every time. "That's fair" costs nothing and makes the narrowing that follows read as precision rather than defensiveness.

Never defend a claim you overstated. If you said "chiplets are cheaper" (§11) and are challenged, the correct move is to narrow it to "cheaper under these conditions" — not to hold the line.

And row 3 is the one worth disagreeing on. The reticle limit is a hard physical ceiling and process affinity is an economic consequence (§14); neither is a node-generation artefact — so this is a place where a candidate can politely and correctly hold a position, which interviewers notice.

18. Common Mistakes

Leading with "Moore's Law." §4: it is a headline, not an argument, and the follow-up is standard and prepared.

Giving one reason instead of three. §5: the three are independent, and their independence is what answers "why not just make a smaller chip?"

Claiming four small dies beat one big one arithmetically. §6: 0.78⁴ = 0.37. The gain is testing, binning and cheap discards — say so before you are asked.

Quoting a yield, reticle area or defect density. §3: process-, foundry- and generation-specific, and unsourceable in the room.

Never mentioning the costs. §9, §10: a candidate who cannot say why chiplets are not always right has not weighed the trade.

Treating partitioning as a manufacturing decision. §9: it is an architecture decision with a lifetime (24.3 §7).

Saying chiplets solve power. §11: they add link power. They help with cost, yield and process fit.

Not bridging to the interconnect. §7: the last sentence sets up your own next question in a UCIe interview.

19. Understanding Check

20. Summary

Five things.

It is an economics question wearing a physics costume (§1). The physics sets a ceiling; the economics forced the change.

Give three independent reasons (§5): a reticle wall, yield economics, and process affinity — and note that they are different kinds of constraint.

Be able to do the yield argument aloud (§6), symbolically, including the 0.78⁴ caveat — the gain is testing, binning and cheap discards, not arithmetic.

Volunteer the costs (§9, §10). "It's a trade, and here is when I would not split" is the strongest sentence available on this question.

And never lead with "Moore's Law" (§4). It invites a prepared follow-up and answers nothing on its own.