Silicon Interposers

Chapter 6.1 ended on a constraint. An organic substrate is a fine printed circuit board with a semiconductor's bump pitch landing on it, and its geometry — feature size, via structures, escape congestion, layer count — puts a ceiling on how many conductors can cross between two dies. Below that ceiling the substrate is the right answer, because it is cheap, mature, and has to be there anyway to deliver power and reach the board.

This chapter is about what happens above that ceiling. The move is drastic and, stated plainly, sounds absurd: put a piece of silicon under the silicon, purely so that the wiring between dies can be manufactured the way wiring inside a die is manufactured. It works, it is in volume production, and it buys a genuinely different class of connectivity. It also introduces a new physical object with its own area, power, thermal, yield, and cost behaviour — and, more importantly for a digital engineer, its own route graph that your RTL is quietly assuming.

1. The One-Sentence Model

A silicon interposer moves package routing into a silicon-like wiring environment, greatly increasing the number of connections possible between neighbouring dies — while adding a new physical structure that carries its own area, power-delivery, thermal, yield, and cost constraints.

Notice what that sentence does not say. It does not say "interposer = more bandwidth". Bandwidth is a consequence, and a conditional one. What the interposer changes is the wiring medium, and every architectural effect — wider links, richer topology, package-level memory, different partitioning — follows from that one change and is bounded by everything the change costs.

The failure mode of the shallow version is predictable. An architect who believes "interposer removes the package constraint" designs a connectivity graph that no interposer floorplan can embed, and discovers it after the die floorplans are frozen. The constraint did not vanish. It moved, changed units, and got harder to see.

2. The Physical Stack

Working downward from the top:

• The active dies — compute, I/O, accelerator, memory stacks. These are the system. They are attached face-down.
• Micro-bumps — the die-attach interface between each die and the interposer. These are much finer and far more numerous than the flip-chip bumps that attach a die directly to an organic substrate; fine pitch is the whole reason for the structure below.
• The silicon interposer — a piece of silicon carrying redistribution / routing layers patterned with semiconductor processing. This is where die-to-die connections actually run.
• Through-silicon vias (TSVs) where the architecture requires them — vertical conduits passing through the interposer body so that signals and power can continue downward.
• The organic package substrate — still present, still doing its 6.1 job: power distribution, global routing, and reaching the package's external connections.
• The PCB below that.

3. Why Silicon Routes Denser Than Laminate

Chapter 6.1 explained why organic laminate is coarse: its features are patterned by processes with far larger minimum geometry than lithography on silicon, its vias and capture pads consume lateral space, and its layer-to-layer alignment tolerance forces conservative spacing. Every one of those limits relaxes when the routing medium is a silicon wafer running in a semiconductor fab.

The mechanism, in the order it matters:

1. Feature size. Interconnect on silicon is patterned with the same lithography that patterns on-die metal. Line and space shrink by a large factor relative to laminate, and connections-per-unit-width scales directly with that.
2. Via structure. Vias in silicon interconnect are small and can be stacked and placed densely; laminate microvias need capture pads and keep-out that consume far more area than the via itself.
3. Attach pitch. The interposer accepts micro-bumps, so the die can present its die-to-die interface at a much finer pitch than flip-chip attach to laminate allows. This is why UCIe's advanced-package track — which assumes exactly this class of structure — specifies a bump pitch of roughly 25–55 µm against roughly 100–130 µm for the standard package.
4. Distance. Because dies mounted on a common interposer sit close, the conductors are short. Short conductors have less loss and less delay, which is what makes a very wide, relatively slow, parallel interface efficient instead of wasteful.

Put the four together and the architecture flips from few and fast to many and short. UCIe encodes this directly: the standard-package module carries 16 data lanes, the advanced-package module carries 64, and the advanced-package channel is specified for reach up to roughly 2 mm where the standard package reaches up to roughly 25 mm. Same protocol, same layering, different physical operating envelope — because the medium changed.

The interposer converts the package from board-like routing toward chip-like routing. Everything else in this chapter is a consequence of that sentence, including the problems.

4. Lateral Routing Versus Vertical TSVs

This is the section to read twice, because the misconception it kills is nearly universal.

Ask what a signal actually does. A die-to-die signal leaving Die A goes down through a micro-bump into the interposer's top routing layers, travels laterally across the interposer to a landing under Die B, and goes up through a micro-bump into Die B. Total vertical travel: two micro-bumps. Total lateral travel: the distance between the dies. The interposer's routing layers did the work.

A through-silicon via does something else entirely. A TSV passes vertically through the silicon body of the interposer. Its purpose is to let something continue downward — most importantly power, which has to come up from the board through the substrate and through the interposer to reach the dies, and also any signal that needs to reach the outside world rather than the neighbouring die.

So:

5. What the Density Actually Buys

Higher connection density is an enabler, and it is worth being specific about what it enables:

• Wider links. More parallel lanes between a die pair, so more bandwidth at a given per-lane rate.
• More links. Several independent interfaces from one die, rather than one interface that everything shares.
• More neighbours. A die can maintain dense connections toward more than one other die.
• Cheaper bits. Short conductors in a dense medium move data at lower energy per bit — UCIe quotes roughly 0.25–0.5 pJ/bit for the advanced package against 0.5–1 pJ/bit for the standard package.

And now the part that keeps architects honest. Every additional connection still costs, on the die:

• PHY area — a wider interface is more silicon on both endpoints.
• Die-edge length — a D2D PHY wants perimeter, and perimeter is fixed by die size.
• Power — more lanes running is more active circuitry, even at better pJ/bit.
• Routing on the interposer — connections are not free there either; they compete for the same layers.
• Configuration and verification surface — every width and topology option is a state the design can be in and DV must cover.

The interposer does not remove the physical constraint. It moves the constraint — from "how many conductors can laminate carry" to "how much die edge, PHY area, power, and interposer routing area is available at this floorplan".

6. Topology Freedom, and Where It Ends

On an organic substrate, high-bandwidth die-to-die connection strongly prefers facing edges. Two dies placed with their PHY edges opposite each other, close together, give short escape routes and short conductors; almost anything else drives the route count or length past what laminate can carry. That preference is so strong it effectively dictates the floorplan.

A dense interposer relaxes that. With far more routing resource in the medium between the dies, the architect gains real choice:

• Point-to-point — the classic pair, still the cheapest thing to route.
• Hub and spoke — several compute dies each connected to a central system or I/O die.
• Local mesh — a die connected to more than one neighbour, giving alternate paths and better locality.
• Resource-centred — compute dies arranged around shared memory structures they all need to reach.

This is a real capability increase. It is also the point at which people over-claim, so state the limit precisely: the interposer has finite routing resource, and routes that cross each other compete. A connection from a die in one corner to a die in the opposite corner is long, consumes routing area across everything in between, and takes that area away from links that needed it more. All-to-all connectivity across many dies is not free; it is a routing problem that gets harder superlinearly.

7. The Route Graph Is Part of the Architecture

Here is the idea that separates a packaging chapter from an architecture chapter.

The interposer is not merely underneath the architecture. Its route graph is part of the architecture.

When you draw a line between two boxes in a system block diagram, on a monolithic die that line is a routing problem the physical-design team will solve internally. In a 2.5D system that line is a physical route on interposer metal, with a specific origin, a specific destination, a length, a width, and a claim on a shared resource. Which means the block diagram is now making physical assertions, and those assertions can be false.

Concretely, a logical connection determines and is determined by:

• Available width — how many lanes the route can actually carry given everything else routed nearby.
• Distance — which affects loss, delay, and therefore what per-lane rate the channel will hold.
• Contention — every route crossing a congested region makes the other routes there harder.
• PHY placement — the route has to start and end somewhere specific on each die.

The practical consequence is a process one: the connectivity graph and the package floorplan must be agreed together, early. A logical architecture signed off without a floorplan is a hypothesis.

8. Placement Still Matters

A common over-correction: "we are on an interposer, so placement is a mechanical concern". No.

• Facing edges still shorten every conductor in the link. Shorter is better for loss, delay, and energy — the interposer improved the medium, not geometry.
• Die edge is still finite. A die has a perimeter, the PHY needs a contiguous stretch of it, and two high-bandwidth neighbours both wanting the same edge is a real conflict.
• Placement determines route length and crossings. Two dies that talk heavily and sit far apart consume interposer routing across the whole span between them.
• Interposer area is not free (§11), so placements that spread dies out cost real money.

The design rule that falls out of this is the same one 6.1 gave, now with more room to work in: the pairs that exchange the most traffic should be adjacent, and adjacency remains a finite resource because a die has four edges and only so much of each.

9. Power Still Has to Get Through

Adding a routing layer does not deliver power. If anything, it complicates it.

Current from the board must travel: PCB → package substrate → through the vertical structures (TSVs where the interposer is in the path) → interposer distribution → micro-bumps → die. That is a longer series path than a die flip-chipped directly to a substrate, and it passes through a structure whose top layers are simultaneously full of dense signal routing.

Three consequences worth internalising:

1. Signal density competes with power delivery for the same layers and the same vertical structures. This is exactly the 6.1 lesson, one level up in density and therefore sharper.
2. Return paths need the same attention. A dense parallel interface needs clean references; references are conductors too, and they consume the same resource.
3. The failure presentation is indirect. Insufficient PDN quality shows up as a link that is marginal under load, or that trains and then degrades when the neighbouring die goes busy — not as a routing error, and not as anything an RTL simulation will ever show you.

10. Thermal Coupling Comes With Proximity

Proximity is the point of the whole exercise, and proximity has a thermal cost. Several high-power dies packed closely, on a shared structure, with a shared cooling solution, means:

• Dies heat each other. A hot accelerator raises the operating temperature of the compute die beside it.
• Placement becomes a thermal decision as well as a bandwidth decision, and the two can conflict — the pair you most want adjacent for bandwidth may be the pair you least want adjacent for heat.
• Sustainable power states may be coupled. The package may not be able to support every die at maximum activity simultaneously, which turns into a system-level arbitration question (Chapter 6.4 §14 takes this up properly).

No junction temperatures here — those are product- and cooling-specific, and inventing them would be worse than useless. The architectural consequence is what matters: performance states can become a shared, package-level resource rather than a per-die one.

11. The Interposer Is Itself a Die

A silicon interposer covering several dies plus memory is a large piece of silicon, and it obeys silicon's economics:

• It is manufactured in a fab, with wafer cost, process steps, and yield behaviour — the Chapter 1.3 defect model applies to it as it applies to anything else on a wafer.
• It is large in area, and area drives cost and yield exposure in the way 1.3 and 1.4 described.
• It is a simpler structure than a logic die — predominantly interconnect, patterned at far relaxed geometry compared with leading-edge logic — which is why the naive "a giant die must have terrible yield" intuition does not transfer directly.
• It has an area limit like anything patterned lithographically, which is why interposer size is a real design constraint and why the industry has invested in techniques to extend it.

The honest summary is a conditional one: an interposer adds a manufactured silicon component and therefore adds cost and manufacturing complexity relative to a laminate-only package, and how much depends on its size, its process, and the volume. What is not honest is either extreme — "interposers are cheap now" or "interposer yield is hopeless". Both are slogans.

12. Where Interposer Geometry Becomes RTL

Now the bridge that this curriculum exists to build.

At some point the package team signs off a floorplan. That signoff is a set of facts: which die pairs have a physical route, how many conductors each route can carry, and what per-lane rate the channel analysis supports. Those facts are not negotiable by RTL, and they arrive in the design as parameters.

// Illustrative package-to-RTL configuration — not UCIe normative signal naming.
package pkg_topology_pkg;
 
  // ── Facts signed off by package + SI analysis, not chosen by RTL ──────────
  localparam int NUM_DIES            = 4;
  localparam int NUM_LINKS           = 2;   // D2D links this die instantiates
  localparam int PKG_MAX_LANES [NUM_LINKS] = '{64, 32};  // per-link routed width
 
  // ── Choices RTL is allowed to make, inside those facts ───────────────────
  localparam int ACTIVE_LANES  [NUM_LINKS] = '{64, 32};
 
endpackage

Architecture. Two links exist on this die because the interposer floorplan provides two routes from it. The width of each is whatever the route could carry after escape routing, crossings, and power delivery took their share.

State. None yet — this is elaboration-time configuration. That is deliberate: these are static physical facts, and encoding them as parameters rather than registers means a violation is a compile error rather than a runtime surprise.

Cycle behaviour. None. Nothing here is sampled.

Contract. The PHY instantiation, the lane-mapping logic, and the bandwidth model in the fabric all read these numbers. Anything that assumes a width must derive it from here rather than restating it.

Failure. If ACTIVE_LANES exceeds PKG_MAX_LANES, the design enables lanes that have no conductor. In simulation, where the channel is ideal, it works perfectly. In silicon, those lanes never train — or worse, train marginally and fail under thermal or voltage stress, producing an intermittent that looks like a PHY problem.

DV. Catch it at elaboration, not at runtime:

// Illustrative — elaboration-time legality check.
generate
  for (genvar L = 0; L < NUM_LINKS; L++) begin : g_width_legal
    if (ACTIVE_LANES[L] > PKG_MAX_LANES[L])
      $fatal(1, "Link %0d configured for %0d lanes; package routes %0d.",
                L, ACTIVE_LANES[L], PKG_MAX_LANES[L]);
  end
endgenerate

Package capability is a hard upper bound on digital configuration. An RTL parameter that exceeds it is not an aggressive setting; it is a design that cannot exist. Make the tool say so.

13. Physical Routability Becomes Logical Reachability

Width is the easy half. The harder half is which die pairs have a route at all — because a fabric that routes traffic has an opinion about that, and its opinion is usually "everything is reachable".

The interposer floorplan defines a graph. Encode it:

// Illustrative package-to-RTL configuration — not UCIe normative signal naming.
// One bit per (source, destination) die pair: 1 = a physical route exists.
localparam logic [NUM_DIES-1:0] ADJACENCY [NUM_DIES] = '{
  /* die 0: compute0 */ 4'b0100,   // → system die only
  /* die 1: compute1 */ 4'b0100,   // → system die only
  /* die 2: system   */ 4'b1011,   // → compute0, compute1, accelerator
  /* die 3: accel    */ 4'b0100    // → system die only
};
 
// A route request is physically meaningful only if the package provides the edge.
logic route_legal;
assign route_legal = ADJACENCY[src_id][dst_id];

Architecture. The interposer floorplan placed a system die centrally with three neighbours; the two compute dies are not directly routed to each other or to the accelerator. That is a routing-resource decision made in the package, and the digital system now has to live inside it.

State. The adjacency itself is a localparam — a physical fact. Only things that can genuinely change at runtime (which links are enabled, which dies are present) deserve registers, and Chapter 6.3 §11 and Chapter 6.4 §12 develop that distinction.

Cycle behaviour. route_legal is combinational, evaluated per route decision.

Contract. The routing or arbitration logic that selects a destination must consult it. Note carefully what is not here: no bump numbers, no interposer layer indices, no lane health. This is logical reachability, derived from physical facts but not exposing them — the Module 5 layering discipline still holds, and Chapter 6.4 §17 revisits why.

Failure. Without the check, a fabric happily selects a destination the package cannot reach. The traffic leaves, nothing arrives, no error is signalled by anything, and the transaction ages out — or, if there is no timeout, hangs.

DV. Make the invariant executable:

// Illustrative — package-derived routing invariant.
property p_route_requires_physical_link;
  @(posedge clk) disable iff (!rst_n)
    route_fire |-> ADJACENCY[src_id][dst_id];
endproperty
 
a_route_requires_physical_link :
  assert property (p_route_requires_physical_link)
  else $error("Route %0d -> %0d fired with no physical interposer link.",
              src_id, dst_id);

This assertion is worth understanding as a category, not just a line of code. It encodes a mechanical fact about a piece of silicon as an executable statement about a digital design. That is the whole method of this module: package signoff produces facts; those facts become parameters; those parameters become assertions; DV then proves the digital design correct inside the space the package permits.

14. What DV Must Cover

Package signoff defines the configuration space. DV's job is to prove digital correctness inside it — which means the test plan has package-derived entries:

• The supported topology, exercised end to end, with traffic on every legal edge.
• Absent edges — verify that a request toward an unrouted pair is rejected or routed indirectly, and never silently accepted.
• Reduced-width configurations, where a link runs narrower than its maximum. Width should be a parameter the testbench sweeps, not a constant baked into a single build.
• Asymmetric topology, since a real floorplan rarely gives every die the same neighbours or the same widths.
• Multi-link bring-up ordering, because two links on the same die do not train in lockstep and the fabric must tolerate one being up before the other.
• One link unavailable, where the product architecture defines a behaviour for it — degraded operation is a product decision, not an automatic property (Chapter 6.4 §15).

15. A Debug Signature Worth Memorising

Symptom. Every link trains. Link status is good on all of them. Error counters are clean. But traffic addressed to one particular die never arrives, and the requests eventually time out.

What it is not. Not a CRC problem — CRC failures increment counters and trigger retry. Not a training problem — training failures fail visibly, at bring-up, on the affected link. Not a lane-mapping problem — that corrupts data rather than losing it entirely.

What it almost certainly is. A topology or configuration mismatch: the route table or adjacency assumed a physical interposer edge that the floorplan does not provide, or provides between a different pair than the RTL believes.

How to tell them apart quickly:

The deterministic, error-free, destination-specific pattern is the tell. A physical problem in a channel is rarely that clean.

16. Common Misconceptions

"TSVs are the horizontal die-to-die links." They are vertical conduits through the interposer body. The die-to-die path is lateral, on interposer routing layers (§4).

"The interposer replaces the package substrate." It does not. The substrate is still there, still delivering power, still routing to the package's external connections. The interposer sits between the dies and the substrate and does a different job (§2).

"Silicon routing removes package constraints." It relaxes one constraint — connections per unit width — and leaves die edge, PHY area, power, thermal, interposer routing area, and cost exactly where they were (§5).

"Die placement no longer matters on an interposer." Placement sets route length, crossings, edge conflicts, interposer area, and thermal coupling. All of those still bind (§8).

"More routing density means unlimited bandwidth." Bandwidth needs lanes, which need PHY area on both dies, die edge on both dies, power, and interposer routing. Density improves one term in that product (§5).

"Signal routing and power delivery are independent on an interposer." They share layers, vertical structures, and area. Optimising signal density without PDN co-design produces links that are marginal rather than broken — the hardest failure to diagnose (§9).

"An interposer is basically another compute die." In the mainstream case it is a passive routing structure. Active-interposer concepts exist and are a distinct architectural class (§2).

"RTL topology can be chosen independently of package routes." RTL reachability is a consequence of package routability. Choosing it independently produces a design that works in simulation and hangs in silicon (§13).

"If every link trains, the topology must be correct." Training proves each link's channel works. It proves nothing about whether the links connect the pairs your route table believes they connect (§15).

17. Understanding Check

18. Summary and What Comes Next

A silicon interposer is a piece of silicon that dies are mounted on, whose routing layers carry die-to-die connections in a semiconductor-patterned medium instead of organic laminate. Its density advantage comes from four compounding effects — feature size, via structure, micro-bump attach pitch, and short distance — and it is exactly the structure UCIe's advanced-package track assumes.

The distinction to carry forward above all others: lateral routing on interposer metal is the die-to-die path; TSVs are the vertical conduit for power and board-bound signals. They are different structures doing different jobs, contending for the same interposer.

What the density buys is optional width, more independent links, more neighbours, and cheaper bits. What it does not buy is freedom from die edge, PHY area, power, thermal coupling, interposer routing area, or cost — the constraint moved rather than disappeared. Placement still matters, power still has to get vertically through, proximity still couples heat, and the interposer is itself a manufactured die with area, yield, and cost behaviour.

And the digital bridge: the interposer floorplan produces a route graph and a per-route width, those become elaboration-time constants, those constants become executable assertions, and DV proves the design correct inside the configuration space the package permits. Physical routability becomes logical reachability — and a route table that disagrees with the floorplan produces the cleanest, most deterministic, most misdiagnosed bug in the whole system.

A full interposer gives dense routing everywhere. But most systems do not need dense routing everywhere — they need it in a few specific places, between a few specific die pairs. Paying for a large silicon structure spanning the whole package to get density in three local regions is a real question, and there is an answer to it:

• 6.3 — Intel EMIB — embedding small silicon bridges inside an otherwise organic package, so that dense wiring exists only where it is needed, and adjacency becomes a first-class architectural constraint.

Browse the full path on the UCIe tutorials index.