Organic Substrates

Module 5 ended with the stack understood as hardware. Every constraint so far has been logical — ownership, state, timing, composition. This module changes domain entirely: the remaining constraints are geometric, and they are not negotiable by better RTL.

This chapter is about the organic substrate, the package technology standard-package UCIe is built for. It is routinely dismissed as "the cheap option", which is both unfair and useless. A substrate is a multilayer routing fabric with a specific construction, specific feature sizes, and specific limits — and those limits propagate all the way up into the NUM_LANES parameter an RTL engineer thinks they chose.

1. A Routing Fabric With Coarse Geometry

An organic substrate sits between the dies and the board, and it does three jobs at once: routes signals between dies, routes signals out to the board, and delivers power to everything above it.

An organic substrate is a multilayer package routing fabric between dies and the PCB — but its geometry is far coarser than silicon, so signal density, distance, escape routing, power delivery, and cost all become architecture constraints.

The word doing the work is geometry. Silicon is patterned by lithography at nanometre scale; an organic substrate is built from laminated films with copper patterned at micrometre scale. That difference is why a substrate cannot simply be asked for more connections, and why UCIe defines a separate advanced-package class at all.

2. How a Substrate Is Built

Enough construction to reason about limits, without becoming a materials chapter.

A flip-chip organic substrate is built around a core with build-up layers added on both sides. The core provides mechanical rigidity; the build-up layers provide fine routing. Industry describes the stack-up in a notation like 2+4+2 — two build-up layers, four core layers, two build-up layers. Common materials are a BT-resin core with build-up films such as ABF, chosen according to how many layers and how fine a feature size the design needs.

Connections between layers are made by vias, and in the build-up layers specifically by microvias, typically laser-drilled and then copper-plated. Microvias are what make fine layer-to-layer transitions possible at all.

The die attaches face-down by flip-chip bumping — copper pillar or solder bumps connecting die pads directly to the substrate's top routing layer. At the bottom, the package connects to the board through much larger solder balls.

That size disparity is the crux, and it is worth stating as the substrate's actual purpose:

A central purpose of the build-up layers is to fan out from the fine bump pitch of the die to the far coarser ball pitch of the package.

The substrate is a geometric translator. Everything difficult about it follows from that.

3. Why Density Is Lower Than Silicon

Several physical factors compound, and none of them is fixable by adding effort:

• Feature size. Conductor width and spacing achievable in laminate are far larger than in a silicon process. Fewer conductors fit in the same width.
• Via and pad structures. Vias in a substrate — even microvias — are large relative to silicon vias, and each needs a capture pad. Pads consume routing area on every layer they touch, so vias cost lateral space, not just vertical connection.
• Bump pitch. The die-side attachment pitch is coarser. Published UCIe material gives the standard-package class a bump pitch on the order of 100–130 µm, against roughly 25–55 µm for the advanced-package class — which is precisely why a standard-package module carries 16 data lanes where an advanced-package module carries 64 (Chapter 4.4).
• Trace length. Routes between dies travel further through the package than through a silicon bridge sitting directly beneath the interface.
• Layer count for escape. Because each layer carries fewer conductors, more layers are needed to escape the same number of signals — and layers cost money and thickness.

Note the direction of causation, because it is the chapter's spine: bump pitch and feature size determine routable connections, which determine module width, which determines link bandwidth. The specification's two packaging classes are a consequence of this physics, not an arbitrary choice.

4. Bump Count Is Not Routability

The single most important idea in this chapter, and the one that catches architects out.

A die may present hundreds or thousands of bumps in a two-dimensional array. They cannot all be routed straight outward on one layer — the bumps in the interior are surrounded by other bumps, and there is no straight path to the edge.

Escape routing solves this by fanning out: some signals route laterally between adjacent pads on the top layer, and others drop through microvias to lower layers where there is room, then travel outward. The published capability of the technology is illustrative — line-and-space geometry fine enough to run a conductor between adjacent pads is what makes even one-line-per-pitch escape possible.

Three consequences follow, and each is architectural:

• Every bump needs a route, not just a pad. A design that has enough bumps and no escape path for them has no link.
• Congestion concentrates at the die edge, because every escaping signal must pass through the perimeter region. The area near an interface is the scarcest routing resource in the package.
• A dense die-to-die PHY consumes a disproportionate share of that resource, because it concentrates a very large number of signals into one edge region — exactly where congestion is already worst.

Bump count tells you what the die offers. Escape routing tells you what the package can actually use.

5. Placement Is a Bandwidth Decision

If two chiplets exchange heavy traffic, their relative placement is not a mechanical detail — it determines what interface is achievable between them.

Placing the two PHYs on facing edges shortens every route in the interface, reduces the substrate area the interface consumes, and avoids routes crossing other signal groups. Placing them on non-facing edges means every conductor in the interface travels further, through more congested regions, competing with everything else.

Two honest qualifications. There is no universally correct floorplan — thermal separation, mechanical constraints, board-facing I/O placement, and other interfaces all pull against pure D2D optimisation. And a package has a limited number of adjacencies: with three or more dies, not every pair can face each other, so adjacency is a resource that must be allocated to the pairs whose traffic needs it most.

That is the same reasoning as Chapter 2.7's partitioning framework, now with a physical currency. The partition decides which pairs need bandwidth; the floorplan decides which pairs can have it.

6. Distance, Return Paths, and Crosstalk

Three physical effects that set the ceiling on what a substrate route can carry. Kept qualitative deliberately — precise numbers are channel- and stack-up-specific and belong to signal-integrity analysis.

Distance costs margin. Longer routes attenuate more, accumulate more delay, and give coupling more opportunity to act. This is the physical reason that wide, short die-to-die interfaces favour physical proximity, and it is why §5's placement argument is about electrical feasibility rather than tidiness.

Return paths matter as much as signal paths. A high-speed signal's current returns through a nearby reference plane. If a route crosses a gap in that plane, or transitions layers without a nearby return path, the return current is forced to detour — producing discontinuity, added inductance, and coupling into neighbours. The practical consequence is that a route's quality depends on the layer stack around it, not only on the conductor itself, which is why plane assignment and via placement are part of interface design.

Crosstalk grows with density. Conductors close together couple. Pushing more signals through the same width raises coupling, which is why substrate design rules impose spacing — and why the achievable connection count is lower than the geometry alone would suggest. Density and signalling rate trade against each other: the same substrate may support more conductors at a lower rate or fewer at a higher one.

7. Power Shares the Same Structure

The substrate does not have separate resources for signals and power. They compete.

Power delivery needs conductor cross-section to carry current with acceptable drop, plane area for low impedance, via arrays to move current between layers, and space for decoupling. Every one of those consumes the same layers, area, and via space that signal escape needs.

Signal density cannot be optimised independently of power-delivery quality.

The failure this produces is instructive because it is not a routing failure. Push signal routing hard enough and the power delivery network degrades — more voltage droop under load, worse impedance across frequency — and the symptom appears as marginal high-speed links, jitter, or errors that worsen with activity. Someone debugging the link may conclude the channel is inadequate when the actual cause is that the interface starved the PDN of resources.

Which makes the practical rule: an interface's cost includes its share of power-delivery resources, and a floorplan that leaves no room for the PDN has not solved the routing problem, only relocated it.

8. Why Organic Substrates Remain the Default

Given all these limits, it would be easy to conclude advanced packaging is simply better. It is not, and the reasons are substantial.

Organic substrate manufacturing is mature and high-volume, with a broad supplier base and well-understood yield. Large substrate areas are economically practical in a way large silicon is not — a silicon interposer big enough to host several dies is itself a large die subject to the cost, yield, and reticle constraints of Module 1. The ecosystem of design tools, design rules, assembly, and test is deep. And for a great many products, the connectivity a standard package provides is genuinely sufficient.

The trade, stated carefully:

Advanced packaging is the right answer when the required connectivity genuinely exceeds what the substrate can provide. It is the wrong answer when it does not — paying interposer cost for connectivity a laminate could have carried is simply a more expensive product. Chapters 6.2 and 6.3 cover the alternatives properly.

9. Where Package Geometry Becomes an RTL Parameter

This is the bridge the chapter exists to build, and it is where packaging stops being someone else's problem.

An RTL engineer writes:

// Illustrative configuration — the values are physical-design outcomes.
module d2d_phy #(
  parameter int unsigned NUM_LANES   = 16,
  parameter int unsigned NUM_MODULES = 1
) ( /* ... */ );

Those parameters look like design choices. They are not — they are the end of a physical decision chain:

bump pitch and feature size → how many connections escape the die edge → module width the packaging class supports → how many modules the available edge and routing can carry → NUM_LANES and NUM_MODULES.

Every step is a packaging outcome. By the time the parameter reaches the RTL, the decision has been made by substrate geometry, escape analysis, floorplan, and channel analysis. An RTL engineer who raises NUM_LANES because more bandwidth is needed has not obtained more bandwidth — they have produced a design that cannot be routed.

Those parameters then propagate widely: PHY width and lane logic, buffer sizing throughout the Adapter (Chapter 5.2), achievable link bandwidth and therefore scheduling and flow-control provisioning, and the configuration matrix verification has to cover.

A modest configuration-consistency check is genuinely useful here, and it is the only assertion this chapter needs:

// Illustrative configuration invariant — the design must never enable more
// lanes than the package was qualified to support.
property p_active_lanes_within_package_budget;
  @(posedge clk) disable iff (!rst_n)
    active_lane_count <= PACKAGE_SUPPORTED_LANES;
endproperty
assert property (p_active_lanes_within_package_budget)
  else $error("enabled more lanes than the package supports");

What it catches. A configuration or firmware path that enables a width the package cannot carry — which, unlike a logic bug, produces a link that trains marginally or fails intermittently under conditions nobody can reproduce in simulation, because the deficiency is physical.

10. When the Package Invalidates the Partition

Make the failure concrete. Hypothetical, and deliberately without invented numbers.

An architecture requires a certain bandwidth between two dies. Package analysis then reports that, given the die edge available at the chosen placement, the escape routing required, and the PDN resources that must be preserved, only one module fits.

The architects' options are all architectural, not RTL:

• Raise the signalling rate within what the channel and specification support — bounded by the signal-integrity analysis of §6.
• Reduce the traffic crossing the boundary, by moving function across the partition so less must cross (Chapter 2.7).
• Aggregate or compress traffic so the same work needs less boundary bandwidth.
• Change the floorplan to obtain a better adjacency — which may cost another interface its adjacency.
• Move to an advanced package, buying density at higher cost and complexity.
• Repartition the dies entirely.

Packaging can invalidate a logical partition. A partition that is elegant, well-reasoned, and unroutable is not a partition.

Note that most of these responses have to happen early. Repartitioning after RTL freeze is not a schedule anyone survives, which is why Chapter 2.7 insisted package feasibility is an input to partitioning rather than a downstream check.

11. What SI/PI Proves and What DV Proves

A boundary worth drawing sharply, because engineers on each side sometimes assume the other has covered something.

Signal- and power-integrity analysis proves that the channel can carry the intended signalling — loss, reflections, crosstalk, timing margin — that the power delivery network meets its impedance and droop targets under realistic activity, and that the routing is physically realisable within the design rules.

RTL verification proves that the digital design behaves correctly in the configuration the package enables: correct width handling, correct lane enable and health logic, correct backpressure and bandwidth behaviour, correct error and status handling, correct behaviour in degraded and reduced configurations.

Neither substitutes for the other, and the gap between them is real. A design can be digitally flawless on a channel that cannot carry it; a channel can be excellent under a design that enables the wrong lanes. Simulation does not model the package, and channel analysis does not model the state machines.

The practical consequence for DV: the package-driven configuration space is part of the test plan — different lane and module counts, disabled lanes, degraded modes, and the reduced-bandwidth configurations the architecture permits. Those configurations exist because of packaging, and verifying only the nominal one leaves the ones a real product ships in untested.

12. Common Misconceptions

13. Understanding Check

14. Summary and What Comes Next

An organic substrate is a multilayer routing fabric built as a core with build-up layers on both sides, connected by vias and laser-drilled microvias, with dies attached face-down by flip-chip bumps and the package attached to the board by much coarser solder balls. A central purpose of the build-up stack is to fan out from fine die-bump pitch to coarse ball pitch — the substrate is a geometric translator, and its difficulties all follow from that.

Its density is lower than silicon because of feature size, via and pad structures that cost lateral space, coarser bump pitch, longer routes, and the layer count escape demands. That chain is why UCIe's standard-package module carries 16 data lanes at roughly 100–130 µm pitch where the advanced-package module carries 64 at roughly 25–55 µm.

Three ideas carry forward. Bump count is not routability — every bump needs an escape path, congestion concentrates at the die edge, and a dense D2D PHY consumes the scarcest region. Placement is a bandwidth decision, since facing-edge adjacency shortens every conductor and adjacency is a finite resource. And power shares the same structure, so signal density cannot be optimised independently of PDN quality — with the failure presenting as a marginal link rather than a routing error.

Above all, the bridge: NUM_LANES and NUM_MODULES are the end of a physical decision chain, not RTL choices, and packaging can invalidate a logical partition. SI/PI proves the channel and the power network; DV proves the digital design in the configuration packaging enables — and the package-driven configuration space belongs in the test plan.

Organic substrates trade density for cost and manufacturing practicality. When required die-to-die connectivity exceeds what that fabric can comfortably carry, architects turn to a much denser medium:

• 6.2 — Silicon Interposers — through-silicon interposers and the density they buy, at the cost of being a large die in their own right.

Browse the full path on the UCIe tutorials index.