3D Packaging

Every chapter of Module 6 so far has kept the dies in one plane. Organic substrate, silicon interposer, embedded bridge, complete 2.5D system — different media, different densities, same fundamental geometry: active silicon side by side, connected laterally, each die with its own unobstructed path to the heat spreader above and the board below.

Stacking removes that. When one active die sits directly on top of another, the communication distance between them collapses from millimetres to microns, and the connection count can rise by orders of magnitude. That is an enormous architectural gain, and it is not free — because the same stacking that shortens the signal path also puts one die's heat directly in another die's escape route, puts one die's power supply through another die's body, and buries a die where no probe can reach it.

This chapter is about that trade, and about the digital configuration state it forces into your RTL.

1. The One-Sentence Model

3D packaging trades horizontal distance for vertical integration: communication becomes extremely short and dense, while power delivery, heat removal, test access, yield, and fault isolation all get harder — because the dies now share one vertical footprint.

The first half is why anyone does it. The second half is why it is hard, and every one of those five difficulties has the same root cause: things that used to have independent paths now share one. Heat, current, test access, and assembly risk were per-die concerns in a planar package. In a stack they are stack-level concerns, and a stack-level concern is exactly the kind that shows up as a system architecture decision rather than a die design decision.

2. 2.5D and 3D Are Different Tools

Not a succession — a choice, with genuinely different characteristics.

Neither replaces the other, and real products mix them: a package can be 2.5D laterally — several dies on a common fabric — while one or more of those "dies" is itself a 3D stack. The reasoning below applies to the vertical dimension wherever it appears.

3. Stack Anatomy

A representative shape, working downward:

• Top die — often the higher-power compute die, because it is the one with direct access to the heat spreader.
• The bond interface — the die-to-die connection layer, whose construction (micro-bumps, or direct bonding) is the subject of Chapter 6.6.
• Base die — frequently a system, I/O, or cache die. It provides routing between the stack and the outside world, and it is what the package substrate actually attaches to.
• TSVs through the base die — vertical conduits passing through the base die's silicon body, carrying power up from the package and signals down to it.
• The package substrate, and the board below.

Intel's Foveros is a concrete instance of this shape: the face of the top die is bonded to the face of the base die, and the base die connects downward to the package through TSVs. That last clause is the important one — read §5 before assuming what those TSVs are for.

4. Orientation: Face-to-Face and Face-to-Back

A die is not symmetric. Its face is the side with the transistors and the metal stack; its back is bulk silicon. Which side of each die participates in the bond determines everything about the interconnect path.

Face-to-face (F2F). The two active faces are bonded directly to each other. The connection is as short as it can physically be, because both sets of metal stacks meet at the interface with no silicon in between. This is the orientation that produces the shortest, densest die-to-die interconnect — and it is the orientation Intel describes for Foveros, with the top die's face bonded to the base die's face.

Face-to-back (F2B). One die's active face connects toward another die's backside, which means signals or power must traverse the silicon body of the die in between — a job for through-silicon vias. This orientation is what makes stacks of more than two dies practical, since a die in the middle has to pass connections through it in at least one direction.

The architectural consequence is not about which is "better":

Orientation determines the interconnect path, and therefore also the power path and the thermal path. A face-to-face bond gives the shortest signals but leaves both dies' external connections to be solved some other way — which is precisely why the base die still needs TSVs even when its bond to the top die is face-to-face.

Vendor implementations differ in detail, and stacking terminology is used loosely in marketing material. What transfers is the geometry: which surface carries the connection, and what has to be traversed to reach the outside world.

5. What the TSVs Are Actually For

Chapter 6.2 warned against believing that the dies on an interposer talk to each other through TSVs. The 3D case needs the same care, with a different answer.

In a passive interposer, TSVs are vertical passage through a routing structure. In a 3D stack, TSVs pass through an active die's silicon body, and their job depends on what is above and below:

• Power delivery upward. Current must reach every die in the stack, and it enters from the substrate at the bottom. In a face-to-face pair, the top die's power arrives via the base die — which means through TSVs in the base die's body, then across the bond interface. This is the dominant reason TSVs exist in the shape described in §3.
• External signals downward. Anything the stack exchanges with the package or the board arrives and leaves through the base die, again via TSVs.
• Pass-through connectivity in taller stacks, where a middle die must carry connections between the die above it and the die below it.

What TSVs are generally not, in a face-to-face pair: the die-to-die path itself. That path is the bond interface, and it is short precisely because it avoids traversing silicon.

6. Why Vertical Links Can Be Extremely Dense

Density here comes from geometry before it comes from any process cleverness:

• The distance is microns. Two bonded faces are separated by the bond interface, not by a package route. A conductor that short has very little capacitance to charge.
• The area is two-dimensional. A lateral link escapes through a die edge, which is a one-dimensional resource. A vertical link uses the die face, which is two-dimensional — an entirely different budget, and the reason vertical connection counts can be orders of magnitude larger.
• No escape routing. Chapter 6.1's fan-out problem barely applies: connections do not have to travel outward through congested perimeter routing before they reach anything.
• Pitch can be far finer than anything a laminate or even an interposer attach supports, because the two surfaces are bonded rather than joined through a package structure.

That combination is why a vertical interface can be wide enough to change what counts as a reasonable die boundary — the theme Chapter 6.6 develops. Note what is not claimed here: no specific energy-per-bit figure, because that depends on the bonding technology, the process, and the circuit design. The geometric argument is solid on its own.

7. The Problem That Has No Easy Answer: Heat

This is the section that decides most real 3D architectures.

Stack two active dies and only one of them touches the heat spreader. The other one's heat has to leave through its neighbour. Concretely:

• Lower dies are thermally disadvantaged. Their path to the cooling solution runs through everything above them, and silicon plus a bond interface is a worse thermal path than a direct contact.
• Hotspots align. If a hot block on the top die sits directly above a hot block on the base die, their temperature rises compound in the same vertical column. Nothing about the floorplan of either die alone reveals this.
• Activity on one die constrains the other. Neither die can be characterised in isolation any more, because the temperature each reaches depends on what its neighbour is doing.
• The compact footprint concentrates power. The same total power in a smaller area is a higher power density, which is the quantity cooling actually cares about.

In 2.5D, adjacency couples heat horizontally. In 3D, activity stacks heat vertically — and the vertical direction has one exit.

This is why connectivity and cooling scale in opposite directions. Bonding technology keeps improving the number of connections between two dies. Heat removal does not improve at anything like the same rate, because it is bounded by materials and by the geometry of the exit path. Interconnect density outruns thermal capability, and that gap — not signalling — is the practical limiter on how much active silicon a stack can hold.

8. Thermal-Aware Partitioning

Which means partitioning in 3D has an extra dimension of reasoning that 2.5D did not.

The 2.5D rule was: put heavily communicating dies adjacent. In 3D that rule survives but acquires a competitor, because vertical adjacency is also thermal adjacency in the worst possible way. Some patterns that follow:

• Put the highest-power logic where the cooling path is best — typically the top of the stack, closest to the spreader.
• Consider lower-power layers underneath. Cache or memory arrays, which dissipate less than dense compute logic, are easier neighbours for a hot die than a second hot die.
• Avoid stacking hotspots. Two dies can each be thermally fine and the stack still fail, if their hot regions align vertically. This is a cross-die floorplan constraint — the two teams have to exchange power maps, not just interface specifications.
• Treat sustained-power states as stack-level, since what the top die can sustain depends on the base die's activity and vice versa.

None of these is universal — a memory-over-logic stack and a logic-over-logic stack have different answers, and the right one depends on the power maps and the cooling solution. The transferable point is that thermal reasoning enters the partition decision itself, not the physical implementation afterwards.

9. Power Delivery Goes Vertical Too

Current for the entire stack enters from one place: the package substrate at the bottom. Getting it to a die two layers up requires:

• TSVs through the intervening silicon, which occupy area and have finite current capability.
• Vertical distribution across the bond interface, competing for the same interface the signals want.
• Decoupling at each level, because the impedance from the board to an upper die is worse than to a die attached directly to a substrate.

The consequence generalises the 6.1 and 6.2 lesson into the vertical direction:

Signal interconnect and power interconnect compete vertically. Every connection assigned to data is a connection not assigned to power or ground, and unlike a lateral package there is no separate structure to move the conflict into.

Where this bites: a stack designed to maximise die-to-die bandwidth can end up with a power network that sags under simultaneous activity — and the symptom, as always with PDN problems, is not a power error. It is marginal links, correctable errors, or instability that only appears under specific workloads.

10. Yield and Assembly

Stacking changes the yield arithmetic in a way worth being precise about, and worth not overstating.

A working stack requires: every die in it to be good, every bond to be formed correctly, alignment to be within tolerance, and the vertical connections to be functional. Those are additional, largely independent requirements on top of per-die yield. Conceptually:

stack yield  =  (yield of each die, given the dies used)
             ×  (assembly and bonding yield)
             ×  (vertical interconnect yield)

Three cautions on that expression. It is a structure, not a formula — real models account for correlation, for repair, and for whether partial stacks are salvageable. Per-die yield in a stack is not raw wafer yield, because good dies are selected before assembly. And the bonding term depends heavily on the technology and its maturity, so treating it as a constant across generations is wrong.

The undeniable part is the direction: stack yield cannot exceed the product of its parts, and it adds terms that a planar package does not have.

11. Known-Good-Die and Buried-Die Test

Chapter 1.3's known-good-die argument gets sharper here, for a specific structural reason: assembly is expensive and irreversible. Discovering a bad die after bonding discards every good die bonded to it.

That drives a test strategy with distinct stages:

• Pre-bond test — establish that each die is good before it is committed to a stack. The value of catching a defect here is the value of everything else in the stack.
• Post-bond test — bonds and vertical interconnect are new failure modes that no die-level test could have covered. The die can be perfect and the connection between two dies still absent.
• Stack-level diagnosis — when the assembled stack misbehaves, determining which layer is at fault, which is a harder question than it sounds.

And the structural problem underneath all three:

A buried die cannot be probed. Its signals are reachable only through whatever access path the architecture deliberately provided.

That is an architecture decision made long before assembly. If the inner die's observability was not designed in, it does not exist — no equipment recovers it later. Which is why test access in a stacked product is not a back-end concern to be handled after RTL freeze; it is a partitioning-time decision about what each die must be able to report about itself and how that report reaches the outside world. (The DFT mechanics belong to their own track; what belongs here is that the requirement originates in the package.)

12. Fault Isolation Is a Product Decision

One die in the stack fails to initialise. What does the product do?

1. The whole stack is scrapped. Legitimate, and common, precisely because everything shares one physical assembly.
2. The die is disabled and the system runs without its function, if the architecture defines what that means.
3. The die is bypassed, with traffic that used it routed elsewhere — which requires an elsewhere to exist.
4. A degraded configuration ships, if binning was designed for.

As in Chapter 6.4, do not assume any option beyond the first exists. Degraded operation is design and verification work — discovery, a software contract, a different topology, a different power and thermal budget, and its own coverage — and it does not appear by accident. What it does require, in every case where it exists, is digital state that distinguishes what is physically there from what is being used.

13. Present Versus Enabled, in the Vertical Direction

// Illustrative package-to-RTL configuration — not UCIe normative signal naming.
localparam int NUM_STACK_DIES = 3;   // base + two stacked layers
 
logic [NUM_STACK_DIES-1:0] die_present_q;   // physically bonded and detected
logic [NUM_STACK_DIES-1:0] die_enabled_q;   // the system chooses to use it

Architecture. A stack may ship with different layer populations, and a bonded layer may be present but unusable — failed post-bond test, disabled by binning, held down by a thermal or power constraint, or switched off for debug. One mask cannot represent both facts.

State. Two registers, each one bit per stack layer. die_present_q is written by discovery during bring-up; die_enabled_q by configuration policy. The invariant tying them is die_enabled_q ⊆ die_present_q.

Cycle behaviour. Both settle during bring-up and are stable afterwards. die_enabled_q may change later if the product supports disabling a layer at runtime; die_present_q must not, because physical presence does not change while the part is powered.

Contract. Routing consults enabled. Discovery, diagnostics, and error reporting consult present. Any workload scheduler that dispatches to a layer must consult enabled, never present.

Failure. With a single mask, "not bonded" and "bonded but unusable" become indistinguishable. Work is dispatched into a layer that exists but cannot execute it, and the resulting hang has no diagnostic signature — the layer is physically there, so every presence check passes.

DV. The invariant is one line and catches an entire class of configuration bug:

// Illustrative — the enabled set must be a subset of the present set.
property p_enabled_die_is_present;
  @(posedge clk) disable iff (!rst_n)
    (die_enabled_q & ~die_present_q) == '0;
endproperty
 
a_enabled_die_is_present :
  assert property (p_enabled_die_is_present)
  else $error("Stack layer enabled without being present: enabled=%b present=%b",
              die_enabled_q, die_present_q);

Physical fact encoded: which layers are actually bonded into this assembly. Bug caught: a fuse, strap, firmware table, or debug override that enables a layer the SKU does not contain. Why digital verification owns it: the silicon symptom is a bring-up timeout on a vertical link, which every instinct routes toward bond quality and physical debug when the defect is one bit in a configuration mask.

14. Physical Stacking Does Not Define Logical Topology

This is the vertical restatement of Chapter 6.3's central lesson, and it catches people just as reliably.

Two dies bonded face to face have a physical interface. Three dies stacked do not automatically have three pairwise interfaces — a middle die may connect to the die above and the die below with no direct path from top to bottom. Whether such a path exists depends on whether the architecture provided pass-through routing, and that is a design decision.

The natural wrong assumption:

// WRONG architectural assumption — vertical adjacency is not full connectivity.
assign vertical_route_ok = (src_layer != dst_layer);

This says any other layer is directly reachable. In a stack where only neighbouring layers are bonded, the top layer reaching the package's external I/O requires the base die to forward for it — and if the base die was not designed to forward, that path does not exist at any speed.

The correct form makes the physical edge set explicit:

// Illustrative — vertical interfaces that physically exist in this stack.
localparam int NUM_VERTICAL_LINKS = 2;
 
// Endpoint layer indices for each vertical interface.
localparam int VLINK_LOWER [NUM_VERTICAL_LINKS] = '{0, 1};
localparam int VLINK_UPPER [NUM_VERTICAL_LINKS] = '{1, 2};
 
logic [NUM_VERTICAL_LINKS-1:0] vertical_link_enable_q;

Architecture. The stack's bond interfaces define an edge set — here a chain, base → middle → top — and the enable mask records which of those the system brought up.

State. One bit per vertical interface, written during bring-up.

Cycle behaviour. Sampled by routing legality and by bring-up sequencing; stable in steady state.

Contract. Whatever selects a destination layer consults the edge set, expressed in layer identities. It does not consult bump maps, TSV counts, or bond-interface geometry — the Module 5 layering rule holds in the vertical direction exactly as it does laterally.

Failure. Without it, a request from the top layer toward the package is accepted, issued toward a path that has no physical existence, and never completes. No layer observed a violation, so no layer reports an error.

DV. Both endpoints of an enabled interface must be usable:

// Illustrative — an enabled vertical interface needs both of its layers.
generate
  for (genvar V = 0; V < NUM_VERTICAL_LINKS; V++) begin : g_vlink_endpoints
    property p_vertical_link_endpoints_exist;
      @(posedge clk) disable iff (!rst_n)
        vertical_link_enable_q[V] |-> die_present_q[VLINK_LOWER[V]] &&
                                      die_present_q[VLINK_UPPER[V]];
    endproperty
 
    a_vertical_link_endpoints_exist :
      assert property (p_vertical_link_endpoints_exist)
      else $error("Vertical link %0d enabled with a missing endpoint layer.", V);
  end
endgenerate

Physical fact encoded: a bond interface is only meaningful if silicon is bonded on both sides of it. Bug caught: bring-up driving training into a layer that was never assembled — which burns bring-up time producing an error that is not an error. Why digital: the symptom is a link that will not train, indistinguishable at the waveform level from a genuine bond defect.

14a. The Base-Die Pattern

One architecture recurs often enough to name. The base die acts as the stack's interface to everything else: it carries the package attachment, hosts the TSVs, provides routing between upper layers and the outside world, and frequently owns power management and platform I/O.

That makes it the vertical analogue of Chapter 6.3's hub die, with the same four properties at once — routing hub, bandwidth aggregation point, bottleneck candidate, and fault concentration point. If the base die is down, the stack is down, regardless of how healthy the layers above it are.

Not every 3D package works this way; some stacks are memory over logic with no meaningfully "active" base. But where the pattern appears, the reasoning from 6.3 §9 transfers unchanged, including the warning that multi-hop forwarding exists only if something was designed to forward.

15. Thermal State Becomes Digital State

The package's thermal envelope is a physical property. The system's response to it is digital.

// Illustrative architecture RTL — not UCIe normative signal naming.
// Per-layer thermal limit indication, from platform thermal management.
logic [NUM_STACK_DIES-1:0] thermal_limit;   // 1 = this layer is at its limit
logic                      package_power_ok;
 
// A boost request is granted only if both the shared package envelope and the
// requesting layer's own thermal state permit it.
assign top_die_boost_grant =
    top_die_boost_req && package_power_ok && !thermal_limit[TOP_ID];

Architecture. Vertical stacking couples heat and shares one PDN, so a layer cannot decide its own performance state on local evidence. Two independent constraints apply: the package-wide power envelope, and this layer's own thermal headroom.

State. A limit bit per layer plus a package-level budget indication, both maintained by platform thermal and power management. Nothing here models temperature physics — the RTL consumes a decision made elsewhere.

Cycle behaviour. These change on a much slower timescale than data movement — thermal state evolves over milliseconds, power states over microseconds — so the gating logic is combinational over slowly-moving inputs, not a per-cycle datapath.

Contract. Each layer's performance-state logic must treat its boost as conditional. A layer that raises its state on its own authority has assumed a resource shared with everything above and below it.

Failure. Two layers boosting simultaneously on independent local decisions exceed the envelope. In the power case that produces droop, presenting as marginal vertical links or correctable errors. In the thermal case it produces sustained over-temperature, and the symptom appears in a different layer from the cause — the base die throttles because the top die is hot.

DV. Test simultaneous boost requests across layers, and the withdrawal of budget while a boost is active. The negative test matters more than the positive one: granting under pressure is the bug, refusing is the feature.

16. What DV Must Cover

The package defines the legal configuration space; the test plan names points in it:

• Full stack, everything present and enabled, at full activity.
• An optional layer absent — a different SKU, a different topology, a different bandwidth and power budget.
• A layer present but disabled, which is the case a single-mask design gets wrong.
• A vertical interface disabled with both layers present, proving the disable path is clean rather than merely untested.
• Thermal limit asserted on each layer in turn, including while traffic is in flight.
• Power budget withdrawn during an active boost.
• Bring-up ordering variations, since layers do not come up in lockstep and the base die is generally up before anything above it.
• Illegal configuration rejection — enabling a layer or an interface that is not present must be detected and reported.

Do not generate configurations the package cannot produce. A stack with the middle layer absent but the top layer present is not a test case if the assembly cannot exist; spending coverage on impossible states hides the gaps in the possible ones.

17. Three Failure Signatures

Same discipline as Chapter 6.4, adapted to the vertical direction:

The third column has a signature the planar chapters did not: it changes with time and temperature in a characteristic way. Traffic is correct, no errors appear, and throughput is fine for a while and then collapses as the stack heats — often recovering partially when activity drops. That is not a bug in anything digital. It is the package telling you that the sustained operating point you assumed does not exist.

Note also how the first and third columns can be confused: both are temperature-sensitive. The discriminator is correctness. A thermal throttle keeps the data correct and reduces throughput; a marginal vertical channel corrupts data or drops the link. Correct-but-slow and wrong-but-fast are different problems.

18. Common Misconceptions

"3D just means a smaller package." Footprint is a side effect. The architectural change is that the die-to-die interface becomes short and two-dimensional, and that heat, power, and test access become shared vertical problems (§1, §6).

"Vertical communication eliminates latency." It shortens the physical path dramatically. Logic still has to serialise, buffer, cross clock domains, and arbitrate. Distance is one term in latency, not all of it (§6).

"Stacked dies are thermally independent." They share one exit path. A lower die's heat leaves through the die above it, and aligned hotspots compound (§7).

"TSVs carry the die-to-die traffic." In a face-to-face pair they typically carry the power and external connections the bond interface cannot (§5).

"If every die passes wafer test, stack yield is guaranteed." Bonding, alignment, and vertical interconnect are additional independent requirements that no die-level test covers (§10).

"A buried die can be probed like an exposed one." It cannot be probed at all. Its observability is whatever the architecture designed in, decided long before assembly (§11).

"Physical stacking implies full logical connectivity." Bonded neighbours have interfaces; non-neighbours have whatever forwarding was designed. Top-to-package usually goes through the base die (§14).

"A present layer is automatically usable." Present is a fact about assembly; enabled is a decision by the system. Conflating them dispatches work into a layer that cannot execute it (§13).

"3D is always better than 2.5D." They have different cooling access, different power paths, different test access, and different failure blast radius. Product requirements decide (§2).

"Thermal throttling is firmware's problem." It becomes a digital gating constraint on performance states, with a verification obligation and a distinctive debug signature (§15, §17).

19. Understanding Check

20. Summary and What Comes Next

3D packaging stacks active dies vertically, trading horizontal distance for vertical integration. The interface becomes microns long and uses the die face rather than the die edge, which is why vertical connection counts can be enormous. Face-to-face bonding gives the shortest path; face-to-back requires traversing silicon and is what TSVs are for. In a face-to-face pair the TSVs in the base die generally carry power and external connections, not the die-to-die traffic.

Everything that gets harder has one cause: the dies now share a vertical column. Heat has one exit and the lower dies are behind the upper ones. Power enters at the bottom and must climb, competing with signals for the same interface. Inner dies are buried and unprobeable, making observability a partitioning-time decision. And stack yield adds bonding, alignment, and vertical-interconnect terms that no die-level test covers. Interconnect density improves faster than heat removal, which makes thermal capability the practical limit on how much active silicon a stack can hold — and pushes thermal reasoning into the partition decision itself.

The digital bridge: present and enabled are different facts and need different masks; vertical adjacency is not full connectivity, so the physical edge set must be explicit and src_layer != dst_layer is the natural wrong answer; and thermal and power state become gating conditions on performance, with a debug signature — correct data, zero errors, throughput collapsing as the part warms — that belongs to no other failure class.

This chapter has treated the bond interface as a given. But its construction is exactly what determines how dense the vertical interface can be, and that construction is changing fast enough to move architectural boundaries:

• 6.6 — Advanced Packaging Concepts — micro-bumps, hybrid bonding, and what happens to partitioning when the bump itself starts to disappear.

Browse the full path on the UCIe tutorials index.