Shift Operators

// General syntax: operand shift_op shift_amount
result = value <<  n;    // logical  left  — n can be an expression
result = value >>  n;    // logical  right
result = value <<< n;    // arith    left  — same as <<
result = value >>> n;    // arith    right — sign-extends if value is signed
 
// ── Unsigned examples (logic [7:0]) ──────────────────────────────
logic [7:0] u = 8'b0001_0000;   // 16
u <<  2;   // 8'b0100_0000 = 64  (×4)
u >>  2;   // 8'b0000_0100 = 4   (÷4, zero-fill)
u >>> 2;   // 8'b0000_0100 = 4   (same — unsigned)
 
// ── Signed examples (logic signed [7:0]) ─────────────────────────
logic signed [7:0] s = -8;      // 8'b1111_1000
s >>  2;    // 8'b0011_1110 = +62  WRONG: shifted in 0s
s >>> 2;    // 8'b1111_1110 = -2   CORRECT: shifted in sign bit (1)
 
// ── Shift amount rules ───────────────────────────────────────────
// Shift amount is always treated as UNSIGNED
// If shift amount >= operand width, result is 0 (or all sign bits for >>>)
logic [7:0] v = 8'hFF;
v >> 8;    // 8'h00 — shifted out entirely
v >> 100;  // 8'h00 — same
 
// ── Variable shift (generates barrel shifter in synthesis) ───────
logic [3:0] shift_amt;
result = data << shift_amt;   // shift_amt computed at runtime

module tb_shift_basic;
 
  logic        [7:0] u_val  = 8'd16;   // unsigned 16 = 0001_0000
  logic signed [7:0] s_neg  = -8;      // signed  -8  = 1111_1000
  logic signed [7:0] s_pos  = 8'd16;   // signed +16  = 0001_0000
 
  initial begin
 
    // ── Left shifts — zero fills right, identical for << and <<< ──
    $display("u_val <<  2 = %0d  (16×4=64)",  u_val <<  2);  // 64
    $display("u_val <<< 2 = %0d  (same)",      u_val <<< 2);  // 64
 
    // ── Logical right — zero fills left ───────────────────────────
    $display("u_val >>  2 = %0d  (16÷4=4)",   u_val >>  2);   // 4
    $display("s_neg >>  2 = %0d  (WRONG!)",   s_neg >>  2);   // +62
 
    // ── Arithmetic right — sign fills left ────────────────────────
    $display("s_neg >>> 2 = %0d  (-8÷4=-2)",  s_neg >>> 2);  // -2
    $display("s_pos >>> 2 = %0d  (16÷4=4)",   s_pos >>> 2);  // 4 (positive: 0 fills)
    $display("u_val >>> 2 = %0d  (unsigned: 0 fill)", u_val >>> 2); // 4
 
    $finish;
  end
 
endmodule

u_val <<  2 = 64  (16×4=64)
u_val <<< 2 = 64  (same)
u_val >>  2 = 4   (16÷4=4)
s_neg >>  2 = 62  (WRONG!)
s_neg >>> 2 = -2  (-8÷4=-2)
s_pos >>> 2 = 4   (16÷4=4)
u_val >>> 2 = 4   (unsigned: 0 fill)

module tb_shift_address;
 
  logic [31:0] base_addr = 32'h1000_0000;
  logic [31:0] word_addr, byte_mask, field_mask;
  int          index;
 
  initial begin
 
    // ── Word-aligned address from byte index ──────────────────────
    // AXI/APB: word addresses are byte_addr >> 2
    // Byte address from word index: word_idx << 2
    for (int i = 0; i < 4; i++) begin
      word_addr = base_addr + (32'(i) << 2);
      $display("Word[%0d] addr = 0x%08h", i, word_addr);
    end
    // 0x10000000, 0x10000004, 0x10000008, 0x1000000C
 
    // ── Generate single-bit mask at position n ────────────────────
    for (int bit_pos = 0; bit_pos < 4; bit_pos++) begin
      byte_mask = 32'h1 << bit_pos;
      $display("Bit mask [%0d] = 0x%08h (%032b)",
               bit_pos, byte_mask, byte_mask);
    end
 
    // ── Extract byte N from 32-bit word ──────────────────────────
    logic [31:0] data = 32'hAABBCCDD;
    for (int byte_n = 0; byte_n < 4; byte_n++) begin
      logic [7:0] extracted = (data >> (byte_n * 8)) & 8'hFF;
      $display("Byte[%0d] = 0x%02h", byte_n, extracted);
    end
    // Byte[0]=0xDD, Byte[1]=0xCC, Byte[2]=0xBB, Byte[3]=0xAA
 
    $finish;
  end
 
endmodule

// DSP core verification: right-shift with rounding
// DUT computes: (A × B) >>> SCALE, with half-up rounding
class DspScoreboard;
 
  localparam int SCALE = 8;   // right-shift amount
 
  function int expected_result(input int a, b);
    longint product = longint'(a) * longint'(b);
    longint half    = 1 << (SCALE - 1);       // 0.5 in fixed-point
    longint rounded = (product + half) >>> SCALE;  // arithmetic shift
    return int'(rounded);
  endfunction
 
  function void check(input int a, b, dut_out);
    int exp = expected_result(a, b);
    if (exp !== dut_out)
      $error("DSP FAIL: %0d * %0d >> %0d = exp %0d, got %0d",
             a, b, SCALE, exp, dut_out);
    else
      $display("DSP OK:   %0d * %0d >> %0d = %0d", a, b, SCALE, exp);
  endfunction
 
endclass
 
module tb_dsp;
  DspScoreboard sb;
  initial begin
    sb = new();
    sb.check(100,  200, 78);     // 100×200=20000, 20000>>8 ≈ 78
    sb.check(-100, 200, -78);    // -100×200=-20000, -20000>>8 ≈ -78
    $finish;
  end
endmodule

module tb_unsigned_arith_shift;
 
  logic        [7:0] u_val = 8'hF8;    // unsigned — MSB = 1, but not signed
  logic signed [7:0] s_val = 8'hF8;    // signed   — same bits = -8
 
  initial begin
    $display("u_val = %0d (unsigned 248)", u_val);
    $display("s_val = %0d (signed -8)",   s_val);
 
    // >>> on UNSIGNED — no sign extension, fills 0
    $display("u_val >>> 2 = %0d  (zero-fill: 248/4=62)", u_val >>> 2);
 
    // >>> on SIGNED — sign extension, fills 1s
    $display("s_val >>> 2 = %0d  (sign-fill: -8/4=-2)", s_val >>> 2);
 
    // If you WANT signed behavior on an unsigned variable — cast first
    $display("$signed(u_val) >>> 2 = %0d", $signed(u_val) >>> 2);
    // Now sign-extends: -8/4 = -2
 
    $finish;
  end
 
endmodule

u_val = 248 (unsigned 248)
s_val = -8 (signed -8)
u_val >>> 2 = 62  (zero-fill: 248/4=62)
s_val >>> 2 = -2  (sign-fill: -8/4=-2)
$signed(u_val) >>> 2 = -2

logic [7:0]  a = 8'hFF;
logic [15:0] wide_result;
logic [7:0]  narrow_result;
 
// 8-bit context: a stays 8 bits, the MSB shifts out and is lost.
narrow_result = a << 1;          // 8'hFE
 
// 16-bit context: a is EXTENDED TO 16 BITS FIRST, then shifted.
// No concatenation and no cast is needed - the assignment target
// already widened the expression.
wide_result   = a << 1;          // 16'h01FE, not 16'h00FE
 
// These are the same value, written more explicitly. Use them when the
// intent should be visible without knowing the sizing rules - but know
// that they are documentation, not a fix for a truncation that would
// otherwise happen here.
wide_result   = {8'h00, a} << 1; // 16'h01FE
wide_result   = 16'(a)    << 1;  // 16'h01FE
 
// Self-determined context: no assignment target to widen it, so the
// shift is evaluated at 8 bits and the top bit is lost.
$display("in a display arg: 0x%0h", a << 1);   // 0xfe  <-- differs!
$display("narrow_result:    0x%0h", narrow_result); // 0xfe
$display("wide_result:      0x%0h", wide_result);   // 0x1fe

// ── 1. Single-bit mask generation — error injection ───────────────
function logic [31:0] bit_mask(input int pos);
  return 32'h1 << pos;
endfunction
 
// ── 2. Protocol field packing — build from named fields ───────────
function logic [31:0] pack_axi_ctrl(
  input logic [1:0]  burst_type,
  input logic [2:0]  burst_len,
  input logic         write
);
  return ({29'h0, burst_type} << 16)
       | ({29'h0, burst_len}  << 8)
       | {31'h0, write};
endfunction
 
// ── 3. Byte lane enable from address ──────────────────────────────
function logic [3:0] byte_enables(input logic [31:0] addr, input int size);
  logic [3:0] mask = (4'h1 << size) - 4'h1;   // size bytes → N-bit mask
  return mask << addr[1:0];                      // align to byte offset
endfunction
 
// ── 4. Scoreboard: extract field from DUT response ────────────────
function logic [7:0] extract_status(input logic [31:0] reg_val);
  return (reg_val >> 16) & 8'hFF;   // bits [23:16]
endfunction
 
// ── 5. Constraint: aligned address generation ─────────────────────
class AlignedTxn;
  rand logic [31:0] addr;
  rand logic [1:0]  size;   // 0=byte, 1=halfword, 2=word
 
  constraint c_align {
    addr[1:0] == 2'b00;            // word-aligned
    addr inside {[32'h1000:32'h1FFF]};
  }
endclass

// DUT computes signed accumulator / 4
// Scoreboard model uses wrong shift
int accumulator = -100;
 
// BUGGY: logical right shift fills 0s — makes negative → large positive
int result_wrong = accumulator >>  2;
$display("Wrong: %0d", result_wrong);   // 1073741799 — completely wrong
 
// CORRECT: arithmetic right shift preserves sign
int result_right = accumulator >>> 2;
$display("Right: %0d", result_right);   // -25 — correct (-100/4)

logic [7:0] val = 8'hC0;   // 1100_0000
 
// BUGGY: expecting 0x300 but result truncated to 8 bits
logic [7:0] result = val << 2;
$display("result = 0x%0h", result);   // 0x00 — top bits lost!
 
// CORRECT: widen before shifting
logic [9:0] result_wide = {2'b00, val} << 2;
$display("result_wide = 0x%0h", result_wide);   // 0x300 — correct

logic [7:0] data = 8'hF8;   // MSB=1 but type is UNSIGNED
 
// BUGGY: engineer expects sign extension because "MSB is 1"
// But logic [7:0] is unsigned — >>> fills 0s, not the MSB
logic [7:0] wrong = data >>> 2;
$display("Wrong: %0d", wrong);   // 62 — zero filled, not sign extended
 
// CORRECT option 1: declare as signed
logic signed [7:0] s_data = 8'hF8;   // same bits = -8
logic [7:0] correct1 = s_data >>> 2;
$display("Correct1: %0d", correct1);   // -2
 
// CORRECT option 2: cast at the shift expression
logic [7:0] correct2 = $signed(data) >>> 2;
$display("Correct2: %0d", correct2);   // -2

// shift_semantics_proof.sv
//
// Self-checking proof of >> vs >>>, signed vs unsigned operands, and the
// effect of the surrounding expression width. Every claim in this chapter
// has a corresponding check below.
module shift_semantics_proof;
 
  int errors = 0;
 
  task automatic chk(string name, logic [31:0] got, logic [31:0] exp);
    if (got !== exp) begin
      errors++;
      $display("FAIL %-46s got=%08h exp=%08h", name, got, exp);
    end else
      $display("pass %-46s = %08h", name, got);
  endtask
 
  initial begin
    logic signed [7:0] s;
    logic        [7:0] u;
    logic signed [7:0] r8s;
    logic        [7:0] r8u;
    int                r32;
 
    // ================================================================
    // 1. SAME BITS, DIFFERENT DECLARED SIGNEDNESS
    //    u and s hold the identical bit pattern 8'b1111_1000.
    // ================================================================
    s = -8;          // 8'b1111_1000
    u = 8'hF8;       // 8'b1111_1000  - the same bits
 
    r8s = s >>> 2;   chk("signed   s >>> 2  (sign fill)",  r8s, 8'hFE);  // -2
    r8u = u >>> 2;   chk("unsigned u >>> 2  (ZERO fill)",  r8u, 8'h3E);  // +62
 
    // The operator did not change. The DECLARATION did. This is the whole
    // point: >>> is not "the sign-extending shift", it is the shift that
    // respects signedness - and it has none to respect on `u`.
 
    // 2. The cast restores it, for this expression only.
    r8u = $signed(u) >>> 2;
    chk("$signed(u) >>> 2  (cast to signed)",  r8u, 8'hFE);
 
    // 3. >> ignores signedness entirely - both give the zero-filled result.
    r8s = s >> 2;    chk("signed   s >> 2   (still zero fill)", r8s, 8'h3E);
    r8u = u >> 2;    chk("unsigned u >> 2",                     r8u, 8'h3E);
 
    // ================================================================
    // 4. CONTEXT WIDTH - the same expression, two answers
    // ================================================================
    r8s = s >> 1;    chk("s >> 1 into 8-bit  target",  r8s, 8'h7C);       // +124
    r32 = s >> 1;    chk("s >> 1 into 32-bit target",  r32, 32'h7FFF_FFFC);
 
    // Why: assigning to `int` makes the shift a 32-bit expression, so the
    // context-determined left operand is SIGN-extended to 32'hFFFF_FFF8
    // FIRST, and only then shifted right with a zero fill.
    //
    // The arithmetic shift is stable across contexts, because sign-extending
    // and then sign-filling gives the same value at any width:
    r8s = s >>> 1;   chk("s >>> 1 into 8-bit  target",  r8s, 8'hFC);      // -4
    r32 = s >>> 1;   chk("s >>> 1 into 32-bit target",  r32, 32'hFFFF_FFFC); // -4
 
    // 5. Left shifts: <<< is identical to <<, for signed and unsigned alike.
    chk("s << 1  equals  s <<< 1", 8'(s << 1), 8'(s <<< 1));
    chk("u << 1  equals  u <<< 1", 8'(u << 1), 8'(u <<< 1));
 
    // 6. Over-shift. Logical goes to zero; arithmetic goes to the sign.
    chk("u >> 8   (over-shift, logical)",        8'(u >> 8),   8'h00);
    chk("s >>> 8  (over-shift, negative)",       8'(s >>> 8),  8'hFF);
    s = 8'sd8;
    chk("s >>> 8  (over-shift, positive)",       8'(s >>> 8),  8'h00);
 
    // 7. Floor division, not truncation. This is the reference-model trap.
    s = -7;
    chk("-7 >>> 2  is -2 (floor)",   8'(s >>> 2), 8'hFE);
    chk("-7 / 4    is -1 (truncate)", 8'(s / 4),  8'hFF);
    // They agree only when the division is exact:
    s = -8;
    chk("-8 >>> 2  ==  -8 / 4",      8'(s >>> 2), 8'(s / 4));
 
    if (errors == 0) $display("\nshift_semantics_proof: ALL CHECKS PASSED");
    else             $display("\nshift_semantics_proof: %0d FAILURES", errors);
    $finish;
  end
endmodule