Concatenation, Replication & Conditional

// ── CONCATENATION ────────────────────────────────────────────────────
// result = {expr1, expr2, ..., exprN}
// Width  = width(expr1) + width(expr2) + ... + width(exprN)
 
logic [3:0] a = 4'hA;
logic [3:0] b = 4'hB;
logic [7:0] ab = {a, b};         // 8'hAB — a in upper 4 bits, b in lower 4
 
// Nested concatenation — braces flatten automatically
logic [11:0] abc = {a, {b, 4'hC}};  // same as {a, b, 4'hC} = 12'hABC
 
// ILLEGAL: unsized literal has no defined width
// logic [11:0] bad = {8, a, b};   // ERROR — use 4'd8 instead
 
// ── REPLICATION ──────────────────────────────────────────────────────
// result = {count{expr}}   — count must be a constant expression
 
logic [7:0] pat  = {4{2'b10}};     // 8'b10101010 — replicate 2'b10 four times
logic [7:0] ones = {8{1'b1}};      // 8'hFF
 
parameter PAD = 4;
logic [11:0] padded = {a, {PAD{1'b0}}}; // {4'hA, 4'h0} = 12'hA00 — uses parameter: legal
 
// Sign extension using replication of MSB
logic signed [3:0] s4  = -3;              // 4'b1101
logic signed [7:0] s8  = {{4{s4[3]}}, s4};  // 8'b1111_1101 = -3
 
// ── CONDITIONAL ──────────────────────────────────────────────────────
// result = condition ? expr_true : expr_false
// Result width is determined by context (e.g., LHS width)
// Both branches are syntactically evaluated every time (no short-circuit)
 
logic       sel = 1'b1;
logic [7:0] mux_out = sel ? 8'hFF : 8'h00;  // 8'hFF
 
// Nested conditional — priority mux chain
logic [1:0] s;
logic [7:0] y = (s == 2'b00) ? a :
               (s == 2'b01) ? b : 8'hFF;  // 2-level priority mux

module tb_core_operators;
 
  logic [3:0] a    = 4'hA;          // 1010
  logic [3:0] b    = 4'hB;          // 1011
  logic [3:0] c    = 4'hC;          // 1100
  logic       sel;
 
  logic signed [3:0] sneg = -3;     // 4'b1101
  logic signed [7:0] sext;
 
  initial begin
 
    // ── Concatenation ──────────────────────────────────────────────
    $display("[Concat] {a,b}      = 0x%02h  (8-bit: AB)",  {a, b});
    $display("[Concat] {a,b,c}    = 0x%03h  (12-bit: ABC)", {a, b, c});
 
    // ── Replication ────────────────────────────────────────────────
    $display("[Replic] {4{a}}     = 0x%04h  (16-bit: AAAA)", {4{a}});
    $display("[Replic] {2{a,b}}   = 0x%04h  (16-bit: ABAB)", {2{a, b}});
    $display("[Replic] {4{2'b10}} = %08b",              {4{2'b10}});
 
    // ── Sign extension via replication ─────────────────────────────
    sext = {{4{sneg[3]}}, sneg};    // replicate MSB 4×, append original 4 bits
    $display("[SignExt] -3: 4'b%04b → 8'b%08b (%0d)", sneg, sext, $signed(sext));
 
    // ── Conditional ────────────────────────────────────────────────
    sel = 1'b1;
    $display("[Cond] sel=1 → 0x%h", sel ? a : b);   // A
    sel = 1'b0;
    $display("[Cond] sel=0 → 0x%h", sel ? a : b);   // B
 
    $finish;
  end
 
endmodule

[Concat] {a,b}      = 0xAB  (8-bit: AB)
[Concat] {a,b,c}    = 0xABC  (12-bit: ABC)
[Replic] {4{a}}     = 0xAAAA  (16-bit: AAAA)
[Replic] {2{a,b}}   = 0xABAB  (16-bit: ABAB)
[Replic] {4{2'b10}} = 10101010
[SignExt] -3: 4'b1101 → 8'b11111101 (-3)
[Cond] sel=1 → 0xA
[Cond] sel=0 → 0xB

// STATUS register layout:
// [31:24] = err_code  (8 bits)   [23:16] = flags    (8 bits)
// [15:8]  = burst_len (8 bits)   [7:0]   = state    (8 bits)
 
module tb_reg_packing;
 
  logic [7:0]  err_code  = 8'hAB;
  logic [7:0]  flags     = 8'b1010_0011;
  logic [7:0]  burst_len = 8'd15;
  logic [7:0]  state     = 8'h05;
  logic [31:0] status;
 
  initial begin
 
    // ── Pack all 4 fields into one 32-bit word ─────────────────────
    status = {err_code, flags, burst_len, state};
    $display("Status  = 0x%08h", status);            // 0xABA30F05
 
    // ── Unpack by slicing ──────────────────────────────────────────
    $display("err_code  = 0x%02h", status[31:24]);   // AB
    $display("flags     = 8'b%08b", status[23:16]);  // 10100011
    $display("burst_len = %0d",     status[15:8]);   // 15
    $display("state     = 0x%02h",  status[7:0]);    // 05
 
    // ── Read-modify-write: update only the state field ─────────────
    // Replace lower 8 bits, keep upper 24 unchanged
    status = {status[31:8], 8'hFF};
    $display("Updated = 0x%08h", status);           // 0xABA30FFF
 
    $finish;
  end
 
endmodule

Status  = 0xABA30F05
err_code  = 0xAB
flags     = 8'b10100011
burst_len = 15
state     = 0x05
Updated = 0xABA30FFF

// AXI-like beat: {tid[3:0], data[15:0]} = 20-bit frame
 
module tb_scoreboard;
 
  // Build expected beat from known field values
  function automatic logic [19:0] pack_beat(
    input logic [3:0]  tid,
    input logic [15:0] payload
  );
    return {tid, payload};
  endfunction
 
  // Parse and validate received beat
  task automatic check_beat(
    input logic [19:0] received,
    input logic [3:0]  exp_tid,
    input logic [15:0] exp_data
  );
    logic [19:0] expected  = pack_beat(exp_tid, exp_data);
    logic [3:0]  got_tid   = received[19:16];
    logic [15:0] got_data  = received[15:0];
 
    if (received !== expected)
      $error("MISMATCH got=0x%05h exp=0x%05h [tid:%0h→%0h data:%04h→%04h]",
             received, expected, exp_tid, got_tid, exp_data, got_data);
    else
      $display("PASS  beat=0x%05h  tid=0x%h  data=0x%04h",
               received, got_tid, got_data);
  endtask
 
  initial begin
    check_beat(20'hA_CAFE, 4'hA, 16'hCAFE);  // PASS
    check_beat(20'hB_CAFE, 4'hA, 16'hCAFE);  // MISMATCH: tid corrupted
    check_beat(20'hA_1234, 4'hA, 16'hCAFE);  // MISMATCH: data wrong
    $finish;
  end
 
endmodule

PASS  beat=0xACAFE  tid=0xA  data=0xCAFE
MISMATCH got=0xBCAFE exp=0xACAFE [tid:A→B data:CAFE→CAFE]
MISMATCH got=0xA1234 exp=0xACAFE [tid:A→A data:CAFE→1234]

module tb_corner_cases;
 
  logic [7:0]  val_a = 8'hF0;   // 1111_0000
  logic [7:0]  val_b = 8'hFF;   // 1111_1111
  logic [7:0]  result;
  logic        cond;
  logic [15:0] pkt;
 
  initial begin
 
    // ── Corner 1: X condition — bitwise merge, not blanket X ──────
    cond = 1'bx;
 
    result = cond ? 8'hAA : 8'hAA;          // identical branches
    $display("X cond, same values  : 0x%02h", result);  // AA — no X!
 
    result = cond ? val_a : val_b;             // F0 vs FF
    $display("X cond, F0 vs FF     : %08b",   result);  // 1111_xxxx
 
    result = cond ? 8'hFF : 8'h00;           // all bits differ
    $display("X cond, FF vs 00     : %08b",   result);  // xxxxxxxx
 
    // ── Corner 2: Nested replication ──────────────────────────────
    $display("{3{4'b0101}}         : %012b", {3{4'b0101}});  // 010101010101
    $display("{2{3{2'b01}}}        : %012b", {2{3{2'b01}}});  // 010101010101
 
    // ── Corner 3: Concat + Replication = Frame Builder ────────────
    // Frame: 8-bit sync header + 4 pairs of alternating bits
    pkt = {8'hA5, {4{2'b10}}};
    $display("Frame (sync+pattern) : 0x%04h", pkt);  // 0xA5AA
 
    // ── Corner 4: Z condition — identical behavior to X ───────────
    cond = 1'bz;
    result = cond ? val_a : val_b;
    $display("Z cond, F0 vs FF     : %08b",   result);  // 1111_xxxx
 
    $finish;
  end
 
endmodule

X cond, same values  : 0xAA
X cond, F0 vs FF     : 1111xxxx
X cond, FF vs 00     : xxxxxxxx
{3{4'b0101}}         : 010101010101
{2{3{2'b01}}}        : 010101010101
Frame (sync+pattern) : 0xA5AA
Z cond, F0 vs FF     : 1111xxxx

logic signed [7:0] a = -1;      // 8'hFF
logic signed [7:0] b = -1;      // 8'hFF
logic signed [31:0] r1, r2;
 
r1 = {a, b};             // 16'hFFFF is UNSIGNED -> zero-extends -> 32'h0000_FFFF
r2 = $signed({a, b});    // cast to signed        -> sign-extends -> 32'hFFFF_FFFF

// Arithmetic on a concatenation: unsigned, so this compares 65535 > 0
if ({a, b} > 0) ...              // TRUE, even though a and b are both -1
 
// Arithmetic right shift on a concatenation: nothing to sign-extend,
// so >>> fills zeros exactly as >> would.
r1 = {a, b} >>> 4;               // 32'h0000_0FFF, not a sign-preserving shift
r2 = $signed({a, b}) >>> 4;      // sign-extended first, then sign-filled

localparam int PAD = 0;
 
logic [7:0] ok   = {{PAD{1'b0}}, 8'hA5};   // legal: PAD=0 contributes nothing
                                           // result is simply 8'hA5
// logic [7:0] bad = {PAD{1'b0}};          // illegal: nothing of positive size

logic [3:0] a = 4'hF;
logic [3:0] b = 4'hF;
logic [7:0] result8;
logic [9:0] result10;
 
result8  = {a, b};          // {4'hF, 4'hF} = 8'hFF — exact fit
result10 = {a, b};          // 8'hFF assigned to 10-bit → zero-extended: 10'h0FF
 
// Truncation: concat wider than destination
logic [5:0] narrow;
narrow = {a, b};            // 8'hFF → truncated to 6'b11_1111 = 6'h3F — MSBs lost!
 
// Safe approach: always match concat width to destination width
logic [7:0] pkt;
pkt = {4'h0, a};             // explicit zero-pad to reach 8 bits: 8'h0F
$display("pkt = 0x%02h", pkt);  // 0F

// ── 1. MONITOR: parse incoming AHB address phase ──────────────────
// Raw bus: {haddr[31:0], htrans[1:0], hsize[2:0], hwrite} = 36 bits
logic [35:0] raw_beat;
logic [31:0] mon_addr  = raw_beat[35:4];
logic [1:0]  mon_trans = raw_beat[3:2];
logic [2:0]  mon_size  = {2'b00, raw_beat[1]};   // zero-extend 1-bit size field
logic        mon_write = raw_beat[0];
 
// ── 2. SCOREBOARD: build expected output for comparison ───────────
function automatic logic [35:0] build_ahb(
  input logic [31:0] addr, input logic [1:0] trans,
  input logic        wr,   input logic [1:0] size
);
  return {addr, trans, size, wr};
endfunction
 
// ── 3. DRIVER: conditional data selection ────────────────────────
logic [7:0] drive_data = is_error_injection ? err_pattern : normal_data;
 
// ── 4. CONSTRAINT: conditional distribution ──────────────────────
// In a class:
//   rand logic [31:0] addr;
//   constraint addr_align { addr == {addr[31:2], 2'b00}; } // force 4-byte align
 
// ── 5. ASSERTION: check field value in packed word ────────────────
// Check that the opcode field [15:12] in a 16-bit command is never 0
// assert property (@(posedge clk) cmd_valid |-> cmd[15:12] != 4'h0);
 
// ── 6. COVERAGE: combine fields for cross coverage ────────────────
// coverpoint {prot_type, burst_len} covers all combinations
// cross {wr_rd, beat_count} cross-covers read/write vs burst depth
 
// ── 7. ERROR INJECTION: flip a specific bit using concat ──────────
function automatic logic [31:0] inject_bit_error(
  input logic [31:0] data,
  input int           bit_pos
);
  // flip bit at bit_pos using conditional rebuild
  logic [31:0] mask = 32'h1 << bit_pos;
  return data ^ mask;
endfunction

logic [7:0] data = 8'hAB;
logic [11:0] pkt;
 
// BUGGY: 5 is an unsized integer — no defined width
pkt = {4, data};    // COMPILE ERROR: unsized literal in concatenation
 
// FIXED: always size the literal explicitly
pkt = {4'd4, data};    // 4-bit value 4 = 4'b0100, then 8'hAB → 12'h4AB
 
// If you want to prepend 4 zero bits (zero-extend data to 12 bits):
pkt = {4'h0, data};    // 12'h0AB
 
// Common alternate: use streaming assignment or cast
pkt = {12'(data)};     // zero-extends data to 12 bits — same as {4'h0, data}

logic [3:0] opcode = 4'hA;
logic [2:0] mode   = 3'b110;   // only 3 bits wide
logic [7:0] cmd;
 
// BUGGY: packing 7 bits (4+3) into 8-bit cmd
// Concat result = 7'b1010_110, zero-padded to 8 bits → cmd = 8'b0_1010_110 = 8'h56
// Engineer expects opcode in bits [7:4] but it ends up in bits [6:3] — off by one!
cmd = {opcode, mode};
 
// CORRECT: ensure total operand widths equal destination width
logic [3:0] mode4 = {1'b0, mode};  // widen mode to 4 bits first
cmd = {opcode, mode4};               // 4+4 = 8 bits: 8'hA6
 
// Or pad explicitly inside the concat:
cmd = {opcode, 1'b0, mode};          // 4+1+3 = 8: same result, intent is clear

// RTL: output mux gated by 'valid' signal
logic        valid;           // not initialized — starts as X at time 0
logic [7:0] data_in = 8'hFF;
logic [7:0] data_out;
 
assign data_out = valid ? data_in : 8'h00;
// At time 0: valid=X, data_in=8'hFF, 8'h00
// Bit merge: 8'hFF vs 8'h00 → all bits differ → data_out = 8'hXX
// Every downstream consumer of data_out is now also X
 
// FIX 1: initialize in declaration
logic valid = 1'b0;          // data_out starts at 8'h00 — clean
 
// FIX 2: asynchronous reset drives known state
always_ff @(posedge clk or posedge rst)
  if (rst) valid <= 1'b0;
  else     valid <= next_valid;
 
// FIX 3: testbench — drive before time 0 using initial block
initial begin
  valid = 1'b0;     // immediate assignment — active before any clock edge
  @(posedge clk);
  valid = 1'b1;
end

int           pad_n = 8;      // runtime variable
logic [7:0]  data  = 8'hAB;
logic [15:0] padded;
 
// BUGGY: pad_n is a variable — ILLEGAL, will not compile
// padded = {data, {pad_n{1'b0}}};   // ERROR
 
// FIXED option 1: use a parameter (most common solution)
parameter PAD_BITS = 8;
padded = {data, {PAD_BITS{1'b0}}};       // legal: PAD_BITS is a compile-time constant
 
// FIXED option 2: if runtime width is genuinely needed, use shift
padded = {8'h00, data} << pad_n;         // variable shift — legal, generates barrel shifter
// Note: semantics differ from padding — understand what you need
 
// FIXED option 3: use localparam in a generate block
// for parameterized modules — set pad width via module parameter

logic [7:0] wide_val   = 8'hFF;
logic [3:0] narrow_val = 4'hF;    // 4'b1111
logic [7:0] result;
logic        sel = 1'b0;
 
// BUGGY EXPECTATION: engineer expects sel=0 → result = 8'hFF (all ones)
result = sel ? wide_val : narrow_val;
// narrow_val=4'hF in an 8-bit context → zero-extended to 8'h0F — NOT 8'hFF!
$display("result = 0x%02h", result);   // 0x0F — upper nibble is ZERO
 
// FIX 1: if intent is to replicate the nibble to fill 8 bits:
result = sel ? wide_val : {2{narrow_val}};  // {4'hF, 4'hF} = 8'hFF
 
// FIX 2: if intent is sign extension (narrow is signed):
logic signed [3:0] s_narrow = 4'hF;   // -1 in signed 4-bit
result = sel ? wide_val : $unsigned({{4{s_narrow[3]}}, s_narrow});
// s_narrow[3]=1 → sign extend: 8'b1111_1111 = 8'hFF
 
// FIX 3: always match branch widths explicitly to make intent clear
result = sel ? wide_val : {4'h0, narrow_val};  // explicit zero-extend: 8'h0F

// concat_semantics_proof.sv
//
// Self-checking proof of: concatenation signedness, zero replication,
// the conditional X-merge, and how ?: differs from if/else under X.
module concat_semantics_proof;
 
  int errors = 0;
  localparam int PAD = 0;          // the degenerate parameterized case
 
  task automatic chk(string name, logic [31:0] got, logic [31:0] exp);
    if (got !== exp) begin
      errors++;
      $display("FAIL %-50s got=%08h exp=%08h", name, got, exp);
    end else
      $display("pass %-50s = %08h", name, got);
  endtask
 
  initial begin
    // ================================================================
    // 1. A CONCATENATION IS ALWAYS UNSIGNED
    // ================================================================
    begin
      logic signed  [7:0] a = -1, b = -1;   // both 8'hFF
      logic signed [31:0] r1, r2;
 
      r1 = {a, b};
      r2 = $signed({a, b});
      chk("{a,b} into 32-bit  -> ZERO-extended", r1, 32'h0000_FFFF);
      chk("$signed({a,b})     -> sign-extended", r2, 32'hFFFF_FFFF);
 
      // Consequences, both of which surprise people:
      chk("{a,b} > 0  is TRUE  (unsigned 65535)", 32'({a, b} > 0), 32'd1);
      chk("{a,b} >>> 4  fills ZERO (nothing signed to fill with)",
          32'({a, b} >>> 4), 32'h0000_0FFF);
      chk("$signed({a,b}) >>> 4  fills the sign",
          $signed({a, b}) >>> 4, 32'hFFFF_FFFF);
 
      // The sign-extension IDIOM builds the right bits, wrong type:
      begin
        logic signed [3:0] s4 = -3;         // 4'b1101
        chk("{{4{s4[3]}}, s4} bits are correct",
            8'({{4{s4[3]}}, s4}), 8'b1111_1101);
        // ...but the expression is unsigned, so in a wider context:
        chk("...and it ZERO-extends into 32 bits",
            32'({{4{s4[3]}}, s4}), 32'h0000_00FD);
      end
    end
 
    // ================================================================
    // 2. ZERO REPLICATION - legal inside a concatenation with a
    //    positive-size operand. This must ELABORATE, which is the test.
    // ================================================================
    chk("{{PAD{1'b0}}, 8'hA5} with PAD=0", 8'({{PAD{1'b0}}, 8'hA5}), 8'hA5);
    // A standalone {PAD{1'b0}} would be illegal and is deliberately absent.
 
    // ================================================================
    // 3. THE CONDITIONAL X-MERGE - bit by bit, not a random branch
    // ================================================================
    begin
      logic       sel = 1'bx;
      logic [3:0] a   = 4'b1010;
      logic [3:0] b   = 4'b1001;
      logic [3:0] y_cond, y_if;
 
      y_cond = sel ? a : b;              // MERGE
      if (sel) y_if = a; else y_if = b;  // procedural if - takes ELSE
 
      chk("sel=x : (sel ? a : b)  -> 4'b10xx", 4'(y_cond), 4'b10xx);
      chk("sel=x : if/else        -> 4'b1001", 4'(y_if),   4'b1001);
      // ^ The SAME condition and the SAME two values give different
      //   results. ?: is X-pessimistic; procedural if is X-optimistic.
 
      // Bits that AGREE stay known; bits that DIFFER become X:
      chk("1'bx ? 8'hF0 : 8'hFF -> 8'b1111_xxxx",
          8'(1'bx ? 8'hF0 : 8'hFF), 8'b1111_xxxx);
      chk("1'bx ? 8'hFF : 8'h00 -> all bits differ -> 8'hxx",
          8'(1'bx ? 8'hFF : 8'h00), 8'bxxxx_xxxx);
      chk("1'bx ? 8'hA5 : 8'hA5 -> branches identical -> 8'hA5",
          8'(1'bx ? 8'hA5 : 8'hA5), 8'hA5);
      // ^ The last one is the proof that it is a MERGE and not a
      //   selection: with identical branches the result is fully known
      //   even though the select is completely unknown.
 
      // 1'bz on the condition behaves the same as 1'bx:
      chk("1'bz ? 8'hF0 : 8'hFF -> same merge",
          8'(1'bz ? 8'hF0 : 8'hFF), 8'b1111_xxxx);
    end
 
    if (errors == 0) $display("\nconcat_semantics_proof: ALL CHECKS PASSED");
    else             $display("\nconcat_semantics_proof: %0d FAILURES", errors);
    $finish;
  end
endmodule