Relational & Equality Operators

// ── Relational operators ─────────────────────────────────────────
result = (a <  b);    // less than
result = (a >  b);    // greater than
result = (a <= b);    // less than or equal
result = (a >= b);    // greater than or equal
 
// ── Logical equality (4-state — can return X) ────────────────────
result = (a == b);    // logical equal     — returns X if a or b has X/Z
result = (a != b);    // logical not-equal  — returns X if a or b has X/Z
 
// ── Case equality (2-state — always returns 0 or 1) ─────────────
result = (a === b);   // case equal     — exact bit match, X matches X, Z matches Z
result = (a !== b);   // case not-equal — any bit difference, including X vs 0
 
// ── Common patterns ──────────────────────────────────────────────
if (dut_out !== expected)   // scoreboard check — catches X in dut_out
    $error("Mismatch!");
 
if (signal === 1'bx)        // explicit X detection
    $warning("X on signal");
 
if ($isunknown(bus))         // system function — any bit X or Z
    $error("X/Z on bus");

module tb_comparison_basic;
 
  int a = 10, b = 20, c = 10;
 
  initial begin
 
    // ── Relational operators ──────────────────────────────────────
    $display("a < b   : %0b", a <  b);    // 1
    $display("a > b   : %0b", a >  b);    // 0
    $display("a <= c  : %0b", a <= c);    // 1  (equal counts)
    $display("a >= b  : %0b", a >= b);    // 0
 
    // ── Logical equality — clean values, == and === agree ─────────
    $display("a == c  : %0b", a == c);    // 1
    $display("a != b  : %0b", a != b);    // 1
 
    // ── Case equality — same result here, but NEVER returns X ─────
    $display("a === c : %0b", a === c);   // 1
    $display("a !== b : %0b", a !== b);   // 1
 
    $finish;
  end
 
endmodule

a < b   : 1
a > b   : 0
a <= c  : 1
a >= b  : 0
a == c  : 1
a != b  : 1
a === c : 1
a !== b : 1

module tb_equality_x;
 
  logic [7:0] dut_out;
  logic [7:0] expected = 8'hA5;
 
  initial begin
 
    // ── Case 1: clean, matching ───────────────────────────────────
    dut_out = 8'hA5;
    $display("[CLEAN MATCH]    == %b   !== %b",
              dut_out == expected, dut_out !== expected);
    // == 1,  !== 0  — both agree: it's a match
 
    // ── Case 2: clean, NOT matching ──────────────────────────────
    dut_out = 8'h00;
    $display("[CLEAN MISMATCH] == %b   !== %b",
              dut_out == expected, dut_out !== expected);
    // == 0,  !== 1  — both agree: it's a mismatch
 
    // ── Case 3: DUT output is all X ──────────────────────────────
    dut_out = 8'hxx;
    $display("[DUT IS X]       == %b   !== %b",
              dut_out == expected, dut_out !== expected);
    // == x,  !== 1  ← CRITICAL: == returns x (false in if)
    //                            !== returns 1 (mismatch detected)
 
    // ── Case 4: DUT output is Z (tristate/undriven) ──────────────
    dut_out = 8'hzz;
    $display("[DUT IS Z]       == %b   !== %b",
              dut_out == expected, dut_out !== expected);
    // == x,  !== 1  — same behavior as X
 
    // ── Case 5: both same X pattern ──────────────────────────────
    dut_out  = 8'hxx;
    expected = 8'hxx;
    $display("[BOTH X]         == %b   === %b",
              dut_out == expected, dut_out === expected);
    // == x,  === 1  — case equality: X matches X exactly
 
    $finish;
  end
 
endmodule

[CLEAN MATCH]    == 1   !== 0
[CLEAN MISMATCH] == 0   !== 1
[DUT IS X]       == x   !== 1
[DUT IS Z]       == x   !== 1
[BOTH X]         == x   === 1

class DataScoreboard;
 
  int pass_cnt = 0;
  int fail_cnt = 0;
  int xz_cnt   = 0;
 
  // Use !== so that X/Z in dut_out is always caught
  function void check(
    input logic [31:0] expected,
    input logic [31:0] dut_out,
    input string        tag = ""
  );
    if (expected !== dut_out) begin
      if ($isunknown(dut_out)) begin
        // X or Z on DUT output — different root cause than a value error
        xz_cnt++;
        $error("[SB] X/Z DETECTED %s | exp=0x%08h got=%b",
               tag, expected, dut_out);
      end else begin
        fail_cnt++;
        $error("[SB] MISMATCH     %s | exp=0x%08h got=0x%08h",
               tag, expected, dut_out);
      end
    end else begin
      pass_cnt++;
    end
  endfunction
 
  function void report();
    $display("[SB] Results: PASS=%0d  FAIL=%0d  X/Z=%0d",
             pass_cnt, fail_cnt, xz_cnt);
    if (fail_cnt + xz_cnt == 0)
      $display("[SB] ALL CHECKS PASSED");
  endfunction
 
endclass
 
module tb_scoreboard;
 
  DataScoreboard sb;
 
  initial begin
    sb = new();
 
    sb.check(32'hA5A5_A5A5, 32'hA5A5_A5A5, "txn_0");   // PASS
    sb.check(32'hA5A5_A5A5, 32'h0000_0000, "txn_1");   // FAIL
    sb.check(32'hA5A5_A5A5, 32'hxxxx_xxxx, "txn_2");   // X detected
 
    sb.report();
    $finish;
  end
 
endmodule

[SB] MISMATCH     txn_1 | exp=0xa5a5a5a5 got=0x00000000
[SB] X/Z DETECTED txn_2 | exp=0xa5a5a5a5 got=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
[SB] Results: PASS=1  FAIL=1  X/Z=1

module tb_signed_comparison;
 
  logic        [7:0] u_val = 8'hF0;   // unsigned: 240
  logic signed [7:0] s_val = 8'hF0;   // signed:   -16  (same bit pattern!)
 
  initial begin
    // Same bits — different numeric meaning
    $display("u_val = %0d  (0x%0h)", u_val, u_val);   // 240
    $display("s_val = %0d  (0x%0h)", s_val, s_val);   // -16
 
    // Unsigned comparison: 240 > 127 → TRUE
    if (u_val > 8'h7F)
      $display("u_val > 0x7F: TRUE");
 
    // Signed comparison: -16 > 127 → FALSE
    if (s_val > 8'sh7F)
      $display("s_val > 0x7F: TRUE");
    else
      $display("s_val > 0x7F: FALSE  (signed: -16 is not > 127)");
 
    // Mixed comparison — unsigned wins, signed treated as unsigned
    // u_val (unsigned) vs integer (signed) → comparison is unsigned
    int threshold = -1;
    if (u_val < threshold)
      // threshold (-1) as unsigned 32-bit = 4294967295
      // 240 < 4294967295 → TRUE — unexpected!
      $display("u_val < -1: TRUE  ← mixed sign trap!");
 
    $finish;
  end
 
endmodule

u_val = 240  (0xf0)
s_val = -16  (0xf0)
u_val > 0x7F: TRUE
s_val > 0x7F: FALSE  (signed: -16 is not > 127)
u_val < -1: TRUE  ← mixed sign trap!

logic [7:0] count = 8'b1010_xxxx;   // upper nibble known, lower unknown
logic       r;
 
r = (count > 8'd0);      // 1'bx  - NOT 1, even though the top nibble
                         //         alone guarantees count > 0
r = (count < 8'd255);    // 1'bx
r = (count >= 8'd0);     // 1'bx  - not even this is 1

// This looks like a safety check. It is not, once addr can carry X.
if (addr < LIMIT) begin
  do_access();
end else begin
  report_out_of_range();      // <-- an X addr silently lands HERE
end
 
// And this is worse, because the "safe" branch is the empty one:
if (fill_level > THRESHOLD)
  assert_backpressure();      // <-- an X fill_level never asserts it

// Explicit, and says what it means.
if ($isunknown(addr))      report_undriven_address();
else if (addr < LIMIT)     do_access();
else                       report_out_of_range();
 
// Or assert the precondition, so an X addr is a test failure rather
// than a silently mis-routed branch.
a_addr_known: assert property (@(posedge clk) disable iff (!rst_n)
  req |-> !$isunknown(addr))
  else $error("address is X while req is asserted");

// ── 1. Scoreboard mismatch check — always use !== ─────────────────
function void compare(logic [31:0] exp, logic [31:0] got);
  if (exp !== got)   // !== catches X/Z, != does not
    $error("MISMATCH exp=%0h got=%0h", exp, got);
endfunction
 
// ── 2. X-check assertion — fires if DUT output goes X after reset ─
assert property (@(posedge clk) disable iff (!rst_n)
  !$isunknown(dut_data_out))
else $error("X detected on data_out at time %0t", $time);
 
// ── 3. Reset check — all registers should be 0 after reset ───────
task automatic check_reset();
  @(negedge rst_n);
  @(posedge rst_n);
  if (dut_status_reg !== 32'h0)
    $error("Reset check FAIL: status_reg = 0x%08h", dut_status_reg);
  else
    $display("Reset check PASS");
endtask
 
// ── 4. Bus arbitration — check for tristate release ───────────────
task automatic wait_bus_release();
  int timeout = 100;
  while (bus_data !== 32'hzzzz_zzzz && timeout > 0) begin
    @(posedge clk);
    timeout--;
  end
  if (timeout == 0)
    $error("Timeout: bus not released (still driving)");
endtask
 
// ── 5. Coverage guard — skip sample if signal has unknowns ────────
function void sample(logic [7:0] op_code);
  if (!$isunknown(op_code))   // don't sample X into coverage bins
    cov_op.sample();
endfunction

// BUGGY scoreboard — copied from C++ habit
function void check_buggy(logic [31:0] exp, logic [31:0] got);
  if (exp != got)                // != returns X when got is X
    $error("Mismatch!");           // X in if-condition → FALSE → never fires
  // Result: DUT can output X on every transaction and this never reports.
endfunction
 
// Demonstration
logic [31:0] expected = 32'hA5A5_A5A5;
logic [31:0] dut_out  = 32'hxxxx_xxxx;  // DUT is completely broken
 
check_buggy(expected, dut_out);
// Output: (nothing) — $error never fires — test passes — BUG SHIPS

// CORRECT scoreboard — !== always returns 0 or 1
function void check_correct(logic [31:0] exp, logic [31:0] got);
  if (exp !== got)               // !== returns 1 when got is X → fires
    $error("Mismatch! exp=0x%08h got=%b", exp, got);
endfunction
 
check_correct(expected, dut_out);
// Output: ERROR: Mismatch! exp=0xa5a5a5a5 got=xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
// Bug is caught. Test fails correctly.

// BUGGY RTL — === is a simulation-only operator
always_ff @(posedge clk) begin
  if (data_in === 8'hFF)    // === left here from debug session
    state <= DONE;
end
// Synthesis may warn, replace with ==, or behave unexpectedly
// Simulation passes. Silicon may not match simulation behavior.

// CORRECT RTL — == is synthesizable
always_ff @(posedge clk) begin
  if (data_in == 8'hFF)     // == is synthesizable, maps to comparator
    state <= DONE;
end

// BUGGY — mixed sign comparison
logic [7:0] addr_offset;   // unsigned — DUT address output
int          limit = -1;    // programmer uses -1 as sentinel: "no limit"
 
// Bug: addr_offset is unsigned, so comparison becomes unsigned
// limit (-1 as int) = 0xFFFFFFFF unsigned = 4294967295
// addr_offset (any 8-bit value) < 4294967295 → ALWAYS TRUE
if (addr_offset < limit)
  $display("offset within limit");   // Always fires — guard is useless

// FIX 1 — Use int for offset so both are signed
int addr_offset;   // signed — comparison context is now signed
int limit = -1;
if (limit < 0 || addr_offset < limit)  // explicit sentinel guard
  $display("offset within limit");
 
// FIX 2 — Explicit cast to force signed context
if ($signed(addr_offset) < limit)
  $display("offset within limit");

// comparison_semantics_proof.sv
//
// Self-checking proof of ==, !=, ===, !==, ==?, and the relational
// operators under X/Z, plus the signed/unsigned comparison trap.
module comparison_semantics_proof;
 
  int errors = 0;
 
  task automatic chk(string name, logic got, logic exp);
    if (got !== exp) begin
      errors++;
      $display("FAIL %-52s got=%b exp=%b", name, got, exp);
    end else
      $display("pass %-52s = %b", name, got);
  endtask
 
  initial begin
    // ================================================================
    // 1. THE CANONICAL MATRIX - one value, three equality operators
    //    a carries an X and a Z in its low nibble.
    // ================================================================
    begin
      logic [7:0] a = 8'b1010_01xz;
 
      // ...against the IDENTICAL literal
      chk("a ==  8'b1010_01xz  -> X   (propagates)",  a ==  8'b1010_01xz, 1'bx);
      chk("a === 8'b1010_01xz  -> 1   (literal match)",a === 8'b1010_01xz, 1'b1);
      chk("a ==? 8'b1010_01xz  -> 1   (right wildcards)",a ==? 8'b1010_01xz, 1'b1);
 
      // ...against a FULLY KNOWN value
      chk("a ==  8'b1010_0100  -> X",                 a ==  8'b1010_0100, 1'bx);
      chk("a === 8'b1010_0100  -> 0",                 a === 8'b1010_0100, 1'b0);
      chk("a ==? 8'b1010_0100  -> 0  (NOT masked)",   a ==? 8'b1010_0100, 1'b0);
 
      // ...against a pattern that masks the low nibble
      chk("a ==? 8'b1010_xxxx  -> 1  (masked)",       a ==? 8'b1010_xxxx, 1'b1);
 
      // The inverses are exact complements of the case forms:
      chk("a !== 8'b1010_0100  -> 1",                 a !== 8'b1010_0100, 1'b1);
      chk("a !=  8'b1010_0100  -> X  (propagates)",   a !=  8'b1010_0100, 1'bx);
    end
 
    // ================================================================
    // 2. RELATIONAL OPERATORS RETURN X - they do NOT return false
    // ================================================================
    begin
      logic [7:0] count = 8'b1010_xxxx;
 
      chk("count >  8'd0    -> X  (not 1)",  count >  8'd0,   1'bx);
      chk("count <  8'd255  -> X",           count <  8'd255, 1'bx);
      chk("count >= 8'd0    -> X  (not 1!)", count >= 8'd0,   1'bx);
      // ^ True for EVERY resolution of those X bits, and still X.
      //   There is no case-relational operator to fix this.
 
      // A fully known operand behaves normally:
      count = 8'd10;
      chk("known: 10 > 0     -> 1",          count >  8'd0,   1'b1);
    end
 
    // ================================================================
    // 3. WHY THE SCOREBOARD PASSES - X takes the else branch
    // ================================================================
    begin
      logic [7:0] got = 8'hxx, expected = 8'hA5;
      bit fired_ne, fired_case;
 
      fired_ne   = 1'b0;  fired_case = 1'b0;
      if (got !=  expected) fired_ne   = 1'b1;   // X -> else -> never fires
      if (got !== expected) fired_case = 1'b1;   // 1  -> fires correctly
 
      chk("if (got !=  expected)  fires?  NO  (silent pass)", fired_ne,   1'b0);
      chk("if (got !== expected)  fires?  YES",               fired_case, 1'b1);
    end
 
    // ================================================================
    // 4. SIGNED VS UNSIGNED - the comparison INVERTS
    // ================================================================
    begin
      logic [7:0] data = 8'd10;
      int         lim  = -1;
 
      chk("data > lim   (mixed -> lim reads as huge)", data > lim,          1'b0);
      chk("$signed(data) > lim  (both signed)",        $signed(data) > lim, 1'b1);
 
      // The same trap with two same-width operands:
      chk("8'shF0 > 8'sh0F  (-16 > 15)",  8'shF0 > 8'sh0F,  1'b0);
      chk("8'hF0  > 8'h0F   (240 > 15)",  8'hF0  > 8'h0F,   1'b1);
      // ^ Identical bits. Opposite answers. Declared signedness decides.
    end
 
    if (errors == 0) $display("\ncomparison_semantics_proof: ALL CHECKS PASSED");
    else             $display("\ncomparison_semantics_proof: %0d FAILURES", errors);
    $finish;
  end
endmodule