Signal Integrity

Chapter 7.2 gave the receiver a voltage to decide about. Chapter 7.5 gave it an instant at which to decide. Neither guaranteed that by the time clock and data arrive together at that instant, anything usable is left.

That is this chapter. Signal integrity is not a separate discipline bolted onto a link — it is the question of how much of the transmitted signal survives to the sampling point, and whether what survives is enough to keep working when the part is hot, the supply is low, the neighbouring lanes are all switching, and the silicon is at a process corner nobody tested.

For a digital engineer this chapter has two jobs. Give you a correct mental model of what spends margin and how the effects combine. And — the part you will use most weeks — give you a reliable method for deciding whether a corruption you are looking at is a margin problem at all, because the three most common alternatives look similar and are fixed in completely different places.

1. The One-Sentence Model

Signal integrity is margin accounting. Start with an ideal eye, subtract everything the transmitter, channel, environment, and receiver take from it, and what remains is the operating margin.

Two consequences fall out of taking that literally.

A link that "works" is not a link that is fine. Working means margin was positive at the conditions you tested. Margin is what absorbs the conditions you did not — the hot corner, the low supply, the fast-process die, the workload that switches every neighbouring lane simultaneously. A design with zero margin works perfectly right up until it does not.

Everything is a subtraction from the same two budgets. There are only two: voltage margin and timing margin. Every mechanism in this chapter reduces one, the other, or both. Organising the subject that way turns a list of phenomena into a ledger you can actually reason about.

2. The Eye

Chapter 7.2 deferred this; here it earns its place.

Superimpose many received bit periods on one another, aligned to the clock. Ones stack on ones, zeros on zeros, and the transitions between them trace out crossing regions. What is left in the middle — the region no trace enters — is the eye, and it has two dimensions that mean two different things:

• Eye height — the vertical opening. Voltage margin: how much separation exists between the worst-case one and the worst-case zero at the sampling instant. Consumed by loss, noise, and receiver offset.
• Eye width — the horizontal opening. Timing margin: how much of the unit interval remains where the data is settled and unambiguous. Consumed by jitter, skew, and edge-rate degradation.

The sampling point must sit inside both, and this is where the two dimensions stop being independent. They interact: sampling slightly off-centre in time lands you where the eye is narrower vertically too, because the eye's edges slope. So timing error becomes voltage error, and vice versa. That coupling is why margin is quoted as a two-dimensional region rather than two separate numbers, and why Chapter 7.5's centre-of-UI clock phase matters so much — the centre is where both dimensions are largest simultaneously.

No eye-mask values appear in this chapter. Those are specification- and revision-specific, they belong to compliance rather than to intuition, and an invented one would be worse than none.

3. Channel Loss

A conductor attenuates, and — this is the part that matters — it attenuates high-frequency content more than low. A square edge is built from high-frequency content, so removing that content makes the edge slower and rounder.

Two distinct costs, one from each budget:

• Voltage. Less amplitude arrives, directly reducing eye height.
• Timing. A slower edge takes longer to cross the decision threshold, and the crossing region widens, reducing eye width.

Loss scales with length and with frequency, which is why both terms appear in the design targets. Published UCIe PHY design work targets die-to-die channels of less than about 3 mm in an advanced package and less than about 5 mm in an organic substrate package at the highest rates — and Chapter 6.4's reach figures reflect the same physics, with the advanced-package track specified for roughly 2 mm and the standard package for up to roughly 25 mm at correspondingly lower rates.

Reach and rate are one trade. A longer channel means more loss at a given frequency, so the rate must come down — which is exactly why UCIe's two package tracks pair short reach with high density and long reach with modest width.

4. Inter-Symbol Interference

The direct consequence of loss spreading energy in time.

If the channel's response to a single bit is stretched beyond one unit interval, then energy from this bit is still arriving when the next bit is sampled. The received level therefore depends on the recent history, not just on the current bit.

Two properties make ISI distinctive:

It is deterministic given the data. The same bit sequence produces the same distortion every time — ISI is not noise. That is what makes it correctable in principle, and it is why equalisation exists as a technique.

It is pattern-dependent, which is the diagnostic gift. Some sequences are much harder to receive than others, because they put the channel in the least favourable state before the bit that matters. A long run of one value followed by a transition, for instance, gives the channel time to settle fully one way and then demands an immediate full excursion.

Resist the urge to name a universal worst pattern. Which sequences are worst depends on the channel's actual response, and a pattern that is worst for one geometry can be benign for another. What transfers is the method: if error rate changes with data pattern, ISI and channel response are implicated, and a controlled pattern experiment (§16) will tell you more in an hour than a week of staring at counters.

Why UCIe suffers less than a long-reach link. Chapter 7.2 noted that UCIe's transmitter is described as a CMOS driver with programmable drive strength and no feed-forward equaliser — and that is a statement about ISI. Over a few millimetres, the response settles within the bit period well enough that equalisation is not worth its power and area. Lengthen the channel or raise the rate far enough and that stops being true, which is why equalisation appears in discussions of the highest UCIe rates.

5. Crosstalk

Conductors carrying fast edges couple into their neighbours, capacitively and inductively. The vocabulary is aggressor (the switching neighbour) and victim (the lane being corrupted), and the important structural facts are:

Coupling scales with proximity and with parallel run length. Both are maximised in exactly the geometry a wide die-to-die interface has: many conductors, closely spaced, running side by side for the whole channel.

The worst case is simultaneous switching. One neighbour switching is a small perturbation. All neighbours switching in the same direction at the same moment is a much larger one, and on a parallel bus that is not a rare coincidence — it is what happens whenever the data has low transition diversity.

Single-ended is more exposed. Chapter 7.2 explained why: a differential pair rejects noise common to both conductors, while a single-ended receiver compares against a reference and takes the full coupled disturbance as signal error.

On a wide single-ended parallel interface, a lane's margin depends on what its neighbours are doing. That is not a corner case; it is the normal operating condition, and it is why crosstalk analysis on a UCIe channel is done with realistic aggressor activity rather than one lane at a time.

And the design tension this creates, which §8 develops: crosstalk is the reason you cannot raise transmit swing indefinitely to buy margin. More swing on every lane is more aggression on every lane.

6. Jitter, and Why It Is Not Skew

Both consume timing margin. They are different quantities, they come from different places, and they are fixed differently — so conflating them sends investigations in the wrong direction.

Skew is a systematic relative offset. Clock and data arrive with a repeatable difference in timing, caused by unequal transmit paths, unequal package routes, unequal receive paths, and unequal PVT sensitivity. Chapter 7.5 §7 covered it. Because it is repeatable, it can be measured and compensated — that is what per-lane deskew does.

Jitter is time-varying uncertainty. The edge is not at the same place every period. Sources divide usefully into two families:

• Deterministic jitter — bounded, correlated with something identifiable: data pattern (ISI, seen as timing rather than voltage), duty-cycle distortion, periodic interference coupling in from elsewhere.
• Random jitter — unbounded in principle, from thermal and device noise, and characterised statistically rather than by a worst case.

That distinction has a practical consequence worth internalising: deterministic jitter has a worst case you can budget against; random jitter does not. With random jitter you are choosing a bit error rate, not eliminating errors. Published UCIe 3.0 PHY design work quotes a target raw BER of 1e-12 — which is a statement about probability, not about perfection, and that framing is the correct one for anything driven by random noise.

7. Supply Noise

The mechanism deserves its own section because on this kind of link it is unusually damaging.

Many lanes switching simultaneously draw a large current transient through the power delivery network. The network has finite impedance, so that transient produces supply droop and ground bounce. Two effects follow, and they compound:

• The transmitter's levels move, because the driver's output is referenced to a supply that just sagged. Less amplitude leaves the die.
• The receiver's reference moves, because the decision threshold is derived from local supplies. On a single-ended link that is a direct subtraction from margin — Chapter 7.2 §5's point that the reference is part of the signal path.
• The clocking moves too. Supply variation shifts circuit delays, which shifts the sampling instant. Supply noise therefore spends both budgets.

This is the same phenomenon as simultaneous switching output noise, and it is where Module 6 comes back. Chapter 6.1 established that signal routing and power delivery compete for the same package structure; Chapter 6.5 that the vertical direction makes it worse. The link's quality depends on a package resource that the link itself is consuming.

There is direct evidence of this being taken seriously as rates rise: the 64 GT/s PHY bump map defined in the UCIe 3.0 specification includes more power and ground bumps than the 32 Gb/s PHY. That is a specification-level acknowledgement that at higher rates, power delivery — not signal count — is the binding constraint on the bump map.

A margin problem can be a power problem. If errors track activity rather than data pattern — worse when more lanes are switching, regardless of what they carry — suspect the PDN before the channel.

8. Why Advanced Packaging Both Helps and Hurts

The nuance that separates understanding from slogans.

Where it helps:

• Much shorter routes, so much less loss and much less ISI.
• Finer geometry, allowing controlled impedance in a smaller cross-section.
• Lower per-lane rates for the same bandwidth, because density buys width — and lower rate is the single most effective way to buy margin.

Where it hurts:

• Neighbours are closer. Crosstalk coupling rises exactly as pitch falls.
• More lanes switch simultaneously. A x64 module has four times the simultaneous-switching current of a x16 one.
• Power and ground compete harder. The same fine pitch that packs signals in also constrains how many connections remain for the PDN — Chapter 6.6 §14's point that a pitch specification is about connection density, not data bandwidth.
• Less physical room for isolation. Ground shielding between lanes costs conductors, which are the scarce resource.

Advanced packaging converts one set of SI problems into another. It trades loss and ISI — the length-driven effects — for crosstalk and supply noise — the density-driven effects. Neither package class is "easier"; they are difficult in different directions, and an engineer who learned SI on long channels will be looking for the wrong failure on a short dense one.

9. Process, Voltage, Temperature

Every quantity in this chapter varies:

• Process — device speed, drive strength, receiver offset, and on-die resistance all vary die to die and within a die.
• Voltage — supply level moves with regulation, load, and the droop of §7. Lower supply generally means slower circuits and less swing.
• Temperature — conductor resistance rises with temperature, increasing loss; device behaviour shifts; and — Chapter 6.5's point — in a stacked or dense package, temperature is influenced by neighbouring dies.

The consequence is a one-line rule with a lot of engineering behind it:

A room-temperature pass at nominal supply on one part is a single point in a multidimensional space. SI signoff is about the corners, and silicon validation is about sweeping toward them deliberately rather than waiting for a customer to find them.

This is also why runtime recalibration matters. A link calibrated once at bring-up is optimised for the conditions at bring-up. UCIe 3.0's addition of runtime TX-side recalibration exists precisely because conditions move, and a setting that was optimal at 25 °C is not optimal at 95 °C.

10. The Margin Budget, Symbolically

A teaching model:

V_margin  =  V_swing  −  V_loss  −  V_ISI  −  V_crosstalk  −  V_supply  −  V_rx_offset
T_margin  =  T_UI     −  T_jitter  −  T_skew  −  T_setup  −  T_hold  −  T_dcd

The genuinely useful properties of the model:

• Every term is a subtraction. Nothing in the list adds margin except the first term of each line.
• The two lines are coupled (§2), so a term that looks like it belongs to one budget usually costs a little of the other.
• It tells you where to look. If timing margin is short, the second line names your suspects; adjusting swing will not help.

11. Making Margin Observable

The PHY cannot measure its eye from RTL. What it can do is count what the lack of margin produces, and structure those counts so they answer questions.

// Illustrative PHY telemetry RTL — not UCIe normative registers.
localparam int NUM_LANES = 64;
localparam int ERR_W     = 16;
 
logic [ERR_W-1:0] lane_error_q [NUM_LANES];   // saturating, per lane
logic             si_fault_seen_q;            // sticky, survives the event
 
always_ff @(posedge phy_clk or negedge rst_n) begin
  if (!rst_n) begin
    for (int l = 0; l < NUM_LANES; l++)
      lane_error_q[l] <= '0;
    si_fault_seen_q <= 1'b0;
  end else begin
    for (int l = 0; l < NUM_LANES; l++)
      if (lane_error_event[l] && !(&lane_error_q[l]))
        lane_error_q[l] <= lane_error_q[l] + 1'b1;    // saturating
 
    if (|lane_error_event)
      si_fault_seen_q <= 1'b1;                        // sticky: set, never self-clear
  end
end

Architecture. Marginality is invisible except through its consequences. Counting per lane rather than per link turns an aggregate into a spatial map, and §12 shows why that map is worth far more than the total.

State. One saturating counter per lane, plus a sticky fault bit. Note si_fault_seen_q has no self-clearing branch — clearing is an explicit software action or a broader reset, never automatic.

Cycle behaviour. Each lane's counter increments on that lane's error event, inhibited at all-ones. The sticky bit sets on any lane's event and stays set.

Contract. Firmware, telemetry, and diagnostics read these. Nothing in the functional datapath depends on them — Chapter 5.4's wide observability path, which must never become a functional dependency.

Failure. Two, both common. A wrapping counter makes a lane with 65,536 errors read identically to a healthy one, destroying exactly the evidence it was built to preserve. And a non-sticky fault indication misses transients entirely:

// WRONG as the only observability path — the event is gone before anyone reads.
assign si_fault = si_fault_event;

This combinational form is perfectly correct as a real-time signal driving hardware that reacts immediately. It is wrong as the only record, because software polling milliseconds later sees nothing and concludes the link is healthy. Real-time reaction and post-mortem evidence are different requirements needing different hardware, and a design that provides only the first cannot be debugged after the fact.

DV. Drive more events than a counter can hold and confirm saturation. Drive a single-cycle event and confirm the sticky bit is still readable an arbitrary time later. Confirm nothing in the datapath reads these.

12. Reading the Spatial Distribution

Per-lane counts are worth having because their shape is diagnostic. Four patterns, four different conclusions:

One lane far above the rest.

lane  0: 0    lane  1: 0    lane  2: 381   lane  3: 2
lane  4: 0    lane  5: 1    lane  6: 0     lane  7: 0

One physically marginal lane — its route, its bump, its driver, or its receiver. Repair or remap it (Chapter 7.3 §14) and the link is healthy again.

Two or three adjacent lanes elevated together. Crosstalk between neighbours, or a shared physical feature — a via region, a route congestion point, a package layer transition — affecting a contiguous group.

All lanes elevated roughly equally. Something shared: supply noise, the clock path, temperature, or an operating point that is simply too aggressive for the channel. Individual lanes are not the problem, so lane repair will not help.

All lanes zero but transfers still failing. Not a physical problem at all. Go to Chapter 7.3 — this is mapping, ordering, or configuration.

The total error count tells you the link is unhealthy. The distribution tells you what to do about it. Instrument per lane, or you will spend the difference in debug time.

13. Count Is Not Rate

A count without a window is not a health metric. One hundred errors in a second and one hundred errors in a year describe completely different links, and a bare counter cannot distinguish them.

// Illustrative PHY telemetry RTL — not UCIe normative registers.
// Error RATE, measured as a count within a fixed observation window. The
// threshold is precomputed for the window, so no division is needed.
localparam int WIN_W       = 24;
localparam int ERR_THRESH  = 16;    // errors per window that count as "high"
 
logic [WIN_W-1:0] window_q;
logic [ERR_W-1:0] window_errors_q;
logic             error_rate_high_q;
 
always_ff @(posedge phy_clk or negedge rst_n) begin
  if (!rst_n) begin
    window_q          <= '0;
    window_errors_q   <= '0;
    error_rate_high_q <= 1'b0;
  end else if (&window_q) begin
    // End of window: evaluate, then restart. Both counters clear together so a
    // count can never be attributed to the wrong window.
    error_rate_high_q <= (window_errors_q >= ERR_W'(ERR_THRESH));
    window_q          <= '0;
    window_errors_q   <= '0;
  end else begin
    window_q <= window_q + 1'b1;
    if (|lane_error_event && !(&window_errors_q))
      window_errors_q <= window_errors_q + 1'b1;
  end
end

Architecture. Policy decisions — recalibrate, disable a lane, report degradation — must be driven by a rate, not by a cumulative total that only ever grows.

State. A free-running window counter, a per-window error counter, and a latched verdict.

Cycle behaviour. The window counter increments every cycle. Errors accumulate within the window. On the cycle the window saturates, the comparison is latched and both counters clear together — resetting them at different times would attribute errors to the wrong window, a subtle off-by-one that shows up as a rate that reads high after a quiet period.

Contract. error_rate_high_q drives the recalibration policy in §14. The raw per-lane counters of §11 remain for diagnosis; these two structures answer different questions and both are needed.

Failure. Comparing a cumulative count against a threshold means the threshold is crossed once, early, and stays crossed forever. Every subsequent policy decision then fires on a condition that stopped being true long ago.

Why no division. Rate is errors per window, and if the window is fixed, comparing the count against a precomputed threshold is arithmetically identical and costs a comparator instead of a divider. Choosing the representation that avoids the expensive operation is ordinary good RTL practice and worth naming.

14. Policy Needs Hysteresis

Measurement is not policy. Turning a threshold directly into an action produces a system that fights itself.

// WRONG — every error triggers recovery.
assign recal_request = si_fault_event;

The recalibration storm. A transient noise burst causes an error. The error triggers recalibration. Recalibration interrupts traffic. Traffic resumes, and the next transient triggers it again. The link now spends more time recovering than carrying data, and — the cruel part — throughput collapses while every individual mechanism behaves exactly as designed. Nothing is broken; the control loop is unstable.

The fix is standard control practice: hysteresis and a holdoff.

// Illustrative PHY policy RTL — not UCIe normative behaviour.
localparam int ENTER_THRESH = 16;   // errors/window to declare degradation
localparam int EXIT_THRESH  =  4;   // errors/window to clear it  (EXIT < ENTER)
localparam int HOLDOFF_W    = 20;
 
logic                 degraded_q;
logic [HOLDOFF_W-1:0] holdoff_q;
logic                 recal_request;
 
always_ff @(posedge phy_clk or negedge rst_n) begin
  if (!rst_n) begin
    degraded_q <= 1'b0;
    holdoff_q  <= '0;
  end else begin
    if (window_end) begin
      // Two thresholds, so the state cannot chatter around a single boundary.
      if (!degraded_q && (window_errors_q >= ERR_W'(ENTER_THRESH)))
        degraded_q <= 1'b1;
      else if (degraded_q && (window_errors_q <= ERR_W'(EXIT_THRESH)))
        degraded_q <= 1'b0;
    end
 
    // Rate-limit the action itself, independently of the state.
    if (recal_request)          holdoff_q <= '1;
    else if (|holdoff_q)        holdoff_q <= holdoff_q - 1'b1;
  end
end
 
assign recal_request = degraded_q && link_operational && (holdoff_q == '0);

Architecture. A noisy measurement drives an expensive, disruptive action. Both the state and the action rate must be damped, and they are damped by different mechanisms.

State. A degradation flag with two thresholds, and a holdoff timer.

Cycle behaviour. At each window end, degraded_q sets if errors exceed the entry threshold and clears only if they fall below the lower exit threshold. recal_request fires only when degraded, the link is operational, and the holdoff has expired; issuing it reloads the holdoff.

Contract. The link FSM consumes recal_request. Note the link_operational term — requesting recalibration of a link that is already down is at best pointless and at worst interferes with the bring-up already in progress.

Failure — three distinct ones, which is why all three mechanisms exist. Without two thresholds, the state chatters on every window near the boundary. Without the holdoff, a genuinely degraded link recalibrates continuously and carries nothing. Without link_operational, recovery and recalibration fight each other during bring-up.

DV. Drive an error rate that hovers exactly at the entry threshold and confirm the state does not oscillate. Drive a sustained high rate and confirm recalibration is issued at the holdoff interval rather than continuously. Drive errors while the link is down and confirm no request is issued.

15. The Diagnostic Table

The most reusable thing in this chapter. Four failure classes that all present as "something is wrong with the data", each fixed somewhere completely different.

Four questions resolve almost every case, in this order because that is the order of increasing cost:

1. Are there bit errors at all? No errors with poor throughput is a bandwidth problem — Chapter 7.4 §13. Stop here.
2. Are the same bit positions wrong every time? Yes means mapping or configuration — Chapter 7.3. Stop here.
3. Does it change with temperature or supply? Yes means margin. This chapter.
4. Neither deterministic nor environment-sensitive? Suspect CDC — the class whose signature is precisely that the environmental sweeps report nothing (Chapter 7.5 §16).

Steps 1 and 2 are free and eliminate the two most common false leads. Do them first, every time.

16. Practical Experiments

Each of these takes an hour and eliminates a hypothesis. All are worth more than another day of reading counters.

Sweep temperature. Log temperature alongside per-lane error counts over time. If the error slope rises with temperature, that is strong evidence of insufficient margin, and it also tells you the margin is close — a link with generous margin does not respond to a 40 °C change.

Sweep supply. Margin the supply up and down within its legal range. Responsiveness to supply points at margin generally and at the PDN specifically (§7). Combined with the temperature result, this separates conductor-loss effects from circuit-speed effects.

Sweep rate. If the link supports multiple rates, drop one step. Errors that disappear at a lower rate are a margin problem almost by definition — the unit interval got longer and the same impairments now fit inside it. Errors that persist unchanged at a lower rate are almost certainly not SI.

Change the data pattern. Pattern dependence implicates ISI and channel response (§4). Compare a high-transition-density pattern against long runs. A large difference is a finding; no difference argues against ISI.

Change neighbour activity. Hold the lanes adjacent to a suspect lane quiet while exercising the victim, then switch the aggressors hard. A large change implicates crosstalk (§5). A change that tracks how many lanes switch, rather than which, implicates supply noise instead (§7) — that distinction is worth the extra experiment.

Review the retrain and recalibration history. A link that repeatedly recovers and degrades is describing marginal operation. A link that has never retrained and is corrupting data is describing something else entirely.

Compare against the SI signoff assumptions. Length, layer, neighbours, package class, rate, and temperature range. A channel outside the analysed envelope is not a mystery — it is an unanalysed channel, and no amount of debug substitutes for analysing it.

17. Who Proves What

And the boundary restated once, precisely, because it is the most-violated one in this subject:

SVA proves the digital reaction to signal-integrity status. It cannot prove the margin itself.

Assertions can prove that a fault event was captured and made sticky, that a recalibration request followed a sustained degraded state and not a single error, that traffic stopped when the architecture requires it, that counters saturate rather than wrap, and that policy respects hysteresis. They cannot prove eye height, eye width, jitter distribution, or crosstalk. Those require measurement — in a channel simulator before silicon, and on a bench after.

18. Common Misconceptions

"Signal integrity means whether the link works at room temperature." It means how much margin remains after everything has taken its share — margin being precisely what covers the conditions you did not test (§1, §9).

"Eye height and eye width are the same margin." Height is voltage, width is timing, they are consumed by different mechanisms, and they interact because the eye's edges slope (§2).

"Jitter and skew are interchangeable." Skew is systematic and correctable by deskew; jitter is time-varying and only reducible. Budgeting them together loses the distinction that decides the fix (§6).

"A short advanced-package channel removes SI concerns." It removes loss and ISI and adds crosstalk and simultaneous-switching noise. The problems convert rather than disappear (§8).

"Crosstalk is a PCB problem." It scales with proximity and parallel run length, both of which are maximised on a dense wide die-to-die interface (§5).

"One error count proves a lane is bad." A count without an observation window is not a rate, and one lane's count only means something relative to its neighbours' (§12, §13).

"Every error should trigger retraining." That is a recalibration storm: throughput collapses while every mechanism behaves as designed. Policy needs thresholds, hysteresis, and a holdoff (§14).

"If mapping is correct, remaining corruption must be SI." CDC produces bit errors too, and its signature — non-deterministic, not lane-local, insensitive to temperature and supply — is distinct from both (§15).

"SVA can prove margin." It proves the digital reaction to margin status. Margin needs measurement (§17).

"A link that passes at nominal PVT is production-ready." Nominal is one point in a multidimensional space, and margin is the whole subject (§9).

19. Understanding Check

20. Module 7 in One Page

Five chapters, one question answered five ways: what does it take to move a bit reliably between two dies?

The through-line: every one of those five is a resource that can run out, and the digital design's job is to know when it has. Swing runs out into noise. Conductors run out into repair. Width runs out into package geometry. Timing runs out into skew. And margin runs out into errors — which is why the last chapter is the one that teaches you to count rather than to assume.

21. What Comes Next

The PHY now has everything it needs to move bits reliably: levels, lanes, width, a timing reference, and a way to know whether margin remains. Every one of those, though, has been described in its operating state. Chapter 7.2's calibration codes had to be arrived at. Chapter 7.3's lane map had to be built and agreed with a peer. Chapter 7.4's active width had to be negotiated. Chapter 7.5's clocks had to become stable and be qualified.

None of that happens spontaneously. Before a single bit crosses, every state machine, lane map, clock-domain boundary, and calibration engine on both dies must begin from a known state — and establishing that, across multiple clock domains and multiple layers without creating metastability, partial initialisation, or lost state, is a harder problem than it sounds:

• 8.1 — UCIe Reset — reset as a distributed protocol: asynchronous assert and synchronous deassert, per-domain synchronisers, what must and must not be reset, reset-domain crossings, and why reset release is not link readiness.

Browse the full path on the UCIe tutorials index.