Electrical Signalling

Chapter 7.1 established what the PHY owns and drew a firm line: the Adapter gets a link it can trust, and the machinery that makes it trustworthy stays below. It also treated the electrical layer as a black box that either works or does not.

Open the box. Underneath every clean phy_operational there is a transmitter pushing charge onto a conductor, a package route that attenuates and delays and couples, and a receiver deciding — at one specific instant — whether what arrived counts as a one. Nothing in that sequence is Boolean. The entire electrical PHY exists to make an analogue process produce a digital answer reliably enough that everything above it can stop thinking about voltages.

This chapter gives a digital engineer correct physical intuition for that process, and — just as importantly — a precise account of which parts are your problem and which are not. It is not an analogue design course. It is the chapter that stops you from misdiagnosing an analogue problem as an RTL bug, and an RTL bug as an analogue problem.

1. The One-Sentence Model

Digital logic thinks in 0 and 1. The channel only knows voltages, currents, impedance, noise, delay, and time. The PHY exists to make those analogue quantities cross a threshold back into a digital bit, reliably, at a known instant.

Every section below is an elaboration of one word in that sentence. Voltage is swing and common mode. Impedance is termination. Delay and time are why a forwarded clock exists. Reliably is margin. At a known instant is sampling.

2. A Bit Is Not a Boolean on the Wire

Start with the smallest possible thing. In RTL:

logic tx_bit;
assign tx_bit = 1'b1;

That statement is complete inside the die. It is a name for a node that will be at a supply rail, and any logic reading it gets a 1.

The moment that value has to leave the die, it stops being a value and becomes an event. The transmitter drives the conductor toward some voltage. Charge moves. The conductor has resistance, capacitance, and inductance, so the voltage does not arrive instantly or in the same shape it left. Meanwhile the neighbouring conductors are doing the same thing and coupling into it, the supply feeding the driver is sagging slightly because a lot of drivers switched at once, and the far end is deciding what it sees.

At the receiver, a completely different question is being asked. Not "what is the value?" but:

Did the channel deliver enough voltage, in the right direction, at the instant I sampled?

The gap between the RTL statement and that question is the whole electrical PHY problem. Everything in this chapter lives in that gap.

3. What UCIe Actually Signals With

This is an accuracy gate, and the honest answer is genuinely surprising if your instincts come from PCIe or any long-reach SerDes.

UCIe's mainband data lanes are single-ended. Each module provides N single-ended, unidirectional, full-duplex data lanes — 16 for the standard package, 64 for the advanced package — plus one single-ended Valid lane, one Track lane, a differential forwarded clock per direction, and four lanes for sideband signalling. The interface uses clock forwarding with single-ended, low-voltage, DDR signalling specifically to improve power efficiency.

Take that apart, because each choice has a reason:

Single-ended, not differential. A differential pair uses two conductors per bit. On a link whose entire premise is that connections are scarce and precious — Module 6's argument, in one sentence — halving the bits per conductor is an enormous cost. Long-reach SerDes pays it because a differential pair rejects common-mode noise and survives a metre of PCB. UCIe does not need to survive a metre; it needs to survive a few millimetres of package routing. Over that distance, single-ended is viable, and the conductors saved go straight into width.

Low voltage. Energy per transition scales with the voltage being swung. On a link with dozens of lanes switching at gigahertz rates, that term dominates, and it is why UCIe quotes energy figures well below a picojoule per bit for the advanced package.

DDR — double data rate. Data is transferred on both clock edges, so the signalling rate is twice the clock frequency. That halves the clock frequency needed for a given data rate, which matters enormously for the power and the distribution problem.

Forwarded clock, and it is differential. Rather than recovering timing from the data stream — which is what a long-reach SerDes does with a CDR, at considerable power and complexity — the transmitter sends its clock alongside the data. The receiver samples with a clock that experienced substantially the same conditions as the data. That is why UCIe can afford a simple receiver, and it is why the one signal that genuinely needs noise immunity — the timing reference — gets the differential treatment the data lanes do not. Chapter 7.5 owns this properly.

The whole electrical design point follows from the channel being short. Short channel → single-ended is enough → more conductors per bit of area → go wide and slow → low swing, simple circuits, forwarded clock, low energy per bit. Change the channel length assumption and every one of those choices flips, which is exactly what distinguishes the standard-package and advanced-package tracks.

4. Voltage Swing

Swing is how far the transmitter moves the conductor between a 0 and a 1. It is the raw material of the receiver's decision: everything the channel and the noise environment take away is subtracted from it, and what remains at the sampling instant is the voltage margin.

The naive conclusion is "more swing is better". It is a trade, in both directions:

The third row on each side is the one people miss, and it is why the trade is not monotonic. A lane's swing is another lane's noise. Raising swing to improve one lane's margin raises the crosstalk that lane injects into its neighbours, and on a dense parallel interface the neighbours are very close. The same current that improves the signal makes the supply that produces the signal noisier. Past some point, raising swing makes the aggregate margin worse.

Which is why the transmitter is configurable rather than fixed. UCIe PHY material describes a CMOS driver with programmable drive strength and no feed-forward equaliser — the equaliser being unnecessary precisely because the channel is short. Programmability exists so that the driver can be matched to the channel it actually got, rather than to the worst channel anyone might build.

5. Common Mode, for Digital Engineers

Two different questions about the same waveform:

• What is the signal? The difference between the high level and the low level — the swing, and which side of the threshold a given bit is on.
• Where is the signal sitting? The average voltage the whole waveform is centred around. That is the common mode.

Why a digital engineer should care: a receiver is a circuit made of transistors, and those transistors have an input range within which they behave the way the designer intended — right gain, right speed, right offset. Move the whole waveform outside that region and the receiver degrades or stops working even if the swing is unchanged. The information is still there; the circuit can no longer extract it.

Common mode drifts for ordinary reasons: supply variation, process differences between the two dies, temperature, and any DC offset between the two ends' references. On a single-ended link this matters more than on a differential one, because a differential receiver looks at the difference between two conductors and rejects a shift common to both — that rejection is most of why differential exists. A single-ended receiver compares against a reference, so anything that shifts the signal relative to that reference eats directly into margin.

On a single-ended link, the receiver's reference is part of the signal path. Anything that moves the signal relative to that reference — supply noise, offset between dies, temperature drift — consumes margin exactly as if the swing had shrunk.

This is one of the main things calibration (§8) exists to handle, and one of the main reasons a link that is fine at room temperature can be marginal hot.

6. Termination

A fast edge travelling along a conductor is a wave, and waves reflect at discontinuities. A conductor has a characteristic impedance set by its geometry and materials, and when the wave reaches an end that does not match that impedance, some of its energy comes back.

You do not need the transmission-line mathematics. You need the consequence:

• Overshoot and undershoot — the reflected energy adds to or subtracts from what is already there, so the level goes past where it should and rings.
• Multiple threshold crossings — a ringing edge can cross the receiver's threshold more than once, so one transition can look like several.
• Reduced margin — reflections from previous bits are still bouncing around when the current bit arrives, subtracting from its usable amplitude and timing window.

Termination is the fix: place an impedance at the end of the conductor that matches it, so the wave is absorbed instead of reflected.

Termination makes the channel look electrically predictable to a fast edge.

Two nuances that keep the picture honest.

Termination is not free. A resistive termination to a supply draws static current whenever the line is driven against it. On a link with many lanes, that is real power, which is precisely the resource UCIe's low-swing, short-channel design point is trying to conserve. This is why termination is a configurable choice rather than a universal one — UCIe PHY material describes the transmitter as a CMOS driver without source termination, and receiver-side termination as something that depends on the channel and the operating mode.

Shorter channels need it less. Reflection matters when the round-trip time on the conductor is comparable to the bit period. Make the conductor short enough and the reflections settle within the bit, so an unterminated line can be perfectly adequate — and cheaper in power. That is another consequence of the short-channel design point, and another place where the standard-package and advanced-package envelopes genuinely differ.

7. What RTL Does and Does Not Control

The critical distinction of this chapter, stated before any more code appears.

RTL does not implement termination. There is no resistor in your Verilog. The termination is a physical circuit — transistors, resistors, and a control code that sets its effective impedance. What the digital PHY holds is the selection: which mode, which code, whether it is engaged.

// Illustrative PHY control — not UCIe normative signal naming.
// The termination itself is an analogue circuit. This is the digital state
// that selects among the modes that circuit provides.
typedef enum logic [1:0] {
  TERM_OFF    = 2'd0,   // unterminated — lowest power, shortest channels
  TERM_MODE_A = 2'd1,   // one of the terminated options the AFE offers
  TERM_MODE_B = 2'd2    // a second option, e.g. a different effective value
} term_mode_t;
 
typedef struct packed {
  term_mode_t  term_mode;
  logic [3:0]  drive_strength;   // TX driver strength code
  logic [5:0]  term_cal_code;    // calibration result applied to the AFE
} elec_cfg_t;

Architecture. The analogue front end offers a set of configurable behaviours. Something has to choose among them, hold the choice stably, and present it to the AFE. That something is digital, and it is the PHY's.

State. An enumerated mode, a drive-strength code, and a calibration code. Note what is absent: no ohms, no volts, no impedance. Those are properties of the circuit the codes select, not of the codes. A field called term_ohms would be a lie — the RTL has no idea what impedance a code produces.

Cycle behaviour. Written during configuration, then held. These are not per-cycle datapath signals; they are static control that the analogue circuit takes time to respond to.

Contract. The AFE consumes them. The training engine chooses them. Nothing above the PHY sees them at all.

Failure. A design that treats these as freely writable — allowing a change while the link is running — perturbs the analogue circuit under live traffic. The result is a burst of errors with no digital cause anywhere, which is close to undiagnosable from RTL waveforms alone.

DV. Verify that every code the RTL can emit is one the AFE actually supports, that unsupported encodings are rejected rather than passed through, and — §9 — that the configuration cannot change while it is being relied upon.

8. Calibration

The AFE's behaviour depends on process, voltage, and temperature. A termination code that produces the intended impedance on a typical die at 25 °C produces something else on a fast-corner die at 100 °C. A receiver's decision point has an inherent offset that varies device to device. Timing relationships between a forwarded clock and its data drift.

None of that can be fixed at design time, because the variation is per-part and per-moment. So the PHY measures and corrects at run time — that is calibration. Generic examples, kept generic deliberately:

• Termination calibration — determine the code that produces the intended impedance for this die at this condition.
• Receiver offset calibration — measure and cancel the receiver's inherent decision offset.
• Timing calibration — position the sampling instant where the margin is best.

UCIe 3.0 makes this more explicitly a runtime concern: the Consortium describes runtime TX-side recalibration among its additions, alongside doubling the maximum rate to 48 and 64 GT/s. That direction is not surprising — the faster the signalling, the smaller the margins, and the less tolerable it is to calibrate once at bring-up and hope conditions never move.

What the digital PHY sees of all this is a handshake, and nothing more:

// Illustrative PHY control — not UCIe normative signal naming.
logic cal_start;   // digital → AFE: begin calibration
logic cal_busy;    // AFE → digital: in progress
logic cal_done;    // AFE → digital: finished, result valid
logic cal_fail;    // AFE → digital: could not converge

The digital side does not know what is being measured, how, or what "good" means. It knows when to start, when it finished, and whether it worked. That is the correct amount of knowledge, and it is the same abstraction discipline Chapter 7.1 §16 argued for at the Adapter boundary, applied one level down.

9. Electrical Readiness Is State

Configuration existing is not the same as the circuit being ready, and conflating them is this chapter's counterpart to 7.1's phy_ready = rst_n:

// WRONG — configuration present does not mean the analogue circuit is ready.
assign electrical_ready = cfg_valid;

cfg_valid says a mode has been selected. It says nothing about whether the termination code has been calibrated for this die at this temperature, whether the receiver's offset has been cancelled, or whether calibration attempted and failed.

// Illustrative — electrical readiness is a conjunction of prerequisites.
assign electrical_ready = cfg_valid && cal_done && !cal_fail;

A small controller makes the sequencing explicit. Note that this is deliberately not another copy of 7.1's link FSM — it covers electrical readiness only, and its elec_ready output is one of the inputs that chapter's PHY_TRAIN state depends on:

// Illustrative PHY RTL — not UCIe normative signal naming.
typedef enum logic [1:0] {
  ELEC_RESET,      // codes at defaults, AFE not trusted
  ELEC_CONFIGURE,  // mode selected, snapshot taken, waiting to calibrate
  ELEC_CALIBRATE,  // calibration running
  ELEC_READY       // configured and calibrated; the link may train
} elec_state_t;
 
elec_state_t elec_state_q, elec_state_d;
elec_cfg_t   active_elec_cfg_q;
logic        elec_fault_q;
 
always_comb begin
  elec_state_d = elec_state_q;                    // explicit default: hold
  unique case (elec_state_q)
    ELEC_RESET     : if (cfg_valid && cfg_legal) elec_state_d = ELEC_CONFIGURE;
    ELEC_CONFIGURE : elec_state_d = ELEC_CALIBRATE;
    ELEC_CALIBRATE : if      (cal_fail) elec_state_d = ELEC_RESET;
                     else if (cal_done) elec_state_d = ELEC_READY;
    ELEC_READY     : if (recal_request || elec_fault_q) elec_state_d = ELEC_CALIBRATE;
    default        : elec_state_d = ELEC_RESET;
  endcase
end
 
always_ff @(posedge phy_clk or negedge rst_n) begin
  if (!rst_n) begin
    elec_state_q      <= ELEC_RESET;
    active_elec_cfg_q <= '0;
    elec_fault_q      <= 1'b0;
  end else begin
    elec_state_q <= elec_state_d;
 
    // Snapshot on entry to CONFIGURE — see §10.
    if (elec_state_q == ELEC_RESET && elec_state_d == ELEC_CONFIGURE)
      active_elec_cfg_q <= requested_elec_cfg;
 
    if      (cal_fail)                      elec_fault_q <= 1'b1;
    else if (elec_state_q == ELEC_CONFIGURE) elec_fault_q <= 1'b0;
  end
end
 
assign cal_start      = (elec_state_q == ELEC_CONFIGURE);
assign electrical_ready = (elec_state_q == ELEC_READY);

Architecture. Analogue circuits need to be told what to be, then given time to become it. Encoding that as states makes "ready" a conclusion with prerequisites rather than a wire someone assigned.

State. Four-state register, a configuration snapshot, and a sticky fault bit. ELEC_READY has an exit back to ELEC_CALIBRATE, which is what makes runtime recalibration expressible.

Cycle behaviour. One transition per clock. cal_start is a level asserted for the duration of ELEC_CONFIGURE, which gives the AFE a clean, unambiguous request rather than a pulse it might miss. The snapshot is written on exactly the cycle of the RESET → CONFIGURE transition.

Contract. The link-level FSM from 7.1 must gate PHY_TRAIN on electrical_ready. Training a link whose receiver offset has not been cancelled produces a training failure that looks like a channel problem.

Failure. Without the cal_fail path, a calibration that never converges leaves the machine waiting forever, and bring-up hangs with no indication of which stage stalled. Without the sticky elec_fault_q, a transient failure is invisible after the fact, so post-mortem debug has nothing to work with.

DV. Force cal_fail and confirm the machine leaves ELEC_CALIBRATE, records the fault, and never asserts electrical_ready. Force cal_done and cal_fail together — a physically odd but reachable condition — and confirm failure wins.

10. Freeze the Electrical Configuration

Chapter 7.1 §17 established the configuration-snapshot principle for the link FSM. It applies with more force here, because analogue circuits respond to their control codes over time, not instantly.

// Illustrative — electrical configuration is snapshotted, not read live.
if (elec_state_q == ELEC_RESET && elec_state_d == ELEC_CONFIGURE)
  active_elec_cfg_q <= requested_elec_cfg;

Why the analogue case is worse. When a digital configuration changes mid-sequence, different stages use different values — bad, but at least each stage sees some consistent value. When a termination or drive-strength code changes while the circuit is settling, the circuit passes through intermediate states that correspond to no valid configuration at all, and calibration may converge on a measurement taken during that transient. The resulting code is then wrong in a way that is stable, plausible, and invisible.

The assertion has to cover the whole span, not one edge:

// Illustrative — the active electrical configuration is stable for the whole
// of calibration, not merely on the cycle after it starts.
property p_elec_cfg_stable_while_calibrating;
  @(posedge phy_clk) disable iff (!rst_n)
    (elec_state_q == ELEC_CALIBRATE) |=> $stable(active_elec_cfg_q);
endproperty
 
a_elec_cfg_stable_while_calibrating :
  assert property (p_elec_cfg_stable_while_calibrating)
  else $error("Electrical configuration changed during calibration.");

Read the property carefully, because the shape is the lesson. It is evaluated on every cycle the machine is in ELEC_CALIBRATE, and each evaluation requires stability on the following cycle. Chained over a multi-cycle calibration, that is stability throughout. A property written as $rose(calibrating) |=> $stable(...) would check only the first cycle and pass while the configuration changed on the tenth — an assertion that looks correct, always passes, and protects nothing.

DV. Then attack it: drive requested_elec_cfg to a new value at several different points inside calibration and confirm the assertion holds and the outcome is unchanged. A snapshot nobody attacked is a snapshot nobody verified.

11. What the Channel Does to the Bit

Three effects, in the order they matter for a short package link.

Loss. A conductor attenuates, and it attenuates high-frequency content more than low. A square edge is made of high-frequency content, so what arrives is not square — it is slower, rounder, smaller. The immediate consequences: less amplitude at the sampling instant, and a transition spread over more time.

Inter-symbol interference. Because the response is spread in time, energy from this bit is still present when the next bit is being sampled. The received level therefore depends on the recent history, so some bit patterns are harder to receive than others. This is why link failures can be pattern-dependent — a diagnostic signature worth remembering, and one Chapter 7.6 develops properly.

Coupled noise. Neighbouring conductors carry their own fast edges and couple into each other. On a dense parallel interface, "neighbouring" means very close, and a lane's worst case is generally when everything around it switches simultaneously in the unhelpful direction.

Two more effects belong to the environment rather than the conductor. Supply noise moves the levels the transmitter drives and the reference the receiver compares against — which, per §5, is doubly damaging on a single-ended link. And jitter moves the sampling instant relative to the data, spending timing margin directly.

12. What Electrical Marginality Looks Like Digitally

This is the section to keep, because it is the one that changes what you do on a Tuesday afternoon.

Bad electrical margin does not announce itself. It produces bit errors, and bit errors look like bit errors. What distinguishes them is their pattern in time and environment:

The two rows in bold on the right are the ones that end an investigation quickly. Deterministic, position-fixed corruption that ignores temperature, voltage, and rate is not an analogue problem — it is arithmetic, and Chapter 7.1 §14 and Chapter 7.3 tell you where to look. Conversely, an error rate that responds to temperature or supply is not going to be fixed by reading RTL.

The row worth dwelling on is retraining. A link that recovers after a retrain and then degrades again is describing itself: calibration produced a working setting, conditions moved, and the setting stopped being right. That is the classic signature of insufficient margin — and precisely the problem runtime recalibration exists to address.

13. Counting Errors Properly

To ask those questions you need data, which means the PHY has to count. Two RTL lessons hide in something that looks trivial.

// Illustrative PHY RTL — not a UCIe normative register.
localparam int ERR_W = 16;
 
logic [ERR_W-1:0] electrical_error_count_q;   // saturating
logic [ERR_W-1:0] errors_since_retrain_q;     // clears on retrain
 
always_ff @(posedge phy_clk or negedge rst_n) begin
  if (!rst_n) begin
    electrical_error_count_q <= '0;
    errors_since_retrain_q   <= '0;
  end else begin
    // Saturate. A diagnostic counter that wraps destroys the evidence it exists
    // to preserve — 65,536 errors and 0 errors must not look identical.
    if (physical_error_event && !(&electrical_error_count_q))
      electrical_error_count_q <= electrical_error_count_q + 1'b1;
 
    // A second counter with a different lifetime answers a different question:
    // "is it degrading again since we last fixed it?"
    if (retrain_done)
      errors_since_retrain_q <= '0;
    else if (physical_error_event && !(&errors_since_retrain_q))
      errors_since_retrain_q <= errors_since_retrain_q + 1'b1;
  end
end

Architecture. Electrical marginality is a rate, not an event. A single error is meaningless; a rate that changes with temperature is a diagnosis. Hardware has to accumulate what software will later correlate.

State. Two counters with deliberately different lifetimes. The lifetime is the design decision — a counter that never clears answers "has this part ever been unhealthy?", and one that clears on retrain answers "is it degrading again since we last fixed it?". One counter cannot answer both.

Cycle behaviour. Increment on an error event, inhibited at maximum. &counter is the all-ones test, so the increment stops at the top rather than rolling over.

Contract. Firmware and telemetry read these. Nothing in the functional datapath depends on them, which is deliberate — this is Chapter 5.4's wide observability path, and it must never become a functional dependency.

Failure. With a wrapping counter, a part that logged 65,536 errors reads exactly the same as a healthy one. The information was collected and then destroyed by the counter itself. This is a real and common bug, and it is invisible in every test short enough not to wrap.

DV. Drive more error events than the counter can hold and check it saturates rather than wraps. Check the clear-on-retrain counter clears exactly on retrain and not on unrelated state changes.

14. Electrical Prerequisites in the Link FSM

Chapter 7.1 asserted that PHY_ACTIVE is reachable only through training. That property now gets a specifically electrical strengthening:

// Illustrative — the link may not be active without electrical readiness.
property p_active_requires_electrical_ready;
  @(posedge phy_clk) disable iff (!rst_n)
    (phy_state_q == PHY_ACTIVE) |-> electrical_ready_q;
endproperty
 
a_active_requires_electrical_ready :
  assert property (p_active_requires_electrical_ready)
  else $error("PHY_ACTIVE with electrical_ready deasserted.");

Note the difference from 7.1's version, which checked the transition into ACTIVE. This one holds for every cycle the link is active, which catches something the transition check cannot: electrical readiness dropping away underneath a running link. If calibration is invalidated — a fault, a temperature excursion triggering recalibration — while the FSM is still reporting ACTIVE, the Adapter is being told it may send over a link whose analogue configuration is no longer trusted.

The bug this catches is a missing edge in the link FSM: someone remembered to require electrical readiness before activating and forgot to leave ACTIVE when it goes away. That omission is invisible until a part in the field gets hot.

15. Who Proves What

Make this boundary explicit, because work falls into the gap between the two teams and nobody notices.

Neither side can prove the other's column, and a link needs both columns true. An analogue signoff on a configuration the RTL never selects is worthless. An RTL testbench proving perfect sequencing over an ideal channel proves nothing about margin.

The specific corollary, restating 7.1 §15 in electrical terms: SVA cannot prove electrical margin. It can prove that calibration completed before traffic started. It cannot prove the calibration produced a good answer. That requires measurement, on real silicon or in analogue simulation.

16. Debug Checklist — Suspected Electrical Failure

Cheapest and most decisive first:

1. Does the digital configuration match the package mode? A link configured for one electrical envelope on a channel built for another fails electrically for an entirely digital reason.
2. Did calibration complete, and did it report success? Check cal_done and cal_fail, not just that the link left the calibration state.
3. Is the electrical configuration stable? If something is rewriting drive strength or termination during operation, everything below is noise.
4. Is the failure lane-specific? One lane points at that lane's channel or its receiver. All lanes point at something shared — clock, supply, reference, or configuration.
5. Deterministic or intermittent? The single most informative question, per §12.
6. Does temperature change it? If yes, it is margin.
7. Does supply voltage change it? If yes, it is margin — and check the PDN, because Module 6 spent three chapters on why that is a package-level problem.
8. Does the data pattern change it? Pattern dependence points at ISI and channel response.
9. Are the digital lane maps correct? Verify this before commissioning any signal-integrity work. It costs minutes and eliminates the most common false lead.
10. Does the analogue signoff actually cover this channel? Length, layer, neighbours, and package class. A channel outside the analysed envelope is not a mystery; it is an unanalysed channel.

Steps 1 to 3 and step 9 are digital and cheap. Steps 5 to 8 are a few experiments. Only then is a full signal-integrity investigation justified — and by then it has a specific question to answer rather than a general one.

17. Common Misconceptions

"A 1 is a 1 all the way across the wire." On the wire there is no 1 — there is a voltage that arrived in some shape at some time, and a receiver deciding about it (§2).

"Higher voltage swing is always better." More swing means more energy, more switching current, more supply noise, and more crosstalk into neighbours. Past a point the aggregate margin gets worse (§4).

"Termination is analogue housekeeping." It determines whether fast edges reflect, which determines whether the receiver sees clean levels. It is also a power decision, which is why it is configurable rather than always on (§6).

"If the RTL is correct, the bit will arrive." The RTL selects a configuration. Whether the resulting electrical condition survives the channel is a separate question that RTL cannot answer (§15).

"Calibration is optional if the link trains." Training over an uncalibrated AFE may succeed at one condition and fail at another. Calibration is what makes the setting right for this die at this condition (§8, §9).

"A clean link at room temperature proves enough margin." It proves the link works at one point in the space. Margin is what remains for the points you did not test (§11, §12).

"Every intermittent error is a CDC bug." Intermittent, environment-sensitive errors on a physical link are far more often margin. CDC bugs do not usually track temperature (§12).

"Every deterministic error is a signal-integrity problem." The opposite: deterministic, position-fixed corruption is the signature of a digital configuration or mapping error (§12).

"SVA can prove electrical margin." It proves sequencing, gating, and stability. Margin needs measurement or analogue simulation (§15).

"On-die termination means RTL implements a resistor." RTL selects a mode and applies a calibration code. The circuit terminates (§7).

18. Understanding Check

19. Summary and What Comes Next

Digital logic thinks in ones and zeros; the channel knows only voltages, impedance, noise, and time. The PHY's electrical job is to make an analogue process yield a digital answer with margin to spare.

UCIe's electrical design point follows from one fact — the channel is short. That permits single-ended mainband lanes rather than differential pairs, which frees conductors for width: 16 data lanes per standard-package module, 64 per advanced-package module, plus Valid, Track, a differential forwarded clock per direction, and four sideband lanes. Short channels also permit low swing, DDR signalling, and a simple driver with programmable strength and no feed-forward equaliser. Go wide and slow, and every circuit gets easier.

The physical ideas to carry: swing is a trade, because one lane's amplitude is its neighbours' crosstalk and its own supply noise. Common mode matters more when single-ended, because the receiver's reference is part of the signal path. Termination makes the channel look predictable to a fast edge, and costs power, which is why it is configurable. And the channel spends what the transmitter provides — loss, ISI, coupling, supply noise, and jitter all subtract from the voltage and timing margin that remain at the sampling instant.

The digital bridge: RTL selects, the circuit terminates. Configuration is codes, not ohms. Calibration is a handshake — start, busy, done, fail — and nothing more. Electrical readiness is a state with prerequisites, gating training, and it must be withdrawn when it stops being true, not merely required before it starts. Configuration must be snapshotted and stable for the whole of calibration, with an assertion that checks every cycle rather than only the first. Diagnostic counters must saturate, because a wrapping counter destroys the evidence it exists to preserve.

And above all, the two questions: does it change with temperature or supply, and is it the same bits every time. Environment-sensitive and intermittent means margin — stop reading RTL. Deterministic and position-fixed means configuration — stop measuring the channel.

One electrical path carries one slice of a transfer. Useful bandwidth comes from organising many such paths in parallel, and that organisation is not merely "more wires" — it is a structure with identity, state, and mapping:

• 7.3 — Lane Concepts — what exactly one lane is, how lanes group into modules, and the mapping state that keeps logical data ordering independent of which physical conductor carries it.

Browse the full path on the UCIe tutorials index.