The DRAM Cell (1T1C)

Chapter 2.1 described a storage element in isolation: charge on a node, a continuous quantity, no drive and no gain. Chapter 2.2 showed that the state decays, and 2.3 built the digital obligation that follows.

All three took something for granted. An isolated storage node is useless — there has to be a way to reach it, and reaching one specific node among billions is not a small requirement. So:

How can a single tiny stored charge be selected out of an array of billions, using the smallest possible amount of circuitry per cell?

The answer is the cell's complete anatomy: one access transistor, one storage capacitor, one control wire, one shared data wire. That is everything. There is no address decoder in the cell, no buffer, no amplifier, no output driver — because anything replicated per bit is paid a billion times, and Chapter 1.6 §2 established that the replicated term is what sets cost per bit.

This chapter is where the structure gets nailed down. And it has a second purpose that is easy to miss: by the end of it, the destructive read of 2.5 will already be obvious. The arrangement makes reading destructive before a single read has happened — the property is in the wiring, not in the operation.

1. The Complete Cell

Four elements. The discipline is in how few there are.

The storage capacitor holds the charge that represents the bit, exactly as Chapter 2.1 described. One of its terminals is the storage node — the part whose charge matters. Its other terminal connects to a fixed reference potential shared across the array, so the capacitor has something to hold its charge against.

The access transistor is a switch, and nothing more. Its two conducting terminals sit between the storage node and the shared data wire. Its gate is the control input: raise the gate and the switch conducts, connecting the node to the wire; lower it and the switch is off, leaving the node as isolated as Chapter 2.2 showed it can be — which is to say, nearly.

The wordline is the wire driving that gate. It answers when this cell participates.

The bitline is the shared data wire on the other side of the switch. It answers where the charge goes when the cell does participate.

Read the figure as two questions answered by two wires. The horizontal path is the data path: charge moving between the storage node and the bitline, in whichever direction the conditions dictate. The wordline is not on that path at all — it is a control input that decides whether the path exists. Getting this separation clear is what makes the rest of the module readable: a wordline never carries data, and a bitline never carries a command.

And note what is absent. No decoder, no latch, no buffer, no amplifier, no driver. A cell cannot decide whether it is being addressed, cannot remember that it was read, cannot amplify its own charge, and cannot refuse. Everything that decides, remembers, amplifies or refuses lives outside the cell and is shared — because that is the only way its cost per bit becomes acceptable (Chapter 1.6 §3).

2. "One Transistor, One Capacitor" Is a Cost Statement

The name 1T1C is usually treated as a description. It is better read as a budget, and the budget explains the whole design.

Every element in a cell is paid at every bit. A billion-cell array pays its transistor count a billion times, its capacitor area a billion times, its contacts a billion times. So the cell is not designed by asking "what would work well?" — it is designed by asking "what is the minimum that can work at all?"

Compare the answers across the tiers this curriculum has built:

The third row is a complete derivation of Module 2. Each thing the cell cannot do is a job that had to move outside it, and each of those jobs is a mechanism in the DDR standard. The absence of gain means sensing must be external. The absence of drive means restoration must be external. The absence of any self-maintenance means refresh must be external and scheduled (2.3).

Which is why a 1T1C cell cannot be made "better" in isolation. Adding anything to it — a buffer, a second transistor, more capacitance — improves its behaviour and damages the only property that justifies its existence. The engineering work goes into making the minimum manufacturable: this is why real DRAM capacitors are elaborate three-dimensional structures, which is an attempt to keep capacitance up while the cell's footprint goes down. That is not adding to the budget; it is spending the same budget more cleverly.

3. What "Selected" Means

A precise account, because the word does a lot of work later.

A cell is selected when its wordline is asserted, which turns its access transistor on, which connects its storage node to its bitline. Nothing else about the cell changes. The cell does not know it was selected, does not signal that it was, and cannot decline.

Unselected means the wordline is low and the access transistor is off. The storage node is left holding its charge, subject only to the slow leakage of Chapter 2.2. An unselected cell is not "disabled" or "idle" in any active sense — it is simply not connected to anything, which is the whole of its data-retention strategy.

Three consequences that matter more than they look.

Selection is a physical connection, not a message. There is no request, no acknowledgement, no handshake. This is why the digital contracts in this module are enforced outside the array: the cells cannot participate in a protocol.

Selection is not per cell. One wordline runs across many cells, so asserting it selects every cell along it, simultaneously. This is not an optimisation — it is what one shared control wire per row means. A per-cell select wire would be a second wire paid at every bit, and §2 says that budget does not exist.

Therefore the smallest thing that can be selected is a whole row of cells. That single sentence is the origin of row-oriented behaviour in every DRAM device ever built, and of most of the DDR standard's structure. It is not a protocol convention that could have been chosen differently; it is what falls out of spending one control wire per row instead of one per cell.

4. The Bitline Is Shared, and That Is the Whole Problem

The wordline's sharing produces row-oriented selection. The bitline's sharing produces something more dramatic.

Many cells connect to one bitline. They must: a private data wire per cell is another per-bit cost, and it would also be pointless — the circuitry the wire leads to is itself shared, for the same budget reasons.

So a bitline is a long wire running past a great many cells, with each cell's access transistor tapping it. Two facts about that wire decide everything in the next chapter.

It is long, and it has many things attached. It spans many cells and carries each one's connection. A long wire with many attachments has substantial capacitance of its own — and this is the comparison that matters:

The bitline's capacitance is much larger than the storage capacitance of any single cell attached to it.

That is not a fabricated ratio; it is a structural statement about a long shared wire versus a deliberately minimised cell, and it holds by construction in any array built this way. The actual ratio is a real, product-specific design quantity, and this chapter quotes none.

It is the only route in or out. A cell's charge cannot reach anything except through its bitline, and nothing can reach the cell except along the same path.

Now put the two facts together with Chapter 2.1 §4's absences. The cell has no drive, so when it is connected to the bitline it cannot force the bitline to any particular condition — it can only let its charge and the bitline's charge reach a shared condition. And the bitline's capacitance dwarfs the cell's. So when the switch closes:

• the cell's small charge redistributes across a much larger capacitance;
• the bitline's condition changes by a small amount, in a direction that reveals what the cell held;
• and the cell's own condition is no longer what it was, because its charge left.

All three of those follow from the wiring alone, before anyone has issued a read. The small signal that Chapter 2.1 §3 described in terms of Q = C·V is here explained structurally: the signal is small because a tiny charge is being shared with a large wire. And the destructive read of 2.5 is already visible: it is not something a read does, it is what connecting a driveless cell to a much larger capacitance is.

One cell per column participates. That is what one asserted wordline achieves: across the whole row, each column contributes exactly one cell's charge to its own bitline. The unselected cells in the same column are connected to nothing and contribute nothing, which is exactly why the arrangement works at all.

And the sensing is at the far end, shared. The small shift on each bitline is resolved by circuitry serving that whole column, for every row. That is the amortisation of Chapter 1.3 §3 and Chapter 1.6 §3, and Module 3 builds the circuit.

5. Why the Cell Mechanism Is Analog Even Though the System Is Digital

A short section, but it is the abstraction boundary that keeps engineers honest, and it is the reason this module refuses to write RTL for the cell.

Everything in §1 to §4 is a continuous process. A charge redistributes according to the capacitances involved. A switch conducts more or less depending on its gate voltage. A bitline's condition shifts by an amount that depends on the cell's charge, the bitline's capacitance, and the condition the bitline was in beforehand. None of these quantities has two values; all of them take a range, and the result of an interaction is somewhere in that range.

The system above is digital, and unforgivingly so: a bit is zero or one, and a memory that returns "mostly one" has returned a wrong answer.

The conversion happens in exactly one place — the shared sensing circuitry at the end of the bitline, which takes a small continuous shift and produces a definite digital value. That is the boundary Chapter 2.1 §2 drew, now located physically: it is at the edge of the array, not inside the cell.

Two things follow that are worth holding permanently.

The digital abstraction is manufactured, not discovered. Below the sensing circuitry there are no bits, only charge. This is why memory can be marginally wrong — a possibility that has no meaning in logic, and the reason Chapter 2.2 §3's failures are statistical and condition-dependent.

And it is why modelling the cell in RTL is a category error rather than a simplification. A logic variable is on the digital side of the boundary by construction. Using one to represent something on the analog side removes the very property — a continuous state that can be near, far from, or between its targets — that makes sensing necessary, restoration necessary, and refresh necessary. The model would be clean, simulate perfectly, and teach a reader that DDR's mechanisms are arbitrary.

6. Density, and What It Costs at the System Level

Chapter 1.6 argued the economics. This chapter can now state the physical mechanism behind it in one line: the cell is small because almost everything a memory needs was moved out of it and shared.

Count what the cell does not pay for, per bit: address decoding, sensing, amplification, driving, data routing, timing control, error correction. All of it exists, all of it is essential, and all of it is amortised across many cells — which is why a memory die's periphery is a significant fraction of its area rather than a rounding error.

The system-level bill, collected in one place:

Read the right-hand column as a table of contents for the DDR standard. Row-oriented commands, timing constraints between operations, a scheduler, a refresh manager, a protocol with ordering rules: each entry is a job the cell budget refused to pay for. The standard is not complicated because standards tend to be complicated. It is complicated in exactly the ways the cell is simple.

7. The Digital Invariant the Structure Imposes

There is no behavioural RTL in this chapter, but the physical structure does create one genuine digital contract, and it is worth writing down because violating it damages data in a way that is hard to diagnose.

§3 established that asserting a wordline connects those cells to their bitlines, and §4 established that a bitline serves many cells. Therefore:

At most one wordline per shared bitline group may be asserted at a time.

Assert two and two cells' charges are connected to the same bitline simultaneously. Their charges mix; the resulting bitline condition reflects neither cell; and both cells lose their state. The result is not a wrong read — it is destruction of stored data in both locations, with no error reported anywhere, because nothing in the array can detect it.

That is a one-hot (or all-zero) requirement on the selection logic, and it is exactly the kind of property assertions exist for:

// VERIFICATION-ONLY. This is NOT a cell model and NOT array RTL -- it is a
// safety property on the SELECT logic that drives an array, expressed against
// whatever signal vector represents the asserted wordlines.
//
// The physical reason is in §4: two cells connected to one bitline mix their
// charges and BOTH lose their state, with nothing in the array able to report
// it. So this is a data-destruction property, not a data-correctness one.

// P1 -- at most one wordline asserted. Zero is legal (no row selected);
// two or more is never legal.
property p_wordline_select_is_onehot0;
  @(posedge clk) disable iff (!rst_n)
    $onehot0(wl_sel);
endproperty
assert property (p_wordline_select_is_onehot0);

// P2 -- selection is stable while an access is in progress. Changing the
// selected row underneath an access connects a second cell to a bitline that
// is already mid-interaction, which is P1's failure spread over two cycles
// instead of one -- and a one-hot check alone would not catch it.
property p_selection_stable_during_access;
  @(posedge clk) disable iff (!rst_n)
    access_active |-> $stable(wl_sel);
endproperty
assert property (p_selection_stable_during_access);

What these prove and what they do not. They prove the select logic never commands an illegal combination, which is the failure a decoder bug or a mid-access change would produce. They prove nothing about the array itself — no assertion can, because the array is on the analog side of §5's boundary and has no digital observables. That division is the honest one: assert the digital control that drives the physical structure, and never pretend to assert the physics.

Why P2 is not redundant. A designer who adds P1 and stops has checked instantaneous legality. P2 catches the sequential version of the same fault, where each individual cycle is one-hot but the selection moves while an interaction is underway. It is the harder bug and the less obvious property, which is a common shape: the instantaneous invariant is easy to think of and the temporal one is where the real defect lives.

8. Verification and Design Perspective

For RTL engineers. You will not write a cell. You will write, or integrate with, logic whose correctness depends on the structure in this chapter: selection that must be one-hot and stable, sequencing that must not overlap incompatible operations, and control that must treat a row as the unit of work rather than a word. The invariants in §7 belong in that logic's verification, and the reason to understand the cell is so you know what an apparently harmless violation actually destroys.

For verification engineers. Two lessons. First, the array is not observable in the way logic is — below §5's boundary there are no signals to check, so the verification target is the control that drives the array and the model of the array's response. Second, this chapter names a failure class with no error signal: mis-selection destroys data silently, so its check has to be a property on the selector rather than a comparison of returned data. A scoreboard notices the consequence only if it later reads one of the two damaged locations.

For anyone reading a memory model. A behavioural model in a testbench is on the digital side of the boundary: it stores values and returns them. That is appropriate and useful, and it means the model cannot exhibit marginal behaviour, charge sharing, or mis-selection damage unless those were deliberately added. Knowing what the model cannot show you is what stops you from concluding that the design is proven against behaviour the model never had.

9. Common Misconceptions

"A DRAM cell is addressed individually." Wrong model: each cell has its own select, like an entry in a register file. Engineering consequence: the engineer expects word-granular device behaviour and cannot explain row-oriented commands, the cost asymmetry between accesses to the same row and to different rows, or why refresh covers many cells at once. The whole shape of DDR looks arbitrary. Observable failure: performance models that treat every access as equivalent, and stimulus that never exercises a row change — Chapter 1.4 §10's mistake, with its cause now visible. Correct model: one wordline runs across many cells, so the smallest selectable unit is a row. A per-cell select wire is a per-bit cost the cell budget cannot pay. Prevention: when reasoning about a DRAM access, ask what happened to the rest of the row. The answer is never "nothing".

"The cell outputs its value onto the bitline." Wrong model: selection causes the cell to drive its stored value out. Engineering consequence: the destructive read and the need for restoration both become inexplicable, so they get treated as protocol quirks rather than as physical necessities. Correct model: the cell has no drive. Selection connects a small capacitance to a much larger one, and the two reach a shared condition — which reveals what the cell held and simultaneously destroys it. Prevention: replace the word "output" with "share" whenever thinking about a DRAM read. The substitution fixes most of the reasoning by itself.

"The bitline is just a wire." Wrong model: the connection between cell and sensing is an ideal conductor. Engineering consequence: no explanation for why the signal is small, why sensing is difficult, or why array dimensions are a design trade-off rather than a free parameter. Correct model: the bitline is long, carries many attachments, and has capacitance much larger than any single cell's. It is a circuit element that the cell's charge must be shared with, not a path the charge travels along intact. Prevention: think of the bitline as the larger of the two capacitances in every read. Module 3 develops it as an engineered object.

"A capacitor and a transistor could be written in RTL if you modelled them carefully." Wrong model: the physics is just detail that a sufficiently careful digital model captures. Engineering consequence: a model that removes continuous state, charge sharing and marginality — every property that makes sensing, restore and refresh necessary — and therefore teaches that those mechanisms are arbitrary. Correct model: the cell is on the analog side of §5's boundary. RTL is the right tool for the digital control obligations the physics creates, which is exactly where this module uses it (2.3, 2.6). Prevention: ask which side of the sensing boundary a thing lives on before choosing a notation for it.

"Adding a second transistor would fix DRAM's problems." Wrong model: the cell's limitations are an oversight that a slightly richer cell would remove. Engineering consequence: dismissing the actual constraint. Devices per bit is the cost term paid at every bit (Chapter 1.6 §2), so a richer cell directly attacks the only property that justifies this tier. Correct model: the cell is minimal on purpose. Making it richer produces something with better behaviour and worse economics — which, at several transistors per bit, is the static cell of Chapter 1.3, a technology that already exists and already occupies a different tier. Prevention: remember that the tiers are different points in the same trade space. "Improving" a cell usually means moving it to a tier that is already occupied.

10. Debugging — Data Destroyed With No Error Anywhere

Symptom. Locations in memory are corrupted. Not the location that was accessed — a different location, and reproducibly the same wrong pairing. Nothing reports an error. The corruption appears immediately after particular accesses rather than developing over time.

The last two clues matter enormously: immediate, deterministic, paired corruption is not a 2.2 mechanism. Leakage failures are statistical, condition-dependent and time-dependent. This is a selection fault, and the reasoning is different.

Mechanism 1 — two wordlines asserted simultaneously. What to observe: the selection vector driven at the array, checked for one-hot-zero on every cycle. Expected evidence: two bits set, and the two corrupted locations correspond to the two selected rows. How to discriminate: P1 in §7 fails on the exact cycle. Without it, the tell is that the pair of damaged rows is consistent and maps to two decoder outputs — which points straight at the decode logic rather than at anything analog.

Mechanism 2 — selection changed during an access. What to observe: the selection vector's stability across the whole duration of an access, not just its legality in each cycle. Expected evidence: one-hot in every individual cycle but a change mid-access. How to discriminate: P2 in §7. This is the case a one-hot check alone passes, so if P1 is clean and the symptom persists, this is the next suspect — and it is the more likely of the two in a design whose decoder was reviewed.

Mechanism 3 — an access was terminated before restoration completed. What to observe: whether every access ran to completion, including the restoration phase, before the row was deselected. Expected evidence: corruption confined to the accessed row rather than a pair. How to discriminate: the corruption pattern. One damaged row means the row was disturbed and not repaired (2.6); two damaged rows means two were connected together. Counting the damaged rows separates these immediately and is the cheapest observation available.

Mechanism 4 — the addressing is simply wrong. What to observe: whether the "corrupted" location is the one the system believes it wrote to. Expected evidence: data appearing intact but at an unexpected address, with no actual loss. How to discriminate: if the data is present somewhere, nothing was destroyed and this is an address-mapping bug, not a physical one. Check this early: it is common, cheap to test, and mistaking it for mechanism 1 wastes a great deal of time.

Mechanism 5 — not this chapter. What to observe: whether the corruption is statistical and correlates with temperature, elapsed time or access density. Expected evidence: non-reproducible, condition-dependent failures. How to discriminate: reproducibility. Deterministic pairing points here; statistical drift points at Chapter 2.2 §8.

Root-cause discrimination in one observation. Count the damaged rows per event and check whether the damage is reproducible. Two rows, reproducible → mechanisms 1 or 2, separated by whether each cycle was individually legal. One row, reproducible → mechanism 3. Data intact elsewhere → mechanism 4. Not reproducible → mechanism 5, a different chapter and a different investigation.

The reasoning lesson. This failure class has no error signal by construction — the array cannot detect it, so nothing reports it. That makes the assertions in §7 not a nicety but the only practical detection mechanism, and it is a general pattern worth internalising: when a fault damages state silently, the check must be on the logic that could cause it, never on the state that suffered it.

11. Interview Reasoning

"Describe the DRAM cell and explain why it has exactly that content." One access transistor and one storage capacitor, with a wordline driving the transistor's gate and a bitline connected to its other side. The content is a cost budget rather than a design preference: anything in the cell is paid at every bit, and cell area is the dominant term in cost per bit, so the cell contains the minimum that can work — no decoder, no buffer, no amplifier, no driver. A strong answer names the consequence: everything a memory needs beyond storage was moved outside and shared, and each of those relocations is a mechanism in the DDR standard.

"Why is the smallest accessible unit of a DRAM device a row rather than a bit?" Because selection is shared. One wordline runs across many cells, so asserting it connects every cell along it to its own bitline simultaneously. A per-cell select would be a second wire paid at every bit, which the cell budget cannot afford. Everything row-oriented in DDR — row-granular access, the cost asymmetry between same-row and different-row accesses, row-granular refresh — follows from that one wire-count decision.

"Why is the signal produced by a DRAM read small?" Because a deliberately minimised cell capacitance is shared with a long bitline whose capacitance is much larger, and the cell has no drive with which to force the bitline anywhere. The charge redistributes across the larger capacitance, so the bitline's condition changes only slightly — in a direction that reveals the stored state. Both factors are structural: the cell is small because density demands it, and the bitline is large because it must serve many cells to amortise the sensing circuitry.

"Why is a DRAM read destructive? Answer from the structure, not from the operation." Because connecting a driveless cell to a much larger capacitance necessarily moves the cell's charge out of it. The read does not do something destructive — sharing charge with a larger capacitance is what selection physically means for a cell with no drive. That is why restoration is mandatory rather than optional: the access has consumed the stored state, and something external must re-establish it.

"Why can you not write a DRAM cell in SystemVerilog?" Because a logic variable sits on the digital side of the sensing boundary by construction: it has exactly two values, holds them perfectly, is read without disturbance and is driven. The cell has none of those properties — it holds a continuous quantity, leaks, is disturbed by being read, and cannot drive. A model that removes all of that removes every reason DDR has sensing, restoration and refresh. RTL is the right tool one level up, for the digital control obligations the physics creates.

"What happens if two wordlines in the same bitline group are asserted at once, and how would you catch it?" Two cells are connected to one bitline, their charges mix, the resulting bitline condition reflects neither, and both cells lose their stored state — with no error reported, because nothing in the array can detect it. It is silent data destruction. Catching it means asserting a one-hot-zero property on the selection vector, plus a stability property so the selection cannot move mid-access, which is the harder and more commonly missed of the two. A data-comparison check finds it only later and by luck.

12. Engineering Check

A proposal: add a small buffer to each DRAM cell so it can drive its value onto the bitline instead of sharing charge. This would make the read non-destructive, remove the need for restoration, and produce a large signal that is easy to sense.

Every one of those claims is true. Work out why the proposal is still wrong.

1. What does the proposal cost, in the term that matters? Devices per bit — the cost paid at every single bit, and the dominant term in cost per bit (Chapter 1.6 §2). A buffer is several transistors, and it needs a supply connection, which means more contacts and more wiring per cell. The cell's footprint grows substantially.

2. What would the resulting technology be? Something with a driving, non-destructively-readable cell of several transistors per bit. That is the static cell of Chapter 1.3 — the proposal does not invent a better DRAM, it re-derives SRAM. And SRAM already occupies a tier, for exactly the reasons this curriculum gave: excellent behaviour, unaffordable capacity.

3. Which of the module's obligations would actually disappear? Restoration, because the cell would no longer be disturbed by reading. Sensing would become far easier. But refresh would not necessarily disappear from the same change — that requires the cell to maintain its state against leakage, which needs continuous drive rather than drive on demand. A buffer that only drives when selected leaves a passively stored node between accesses. The obligations are separable, and the proposal quietly assumes it fixes all of them.

4. Would row-oriented access disappear? No — and this is the subtle one. Row granularity comes from selection being shared, not from the read mechanism. Unless each cell also gets its own select wire, one wordline still selects many cells, and access stays row-oriented. Two independent budget decisions produce two independent consequences, and conflating them is the most common error in this kind of reasoning.

5. So what is the correct characterisation of the proposal? It trades the tier's defining property for behaviour the tier does not need. Main memory's requirement is capacity at a price (Chapter 1.7); it tolerates the complexity because the complexity is cheaper than the alternative. Sensing, restoration, refresh and a scheduler are a large one-time engineering cost amortised across an industry. Devices per bit is a cost paid a billion times per part, forever.

6. What is the real engineering direction, then? Keep the cell minimal and make the minimum manufacturable — which is why DRAM capacitors are elaborate three-dimensional structures that preserve capacitance while the footprint shrinks, and why sensing circuitry and on-die error correction have become more sophisticated over generations. When a cost is paid per bit, move work out of it and make the remainder better — the same principle Chapter 1.6 §11's exercise reached from the economics side.

13. Summary

A DRAM cell is one access transistor and one storage capacitor, reached by two wires: a wordline that drives the transistor's gate and decides when the cell participates, and a bitline shared with many other cells that decides where its charge goes. There is nothing else — no decoder, no buffer, no amplifier, no driver, no memory of having been accessed.

That content is a cost budget, not a description. Anything in the cell is paid at every bit, so the cell holds the minimum that can work and everything else was moved outside and shared. Each relocation is a mechanism in the DDR standard: shared selection makes the unit of access a row; absent gain makes sensing necessary and shared, which makes access exclusive; absent drive makes restoration mandatory; absent self-maintenance makes refresh a scheduled correctness obligation; and absent any stored state in the cell means all ordering and legality must be enforced by a controller.

Selection is a physical connection, not a message — a cell cannot know it was selected, signal that it was, or decline. And because one wordline crosses many cells, the smallest selectable unit is a row, which is the single most consequential sentence in the module.

The bitline is the larger of the two capacitances in every read: long, heavily attached, and much larger than any single cell's storage. So when a driveless cell is connected to it, the charge redistributes, the bitline shifts only slightly — a small signal, explained structurally — and the cell's state is gone. The destructive read is in the wiring, not in the operation.

And the cell is analog, while the system is digital. The conversion happens in one place: the shared sensing circuitry at the edge of the array. Below that boundary there are no bits, only charge — which is why memory can be marginally wrong, and why modelling the cell in RTL is a category error rather than a simplification.

14. What Comes Next

This chapter has already given away the next one. §4 showed that connecting a driveless cell to a much larger capacitance shares its charge away, and §13 called the destructive read a property of the wiring rather than of the operation.

Chapter 2.5 makes that precise and follows it through: what the sequence of a read actually is, why the resulting signal must be amplified rather than merely detected, what state the cell is left in, and why the read cannot end there. It is the chapter where the module's central mechanism is finally laid out end to end — and it sets up 2.6, which answers the question a software engineer finds strangest about DRAM: why does a read contain a write?

Return to Capacitor Storage for the storage element, Charge Storage and Leakage for why its state decays, or The Refresh Requirement for the obligation that decay creates. For the tier-level argument this structure serves, see Why DRAM Dominates Main Memory. The full path is on the DDR tutorials index.