Capacitor Storage

Module 1 established why DRAM exists: its cell is the smallest practical way to store a bit, which is what makes a system's working memory affordable, and the bill for that smallness arrives as leakage, destructive reads and a sequenced access. Module 1 named those consequences and deliberately did not open them.

Module 2 opens them. And it has to start further down than most treatments do, with a question that sounds almost philosophical and is entirely practical:

A capacitor stores charge. A bit is an abstraction with exactly two values. What actually happens when the first is used to represent the second?

The honest answer changes how an engineer reasons about every later DDR mechanism. Nothing inside the cell is digital. There is no zero and no one in there — there is an amount of charge, which is a continuous physical quantity, sitting on a node that nothing is actively holding. The digital value the system eventually reads is not retrieved from the cell; it is decided about the cell, by circuitry outside it, on evidence the cell provides. Every hard problem in this module follows from that sentence.

1. What a Capacitor Actually Does

Strip it to the mechanism. A capacitor is two conductive regions separated by an insulator. Move charge onto one side and it cannot cross to the other, so the charge stays — held in place by the fact that there is nowhere for it to go. The separated charge produces a voltage between the two sides, and the relationship is the defining one:

   Q  =  C · V

   Q   the charge separated on the node
   C   the capacitance — a property of the structure's geometry and materials
   V   the resulting voltage across it

That equation is the whole storage mechanism, and three readings of it matter for DRAM.

Charge and voltage are proportional, not independent. Putting charge on the node raises its voltage; removing charge lowers it. "The node is charged" and "the node is at a raised voltage" are two descriptions of one condition. This matters because a designer thinks in voltages and the physics keeps score in charge, and the conversion factor between the two is the capacitance.

Capacitance is set by the structure, so it is a design variable — one being pushed in the wrong direction for storage. A physically smaller capacitor has less capacitance. Density demands physically smaller cells. Therefore density demands less capacitance per cell, and with less capacitance the same voltage represents less charge. The trade Chapter 1.6 described in cost terms appears here as a physical quantity getting smaller with every generation. That DRAM has remained manufacturable at all while cell area shrank is an achievement of capacitor structure engineering, and it is why real DRAM capacitors are elaborate three-dimensional structures rather than two flat plates.

Nothing in the equation maintains anything. It describes a state, not a process. A capacitor with charge on it is not doing something to keep the charge there; the charge remains because no path exists for it to leave. That distinction — between a state actively maintained and a state merely undisturbed — is the single most important difference between this storage element and the one in Chapter 1.3, and 2.2 is what happens when the "no path exists" part turns out to be approximate.

2. Storing a Bit Means Choosing Two Distinguishable States

A capacitor's charge is a continuous quantity: it can take any value in a range. A bit has two values. So representing a bit requires a convention, and the convention is what a memory actually implements.

Pick two target states. Drive the storage node toward one extreme of its available range for one logical value, and toward the other extreme for the other. In DRAM terms these are usually described as charged and discharged — the node driven toward the supply, or toward ground. Which extreme means which logical value is a design decision, not a law of nature, and real devices do not always make the naive choice.

Write by establishing a state. Writing means connecting the node to something that drives it to the chosen extreme and holding it long enough that it arrives.

Read by determining which state it is in. Reading does not mean retrieving a stored symbol. It means measuring the node's electrical condition and deciding which of the two target states it is nearer to.

That last sentence is where the abstraction boundary sits, and it is worth drawing explicitly because almost every misconception in this module comes from putting the boundary in the wrong place.

Read the figure as a boundary, not a pipeline. Everything to the left of the sensing arrow is physics: a quantity of charge, a voltage, a condition that can be nearer one target or the other and anywhere in between. Everything to the right is digital: a value with exactly two possibilities that the rest of the machine can compute with. The bit does not travel across that arrow — it is created at it.

Which yields the reframing this chapter exists for: a DRAM cell does not contain a bit. It contains evidence from which a bit can be inferred, and the quality of that evidence is what the rest of Module 2 is about.

3. Why the Stored Signal Is Small

"Small signal" gets repeated about DRAM until it stops meaning anything. Here is what it means mechanically, built from §1's equation and nothing else.

The charge representing a state is Q = C · V. The voltage swing available is set by the supply the device runs from. The capacitance is set by the cell's physical structure — which density has driven relentlessly downward, because the cell is the replicated term in Chapter 1.6's cost chain.

So the stored charge is the product of a modest voltage and a deliberately tiny capacitance. Both factors push the same way. The result is a genuinely small quantity of charge, and it gets no larger as generations advance — capacitance shrinks with the cell, and supply voltages have trended down rather than up.

Why that is a system problem, not a circuit curiosity. A large stored charge would be easy to detect: connect the node to something and the effect would be unmistakable. A small stored charge produces a small effect, and a small effect has to be distinguished from everything else that can produce a small effect — manufacturing variation between nominally identical cells, coupling from neighbouring structures, thermal noise, and supply disturbance. The narrower the real signal, the more carefully the surrounding circuitry has to be designed, and the more of the device's area and effort goes into the machinery that makes a small difference decidable.

And it explains why the cell cannot stand alone. A structure holding this little charge is not a component that reports its contents. It is a component that influences something else slightly, and that influence has to be amplified before it means anything. Chapter 2.5 is that influence in detail; Module 3 is the circuitry that resolves it.

4. The Two Things the Cell Does Not Have

This is the section to remember. Everything difficult about DRAM comes from two absences, and naming them precisely makes the rest of the module derivable rather than memorisable.

The cell has no drive. Compare it with the static cell of Chapter 1.3: that cell's two inverters are connected to the supply and continuously push their nodes to full levels. A DRAM storage node is connected to nothing except its access device. When the cell participates in a read, it cannot assert its value onto anything — it can only let its charge interact with whatever it has been connected to, and the result is a shared condition rather than a driven one.

The cell has no gain. Gain means a small input producing a larger output — the ability to take a weak signal and make a strong one. The static cell's inverters have gain, which is why they restore their own state continuously and why reading one is harmless. A capacitor and a switch have no gain whatsoever. Whatever charge is on the node is all the signal there will ever be, and interacting with the node spends it rather than copying it.

Now derive the module from those two absences:

No drive plus no gain means reading must be an interaction, not a query. To learn anything about the node, it must be connected to something — and connecting it necessarily changes it, because the cell cannot hold its state against the connection. That is 2.5, and it is a consequence rather than a design flaw.

No gain means amplification must happen elsewhere. The small evidence has to be resolved into a digital decision by external circuitry, and that circuitry is expensive enough that it must be shared across many cells rather than provided per cell. That sharing is what makes the array economics work and what makes access exclusive — the mechanism Chapter 1.6 §3 described in cost terms.

No drive means the state cannot be re-established by the cell itself. After anything disturbs it, something external must put it back. That is 2.6.

And no drive means nothing opposes gradual loss. A state that is merely undisturbed rather than actively maintained degrades whenever anything disturbs it, including the slow unavoidable processes 2.2 is about.

5. Volatility, Precisely

"Volatile" was used loosely in Module 1. At cell level it can be stated exactly, and the exactness matters for design.

The stored state is a quantity of separated charge. That charge was put there by circuitry powered from the supply. Remove the supply and two things follow: nothing can establish a state any more, and nothing can replace charge that drains away. Since 2.2 shows that draining is continuous and unavoidable, the stored states decay toward indistinguishability and the information is gone.

Two distinctions worth holding.

Volatility here is not the same property as the static cell's. A static cell loses its contents when power is removed because its maintenance stops — the loop collapses. A DRAM cell loses its contents because its charge leaks away with nothing to replenish it. Both are volatile; the mechanisms differ, and the difference shows up in how long the data survives after power goes away and in what a designer can or cannot assume during a power transition.

Loss of data is not instantaneous, and that is a design consideration rather than a comfort. The decay is a physical process with a duration, so contents do not vanish at the exact moment power is removed. Engineers building systems with security or safety requirements around residual data treat that interval as real and specify accordingly. This chapter states the direction and quotes no interval: retention behaviour after power removal depends on the device, the temperature and the conditions, and it is a measured property of a part rather than a general fact.

6. Where This Shows Up in Real Engineering Work

A cell-physics chapter can feel remote from an RTL or verification job. It is not, and these are the specific places it surfaces.

Interpreting what a memory model is not telling you. A behavioural memory model in a testbench returns the value that was written. A real device returns a value that circuitry decided from a small physical signal. Most of the time those agree, and the interesting failures are exactly where they do not — marginal cells, extreme temperature, voltage droop, or a part near the edge of its specification. An engineer who believes the cell stores a digit has no mental model for how a memory can be nearly right.

Understanding why device qualification looks the way it does. Memory parts are tested across voltage and temperature with patterns designed to create worst-case conditions for the charge-sharing and sensing mechanisms, not merely to check that every address can be written and read. The reason is §3: the signal is small, and how small depends on conditions. That is why memory test is a specialism and why it takes real time per part — a cost that appeared as a term in Chapter 1.6 §2's chain.

Knowing which layer owns a symptom. A bit that is occasionally wrong in a way that correlates with temperature, with voltage, or with how long data sat untouched is a device-level symptom. A bit that is wrong deterministically for a particular address or access sequence is a logic-level symptom — a controller, an interconnect, or an addressing bug. Those two require completely different investigations, and knowing the cell mechanism is what lets an engineer tell them apart from the first observation rather than the tenth.

Appreciating why on-die error correction became normal. As cells shrink, the signal §3 describes gets no larger while the number of cells grows. Modern devices therefore include error-correction machinery on the die itself. This chapter's contribution is the reason: it is the natural consequence of storing information as an ever-smaller physical quantity across an ever-larger number of locations. The generation-specific details of what a particular standard requires belong to Module 25, not here.

7. Attributing a Fault to the Right Layer

The most useful thing this chapter gives a practising engineer is a discrimination rule, so it is worth stating as one. When memory returns a wrong value, the first question is not which bit but which layer — and the answer is almost always visible in the failure's conditionality.

A cell-level symptom is conditional. Below the sensing boundary there are no bits, only charge, so a marginal cell produces a decision that is nearly right — and whether it comes out right depends on circumstances. The signatures: the error rate changes with temperature; it changes with supply voltage; it changes with how long the data sat before being read; it affects different locations on different units, because cell-to-cell variation differs between dies; and repeating the access may give a different answer.

A logic-level symptom is unconditional. Above the boundary, values are digital and a fault is deterministic. The signatures: the same location wrong in the same way every time; the error following a particular access sequence rather than a particular condition; identical behaviour across units; and perfect reproducibility.

The discriminating experiment is cheap. Repeat the failing access without changing anything. Then repeat it at a different temperature. A result that changes is physics; a result that does not is logic. Two runs, and the investigation splits into two disjoint sets of causes — controller, addressing and datapath on one side, device margin and conditions on the other.

Why this belongs in a chapter about a capacitor. Because the rule is a direct consequence of Figure 1. An engineer who believes the cell stores a digit has no category for "nearly right", so every wrong bit looks like a logic bug and the conditional evidence gets discarded as noise. The boundary is what makes conditionality itself into diagnostic information — and Chapter 2.2 §8 is where the conditions are enumerated properly.

8. Why This Chapter Has No RTL

A deliberate note, because the temptation is real and the mistake is common.

It is easy to write something that looks like a DRAM cell:

   logic cell;                  // ← this is not a capacitor
   always_ff @(posedge clk)     // ← a capacitor has no clock
     if (write_en) cell <= din; // ← this cannot leak, share, or be sensed

Everything about that is wrong in a way that would be worse than teaching nothing. A logic variable has exactly two values, so it cannot represent a continuous quantity that can sit between them — which is the entire subject of this chapter. It holds its value perfectly, so it cannot leak. It is read without being disturbed, so it cannot model a destructive read. It is driven, so it needs no restore. And it has no clock in the physical world at all: the cell responds to its access device being turned on, not to an edge.

A model that removes every property under study is not a simplification. It is a different thing wearing the same name. A reader who learns the cell from that code would be unable to derive a single one of Module 2's consequences, and would be left concluding — as many engineers do — that DDR's complexity is arbitrary.

So this module keeps the abstraction levels apart, on purpose:

The third row is where RTL genuinely teaches, and this module uses it there substantially. Writing RTL for the first two rows would not be more rigorous; it would be less.

9. Common Misconceptions

"A DRAM cell stores a digital 0 or 1, like a flip-flop does." Wrong model: the cell contains a symbol that reading retrieves. Engineering consequence: the engineer has no way to reason about marginal behaviour, and treats any incorrect bit as a logic bug. They also cannot explain why sensing, restore or refresh exist, so DDR's complexity looks like arbitrary protocol overhead. Observable failure: an investigation that searches the controller for weeks for a fault that correlates with temperature and with elapsed time since the last access — the signature of a device-level mechanism. Correct model: the cell holds a continuous quantity of charge near one of two targets. The digital value is produced outside the cell, by circuitry deciding which target the state is nearer. Prevention: keep Figure 1's boundary in mind whenever reasoning crosses from logic into memory.

"Because it stores charge, it must slowly change its value from 1 to 0." Wrong model: leakage flips bits, so a cell gradually becomes a different digital value. Engineering consequence: an expectation that data degrades into wrong-but-valid values, when the real mechanism is loss of distinguishability — the two states converging until a decision cannot be made reliably. Correct model: the quantity drifts, and what fails is the decision, not a stored symbol. Which direction the drift goes depends on the cell's state and its surroundings. Prevention: think in terms of margin between states, not in terms of a value changing. 2.2 develops it.

"A bigger capacitor would solve DRAM's problems." Wrong model: signal margin is a free design choice. Engineering consequence: dismissing the real constraint. A larger capacitor is a larger cell, and cell area is the term paid at every bit (Chapter 1.6 §2) — so a bigger capacitor is directly a worse cost per bit, which is the only reason this tier exists. Correct model: cell capacitance sits at a deliberate optimum between manufacturability, signal margin and density. It is pushed as small as the surrounding circuitry can cope with, and no smaller. Prevention: treat signal margin as something that was spent to buy density, and ask what the surrounding design does to cope.

"The cell drives its value onto the bitline." Wrong model: the cell outputs its state. Engineering consequence: the destructive read becomes inexplicable, and so does the need for restore. If the cell drove its value, reading would cost nothing. Correct model: the cell has no drive and no gain. It can only let its charge interact with what it is connected to, and that interaction is what consumes the stored state. Prevention: remember §4's two absences. They are the generators of the whole module.

10. Interview Reasoning

"What is actually stored in a DRAM cell?" A quantity of separated charge on a storage node — a continuous physical quantity, not a digital symbol. Writing establishes the node near one of two target conditions; reading determines which target it is nearer to. A strong answer names the consequence: the digital value is produced by circuitry outside the cell, so it is a decision about evidence rather than a retrieval of a stored value, which is what makes marginal behaviour possible at all.

"Why is the signal in a DRAM cell described as small, and why does it matter?" Because stored charge is capacitance times voltage, and both factors are small: cell capacitance is deliberately minimised because cell area is the cost term paid at every bit, and supply voltages have trended downward rather than up. It matters because a small signal must be distinguished from everything else that produces small effects — cell-to-cell variation, coupling, noise, supply disturbance — so the machinery required to make the decision reliable is substantial, and it is why sensing circuitry has to be shared across many cells to be affordable.

"Why can a DRAM cell not simply be modelled as a register in RTL?" Because a register has none of the properties under study. It holds exactly two values, so it cannot represent a state between them; it maintains its value perfectly, so it cannot leak; it is read without disturbance, so it cannot be destructively read; and it is driven, so it never needs restoring. A model that removes leakage, charge sharing and the need for restoration removes every reason DDR has the mechanisms it has. The correct division is diagrams and prose for the physical layer, RTL for the digital control obligations the physical layer creates.

"Why does a smaller cell make the surrounding system more complex?" Because shrinking the cell reduces its capacitance, which reduces the stored charge for the same voltage, which shrinks the evidence sensing has to work from. Less margin means more effort outside the cell: more careful sensing, tighter tolerance to variation and noise, and — as cells shrink and counts grow — error correction on the die. The cell got simpler and cheaper; the obligations moved outward. That trade is the whole reason the main-memory tier is affordable and the whole reason its interface is demanding.

"DRAM is volatile and SRAM is volatile. Is that the same statement?" Both lose data without power, but by different mechanisms, and the difference is occasionally decisive. A static cell's state is actively maintained by transistors connected to the supply, so removing power collapses the maintenance immediately. A DRAM cell's state is merely undisturbed charge, so removing power means nothing replenishes what leaks — the decay is a physical process with a duration. That distinction matters for anyone reasoning about residual data across a power transition, where the relevant retention behaviour is a measured property of the part rather than a general fact.

11. Engineering Check

Two proposals to improve a memory design. Proposal A: double the cell capacitance to increase signal margin. Proposal B: keep the cell as it is and add more capable sensing circuitry.

1. What does Proposal A cost, in the terms this curriculum has established? Cell area, which is the term paid at every bit (Chapter 1.6 §2). A larger capacitor makes a larger cell, so the same capacity needs more silicon, so cost per bit rises — attacking the single property that justifies the tier's existence. It would also not be free at the array level, because a larger cell spreads the array out and lengthens the shared wiring.

2. What does Proposal B cost? Area and design effort in the periphery, which is amortised across many cells rather than paid per bit. That is a fundamentally better place to spend, which is why it is the direction real designs take — and it is why the periphery is a significant fraction of a memory die rather than a rounding error.

3. Which proposal describes what the industry actually did? Overwhelmingly B, generation after generation: cells were pushed smaller, and the machinery that copes with the resulting smaller signal became more sophisticated — culminating in error correction on the die itself. The principle generalises: when a cost is paid per bit, move work out of it.

4. Under what circumstance would A be right? When the signal becomes too small for any affordable periphery to resolve reliably — at which point margin is no longer a thing to be traded but a requirement to be met. Real cell design sits near that edge deliberately, which is why DRAM capacitor structures are elaborate: they are attempts to keep capacitance up while cell area goes down, which is neither proposal but a third thing, and much harder than either.

5. Which of the two absences in §4 does either proposal address? Neither. More capacitance and better sensing both improve the quality of the evidence; neither gives the cell drive or gain. So under both proposals the read is still destructive, restore is still required, and refresh is still mandatory. Signal margin and the structural obligations are different problems — and confusing them is how engineers come to expect that a better process will eventually make DDR simple.

6. What single measurement would tell you a real part is near its margin limit? Error rate as a function of conditions — voltage, temperature, and time since a location was last written. A part comfortably inside its margin shows no dependence; a part near the edge shows errors that appear and disappear with conditions. That dependence is also the signature §6 uses to separate a device-level symptom from a logic bug.

12. Summary

A capacitor stores a bit by holding separated charge on a node, where charge, capacitance and voltage are related by Q = C·V. The stored quantity is continuous, not digital: the cell holds an electrical state near one of two chosen targets, and the digital value is created outside the cell by circuitry deciding which target the state is nearer to. The bit does not travel out of the cell; it comes into existence at the sensing boundary.

The stored signal is small, because capacitance is deliberately minimised — cell area is the cost term paid at every bit — and the available voltage swing has trended downward. Both factors push the same way, and the signal does not get larger with newer generations. That is why so much design effort lives in the circuitry around the cell, and why that circuitry must be shared to be affordable.

The two properties the cell lacks generate the rest of the module. No drive: it cannot assert its value, only let its charge interact — so reading disturbs it and something external must restore it. No gain: the stored charge is all the signal there will ever be — so amplification must happen outside, in circuitry expensive enough to be shared.

Which is the module's thesis in one line: the DRAM cell is dense precisely because it contains nothing that does work, and every obligation in the DDR standard is a job that had to be moved outside the cell because the cell cannot do it.

13. What Comes Next

One assumption in this chapter was stated and not examined. §1 said the charge stays on the node "because there is nowhere for it to go", and §5 quietly admitted that this is approximate.

It is approximate in a way that changes everything. Chapter 2.2 examines the paths charge actually has available to it, why none of them can be eliminated, and what the consequence is for a state that nothing maintains: the two target conditions drift toward each other until the decision at Figure 1's boundary can no longer be made reliably. That is not a failure of the cell — it is the predictable behaviour of passive storage, and the reason this technology has an obligation no other tier in the hierarchy carries.

Return to DRAM for the tier-level argument, SRAM for the actively maintained cell this one should be contrasted against, or Cost vs Density for why the cell is under relentless pressure to shrink. The full path is on the DDR tutorials index.