Skip to content
VLSIMentor

Verilog · Chapter 16.1 · User-Defined Primitives

Combinational UDPs in Verilog — Truth-Table Primitives

A combinational user-defined primitive defines a single-output logic function directly as a truth table, with one row per input combination mapping the inputs to the output. It is the simplest kind of UDP: no state, no edges, just input-to-output rows between the table and endtable keywords. Don't-care entries compress the table by matching 0, 1, or x in an input position, so a multiplexer or a majority gate can be written in a few rows. Combinational UDPs are reference material and are not synthesizable, used mainly to model combinational standard cells compactly, including their exact handling of unknown inputs. This page drills the combinational UDP: its truth-table syntax, the don't-care symbol, and the cell models it can express.

Foundation10 min readVerilogUDPCombinationalTruth TableCell Modeling

Chapter 16 · Section 16.1 · User-Defined Primitives

1. The Engineering Problem

A combinational cell's behaviour — including how it treats unknown inputs — is sometimes most compactly captured as a truth table. A combinational UDP does exactly that:

A combinational UDP defines a single output as a truth-table function of its inputs — one row per input combination, with ? for don't-cares.

This page drills the combinational UDP.

2. Mental Model — A Truth Table Maps Inputs to One Output

3. The Combinational UDP

comb-udp.v
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
   // a 2:1 multiplexer as a combinational UDP:
   primitive mux2_udp (out, a, b, sel);
       output out;
       input  a, b, sel;
       table
           // a  b  sel : out
              1  ?  0    : 1;     // sel=0 → out follows a
              0  ?  0    : 0;
              ?  1  1    : 1;     // sel=1 → out follows b
              ?  0  1    : 0;
       endtable
   endprimitive
 
   // instantiate it like a gate:
   mux2_udp u (.out(y), .a(d0), .b(d1), .sel(s));   // (or positional)

Each row maps an input combination to out. The ? don't-cares compress the table — when sel=0, b is irrelevant (?), so two rows cover it. The UDP is instantiated exactly like a built-in primitive (Chapter 11.1).

Visual A — a combinational UDP truth table

Combinational UDP — inputs to one output by table

data flow
Combinational UDP — inputs to one output by tableinputs (a, b,sel)any combinationtable rowsin : out, with ? don't-caresone outputout per matching row
A combinational UDP maps input combinations to its single output via truth-table rows. Don't-care entries (?) match 0/1/x to compress the table. It models a combinational cell's exact behaviour, including unknown handling, and is instantiated like a built-in gate.

4. Don't-Cares and Coverage

  • ? matches 0, 1, or x in an input — used to ignore irrelevant inputs in a row.
  • Cover the cases you mean — input combinations not matched by any row produce x on the output (the UDP's default for unspecified inputs).
  • Compactness — don't-cares let a function be written in far fewer rows than full enumeration (the mux above is 4 rows, not 8).

5. Common Mistakes

  1. Multiple outputs — a UDP has exactly one output; use a module (16 overview).
  2. Incomplete table — unmatched input combinations output x; cover the intended cases (§4).
  3. Expecting synthesis — UDPs are simulation models, not synthesizable (16 overview).

6. Interview Q&A

7. Exercises

Exercise 1 — Write a UDP

Write a combinational UDP for a 2-input AND gate as a truth table.

Exercise 2 — Don't-cares

Rewrite a 3-input majority function UDP using ? to minimize rows.

8. Summary

A combinational UDP is a truth-table primitive:

  • One output, a truth-table function of the inputs (in : out rows).
  • ? is a don't-care that compresses the table.
  • Unmatched inputs → x; cover the intended cases.
  • Reference — simulation model of a combinational cell, not synthesizable.

The next sub-topic adds state: Chapter 16.2 Sequential UDPs drills stateful UDPs — latches and flip-flops with edge/level tables.