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Verilog · Chapter 16.3 · User-Defined Primitives

UDPs Advanced Techniques in Verilog — Edge Symbols & Limitations

This sub-topic closes the chapter with the notation depth and the boundaries of UDPs. The edge notation of a sequential UDP can be written as an explicit transition pair, such as 01 for rising or 10 for falling, or with shorthand symbols like r, f, p, n, and star for any value change. One key rule governs them: only one input may carry an edge in a given row, so each edge-sensitive row specifies a transition on exactly one input, with the others held at levels. Sequential UDPs may also use an initial statement to set the power-up state of the output register. Finally, UDPs have firm limits: exactly one output, a bounded number of inputs, no high-impedance value in the table, and no synthesis, which is why they stay reference material. This page drills all of it.

Foundation11 min readVerilogUDPEdge SymbolsLimitationsCell Modeling

Chapter 16 · Section 16.3 · User-Defined Primitives

1. The Engineering Problem

Reading and writing sequential UDPs fluently means knowing the edge notation in full and the rules and limits that bound them:

Edges are transition pairs ((01)) or shorthand (r f p n *); only one input may carry an edge per row; initial sets power-up state; and UDPs have firm limits (one output, no z, not synthesizable).

This page drills the edge notation, the rules, and the limitations.

2. Edge Notation and Shorthand Symbols

3. Edge Symbols in a Table

edge-shorthand.v
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Snippet
   // positive-edge D flip-flop using shorthand edge symbols:
   primitive dff_sh (q, clk, d);
       output q;  reg q;
       input  clk, d;
       table
           // clk  d : state : next
              r    0 :  ?    :  0;     // r = (01) rising edge → q = d
              r    1 :  ?    :  1;
              f    ? :  ?    :  -;     // f = (10) falling edge → hold
              ?    * :  ?    :  -;     // * = (??) d changes, no clk edge → hold
       endtable
   endprimitive

r replaces (01), f replaces (10), and * ((??)) on d covers data changes without a clock edge (held). This is the same flip-flop as 16.2, written compactly with the edge shorthand.

Visual A — edge symbols

Edge notation — pairs and shorthand

data flow
Edge notation — pairs and shorthandr = (01)rising edgef = (10)falling edgep / nany pos / neg edge (incl. x)* = (??)any value change
A sequential UDP's edge is an explicit transition pair (vw) — (01) rising, (10) falling — or a shorthand symbol: r for (01), f for (10), p/n for any positive/negative edge including x-transitions, and * for any value change (??). Shorthand keeps the edge table compact.

4. The One-Edge-Per-Row Rule and Power-Up State

Two rules complete the sequential UDP:

  • One edge per row — each table row may specify a transition (edge) on at most one input; the remaining inputs are levels. You cannot write two edges in the same row (a UDP responds to one event at a time).
  • initial sets power-up state — a sequential UDP may include an initial statement to set the starting value of its reg output (its state at time 0):
udp-initial.v
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
   primitive dff_init (q, clk, d);
       output q;  reg q;
       input  clk, d;
       initial q = 1'b0;        // power-up state of the output
       table
           r 0 : ? : 0;
           r 1 : ? : 1;
           f ? : ? : -;
           ? * : ? : -;
       endtable
   endprimitive

The initial q = 1'b0; gives the flip-flop a defined power-up value, like a reset state at time 0.

5. UDP Limitations

The boundaries that keep UDPs reference material:

  • Exactly one output — the first port; for multiple outputs use a module.
  • Inputs only besides the output — no inout; all non-output ports are inputs.
  • No z in the table — UDPs model 0, 1, x (high-impedance z is not a table value; a z input is treated as x).
  • Bounded inputs — a combinational UDP allows up to 10 inputs; a sequential UDP up to 9 (plus state) — tables grow large quickly.
  • Not synthesizable — UDPs are simulation models (cell-library and legacy gate-level), never synthesized design logic.

6. Common Mistakes

  1. Two edges in one row — illegal; at most one edge per row (§4).
  2. Expecting z — UDP tables have no z; only 0/1/x (§5).
  3. Multiple outputs / synthesis — one output, simulation-only (§5).

7. Interview Q&A

8. Exercises

Exercise 1 — Shorthand

Rewrite a negative-edge flip-flop UDP using f instead of (10).

Exercise 2 — One edge per row

Why can't a single UDP row specify edges on both clk and reset? How is asynchronous reset modeled instead?

Exercise 3 — Limitations

List three things a UDP cannot do that a module can.

9. Summary

Advanced UDP techniques complete the picture:

  • Edge notation — transition pairs (vw) or shorthand r (01), f (10), p/n (any pos/neg), * (??).
  • One edge per row — each row carries at most one input transition.
  • initial — sets the sequential UDP's power-up state.
  • Limitations — one output, no z, bounded inputs, not synthesizable.

User-defined primitives complete

This closes Chapter 16 User-Defined Primitives — the UDP overview, combinational UDPs (16.1), sequential UDPs (16.2), and these advanced techniques (16.3). You can now read the truth-table primitives found in cell libraries and legacy gate-level models, and understand why they stay reference material rather than design constructs.

The remaining chapters are timing reference: Chapter 17 Delay Modeling, 18 Timing Checks, and 19 Timing Regions — the signoff-adjacent topics that round out the language.