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Verilog · Chapter 16.2 · User-Defined Primitives

Sequential UDPs in Verilog — Latches & Flip-Flops by Truth Table

A sequential user-defined primitive models a stateful element such as a latch or flip-flop as a truth table that includes the element's current state and its next state. Its output is declared as a reg, which is what makes the primitive sequential, so the output value is remembered between evaluations. Each table row has three fields, the inputs, the current state, and the next state, and the way the inputs are written distinguishes the two kinds. Level-sensitive rows with plain input levels model a latch that is transparent while enabled, while edge-sensitive rows with transition notation model a flip-flop that captures on the clock edge. A dash in the next-state field means hold the current value. Sequential UDPs are reference material used to model library cells compactly, and this page covers the reg output, the state table, and both forms.

Foundation11 min readVerilogUDPSequentialLatchFlip-FlopCell Modeling

Chapter 16 · Section 16.2 · User-Defined Primitives

1. The Engineering Problem

Modeling a library flip-flop or latch — its exact capture behaviour and unknown handling — calls for a stateful primitive. A sequential UDP captures it as a truth table over state:

A sequential UDP models a latch or flip-flop as a truth table including current and next state; the output is reg (stateful), and rows are level-sensitive (latch) or edge-sensitive (flip-flop). - means hold.

This page drills the sequential UDP.

2. Mental Model — A Stateful Truth Table Over Current/Next State

3. A Latch UDP (Level-Sensitive)

latch-udp.v
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Snippet
   // a D latch — transparent when en=1, holds when en=0:
   primitive dlatch_udp (q, d, en);
       output q;  reg q;             // reg → sequential
       input  d, en;
       table
           // d  en : q(state) : q(next)
              ?  0  :    ?      :   -;     // en=0 → hold (no change)
              0  1  :    ?      :   0;     // en=1 → q = d
              1  1  :    ?      :   1;
       endtable
   endprimitive

The rows use plain input levels (level-sensitive). When en=0, the next state is - (hold, regardless of current state ?); when en=1, q follows d. This is a transparent latch — the canonical level-sensitive sequential UDP.

4. A Flip-Flop UDP (Edge-Sensitive)

dff-udp.v
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Snippet
   // a positive-edge D flip-flop — captures d on the rising clock edge:
   primitive dff_udp (q, clk, d);
       output q;  reg q;
       input  clk, d;
       table
           // clk    d : q(state) : q(next)
              (01)   0 :    ?      :   0;     // rising edge → q = d
              (01)   1 :    ?      :   1;
              (0?)   ? :    ?      :   -;     // partial/other clk → hold
              (?0)   ? :    ?      :   -;     // falling edge → hold
              ?    (??):    ?      :   -;     // d changes, no clk edge → hold
       endtable
   endprimitive

The (01) notation on clk denotes a rising edge — the output captures d only on that transition. The other rows (- next state) hold the value for non-capturing conditions (falling edge, d changing without a clock edge). This is a positive-edge D flip-flop — the canonical edge-sensitive sequential UDP. Edge notation ((vw)) is what distinguishes a flip-flop from a latch.

Visual A — sequential UDP: level vs edge

Sequential UDP — latch (level) vs flip-flop (edge)

data flow
Sequential UDP — latch (level) vs flip-flop (edge)reg outputstatefullevel rows →latchtransparent when enablededge rows (01) →flip-flopcaptures on edge- = holdno change
A sequential UDP has a reg output (stateful) and a table with current/next state. Level-sensitive rows model a latch (transparent when enabled); edge-sensitive rows with transition notation (01) model a flip-flop (capturing on the edge). A '-' in the next-state field holds the current value.

5. Common Mistakes

  1. Forgetting reg on the output — without it the UDP is combinational, not stateful (§2).
  2. Missing hold rows — non-capturing conditions need - (hold), or the output goes x (§4).
  3. Confusing level and edge — plain levels = latch; (vw) transitions = flip-flop (§3/§4).

6. Interview Q&A

7. Exercises

Exercise 1 — Latch UDP

Write a sequential UDP for an active-high D latch.

Exercise 2 — Flip-flop UDP

Write a sequential UDP for a negative-edge D flip-flop (capture on (10)).

Exercise 3 — Level or edge?

For a transparent latch vs an edge-triggered register, which table notation does each use?

8. Summary

A sequential UDP models stateful elements:

  • reg output — stateful; the table has inputs : current_state : next_state.
  • Latch — level-sensitive rows (transparent when enabled).
  • Flip-flop — edge-sensitive rows with transition notation ((01) rising); captures on the edge.
  • - = hold; reference — cell modeling, not synthesizable.

The last UDP sub-topic covers the notation in depth: Chapter 16.3 UDPs Advanced Techniques drills the edge symbols, shorthand, don't-cares, and UDP limitations.