Error Status, Sticky Flags and Receiver Re-Synchronisation

// ---------------------------------------------------------------------------
//  9.6 — sticky status, SET-DOMINANT, with an explicit clear input.
// ---------------------------------------------------------------------------
module uart_err_status (
    input  logic clk,
    input  logic rst_n,
    input  logic frame_error_evt_i,
    input  logic parity_error_evt_i,
    input  logic overrun_evt_i,
    input  logic break_evt_i,
    input  logic clear_i,                 // software clear, one cycle
    output logic frame_error_sticky_o,
    output logic parity_error_sticky_o,
    output logic overrun_sticky_o,
    output logic break_sticky_o,
    output logic any_error_o
);
    // SET-DOMINANT: when a clear and a new event land on the same cycle the
    // flag STAYS SET. Losing a real event to a clear that raced it is the
    // worse failure for diagnosis — §5 of the chapter argues this.
    always_ff @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            frame_error_sticky_o  <= 1'b0;
            parity_error_sticky_o <= 1'b0;
            overrun_sticky_o      <= 1'b0;
            break_sticky_o        <= 1'b0;
        end else begin
            if (clear_i) begin
                frame_error_sticky_o  <= 1'b0;
                parity_error_sticky_o <= 1'b0;
                overrun_sticky_o      <= 1'b0;
                break_sticky_o        <= 1'b0;
            end
            // Written AFTER the clear, so the set wins on a collision.
            if (frame_error_evt_i)  frame_error_sticky_o  <= 1'b1;
            if (parity_error_evt_i) parity_error_sticky_o <= 1'b1;
            if (overrun_evt_i)      overrun_sticky_o      <= 1'b1;
            if (break_evt_i)        break_sticky_o        <= 1'b1;
        end
    end

    assign any_error_o = frame_error_sticky_o | parity_error_sticky_o
                       | overrun_sticky_o     | break_sticky_o;
endmodule

//===========================================================================
//  uart_err_status_v — Synthesizable Verilog-2001
//
//  Sticky status, SET-DOMINANT, with an explicit software clear.
//
//  The collision case is the whole design decision: when clear_i and a new
//  event land on the SAME clock, the flag stays SET. Losing a real error to
//  a clear that raced it is the worse failure, because the condition has
//  already happened and the only record of it is this bit.
//
//  In Verilog the priority is expressed by WRITE ORDER inside one always
//  block: the later non-blocking assignment to the same register wins.
//===========================================================================
module uart_err_status_v (
    input  wire clk,
    input  wire rst_n,
    input  wire frame_error_evt_i,
    input  wire parity_error_evt_i,
    input  wire overrun_evt_i,
    input  wire break_evt_i,
    input  wire clear_i,
    output reg  frame_error_sticky_o,
    output reg  parity_error_sticky_o,
    output reg  overrun_sticky_o,
    output reg  break_sticky_o,
    output wire any_error_o
);
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            frame_error_sticky_o  <= 1'b0;
            parity_error_sticky_o <= 1'b0;
            overrun_sticky_o      <= 1'b0;
            break_sticky_o        <= 1'b0;
        end else begin
            if (clear_i) begin
                frame_error_sticky_o  <= 1'b0;
                parity_error_sticky_o <= 1'b0;
                overrun_sticky_o      <= 1'b0;
                break_sticky_o        <= 1'b0;
            end
            // Written AFTER the clear: the set wins on a collision.
            if (frame_error_evt_i)  frame_error_sticky_o  <= 1'b1;
            if (parity_error_evt_i) parity_error_sticky_o <= 1'b1;
            if (overrun_evt_i)      overrun_sticky_o      <= 1'b1;
            if (break_evt_i)        break_sticky_o        <= 1'b1;
        end
    end

    assign any_error_o = frame_error_sticky_o | parity_error_sticky_o
                       | overrun_sticky_o     | break_sticky_o;
endmodule

--==========================================================================
--  uart_err_status -- Synthesizable VHDL-2008
--
--  Sticky status, SET-DOMINANT, with an explicit software clear.
--
--  On a same-cycle collision between clear_i and a new event the flag STAYS
--  SET. In VHDL the priority is expressed by SIGNAL ASSIGNMENT ORDER inside
--  one process -- the last assignment to a signal before the process
--  suspends is the one that takes effect -- which is the same mechanism
--  Verilog uses, spelled differently.
--==========================================================================
library ieee;
use ieee.std_logic_1164.all;

entity uart_err_status is
    port (
        clk                   : in  std_logic;
        rst_n                 : in  std_logic;
        frame_error_evt_i     : in  std_logic;
        parity_error_evt_i    : in  std_logic;
        overrun_evt_i         : in  std_logic;
        break_evt_i           : in  std_logic;
        clear_i               : in  std_logic;
        frame_error_sticky_o  : out std_logic;
        parity_error_sticky_o : out std_logic;
        overrun_sticky_o      : out std_logic;
        break_sticky_o        : out std_logic;
        any_error_o           : out std_logic
    );
end entity uart_err_status;

architecture rtl of uart_err_status is
    signal frame_q  : std_logic;
    signal parity_q : std_logic;
    signal over_q   : std_logic;
    signal break_q  : std_logic;
begin

    frame_error_sticky_o  <= frame_q;
    parity_error_sticky_o <= parity_q;
    overrun_sticky_o      <= over_q;
    break_sticky_o        <= break_q;
    any_error_o           <= frame_q or parity_q or over_q or break_q;

    process (clk, rst_n)
    begin
        if rst_n = '0' then
            frame_q  <= '0';
            parity_q <= '0';
            over_q   <= '0';
            break_q  <= '0';
        elsif rising_edge(clk) then
            if clear_i = '1' then
                frame_q  <= '0';
                parity_q <= '0';
                over_q   <= '0';
                break_q  <= '0';
            end if;
            -- Assigned AFTER the clear: the set wins on a collision.
            if frame_error_evt_i  = '1' then frame_q  <= '1'; end if;
            if parity_error_evt_i = '1' then parity_q <= '1'; end if;
            if overrun_evt_i      = '1' then over_q   <= '1'; end if;
            if break_evt_i        = '1' then break_q  <= '1'; end if;
        end if;
    end process;

end architecture rtl;

// 1. clear and a new event on the same edge, flag previously clear
@(negedge clk) clr = 1'b1; fe_evt = 1'b1;
@(negedge clk) clr = 1'b0; fe_evt = 1'b0;
@(negedge clk);
check(fe_st === 1'b1, "SET-DOMINANT: collision leaves the flag SET");

//===========================================================================
//  tb_uart_err_status_v — self-checking Verilog-2001 testbench
//
//  The interesting property is not "a flag sets". It is the COLLISION: what
//  happens when a software clear and a new hardware event land on the same
//  clock. This design is SET-DOMINANT, and that is a contract to be tested,
//  not an accident to be discovered.
//
//  INDEPENDENCE: the checker tracks which events it injected and which
//  clears it issued, and derives the expected flag state from that history
//  alone.
//===========================================================================
`timescale 1ns/1ps

module tb_uart_err_status_v;

    reg clk = 1'b0, rst_n = 1'b0;
    always #5 clk = ~clk;

    reg  fe_evt = 1'b0, pe_evt = 1'b0, ov_evt = 1'b0, bk_evt = 1'b0, clr = 1'b0;
    wire fe_st, pe_st, ov_st, bk_st, any_err;

    uart_err_status_v dut (
        .clk(clk), .rst_n(rst_n),
        .frame_error_evt_i(fe_evt), .parity_error_evt_i(pe_evt),
        .overrun_evt_i(ov_evt), .break_evt_i(bk_evt), .clear_i(clr),
        .frame_error_sticky_o(fe_st), .parity_error_sticky_o(pe_st),
        .overrun_sticky_o(ov_st), .break_sticky_o(bk_st),
        .any_error_o(any_err)
    );

    integer checks = 0, failures = 0;

    task check;
        input cond;
        input [8*60-1:0] name;
        begin
            checks = checks + 1;
            if (cond) $display("  PASS %0s", name);
            else begin failures = failures + 1; $display("  FAIL %0s", name); end
        end
    endtask

    task pulse_fe; begin @(negedge clk) fe_evt = 1'b1; @(negedge clk) fe_evt = 1'b0; end endtask
    task pulse_pe; begin @(negedge clk) pe_evt = 1'b1; @(negedge clk) pe_evt = 1'b0; end endtask
    task pulse_ov; begin @(negedge clk) ov_evt = 1'b1; @(negedge clk) ov_evt = 1'b0; end endtask
    task pulse_bk; begin @(negedge clk) bk_evt = 1'b1; @(negedge clk) bk_evt = 1'b0; end endtask
    task pulse_clr;begin @(negedge clk) clr    = 1'b1; @(negedge clk) clr    = 1'b0; end endtask

    initial begin
        #200_000;
        $display("  FAIL watchdog: simulation did not finish");
        $display("== %0d checks, %0d failures ==", checks+1, failures+1);
        $display("   RESULT: VERILOG STATUS TESTS FAILED (timeout)");
        $finish;
    end

    initial begin
        $display("== uart_err_status_v : self-checking Verilog testbench ==");

        rst_n = 1'b0;
        repeat (4) @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0000, "reset: all flags clear");
        check(any_err === 1'b0,                      "reset: any_error clear");
        @(negedge clk) rst_n = 1'b1;
        @(negedge clk);

        // ---- each event sets ONLY its own flag ---------------------------
        pulse_fe; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b1000, "framing event sets only framing");
        check(any_err === 1'b1,                      "any_error follows");
        pulse_clr; @(negedge clk);

        pulse_pe; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0100, "parity event sets only parity");
        pulse_clr; @(negedge clk);

        pulse_ov; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0010, "overrun event sets only overrun");
        pulse_clr; @(negedge clk);

        pulse_bk; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0001, "break event sets only break");
        pulse_clr; @(negedge clk);
        check(any_err === 1'b0,                      "clear drops any_error");

        // ---- sticky: the flag outlives the event by design ---------------
        pulse_fe;
        repeat (20) @(negedge clk);
        check(fe_st === 1'b1, "sticky: flag survives long after the event");

        // ---- accumulation across different error types -------------------
        pulse_pe; pulse_ov; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b1110, "three distinct errors accumulate");
        pulse_clr; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0000, "one clear clears all four");

        // ---- THE COLLISION: clear and a new event on the same clock ------
        @(negedge clk) clr = 1'b1; fe_evt = 1'b1;
        @(negedge clk) clr = 1'b0; fe_evt = 1'b0;
        @(negedge clk);
        check(fe_st === 1'b1, "SET-DOMINANT: collision leaves the flag SET");

        // ---- and the same collision on a flag with nothing new -----------
        pulse_pe; @(negedge clk);
        @(negedge clk) clr = 1'b1; fe_evt = 1'b1;
        @(negedge clk) clr = 1'b0; fe_evt = 1'b0;
        @(negedge clk);
        check(fe_st === 1'b1, "collision: the colliding flag stays set");
        check(pe_st === 1'b0, "collision: other flags still clear normally");
        pulse_clr; @(negedge clk);

        // ---- a clear with no event clears cleanly ------------------------
        pulse_bk; @(negedge clk);
        check(bk_st === 1'b1, "break sticky set");
        pulse_clr; @(negedge clk);
        check(bk_st === 1'b0, "clear with no collision clears the flag");

        // ---- reset beats everything --------------------------------------
        pulse_fe; pulse_pe; pulse_ov; pulse_bk; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b1111, "all four set before reset");
        @(negedge clk) rst_n = 1'b0;
        repeat (2) @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0000, "reset clears all sticky flags");
        check(any_err === 1'b0,                      "reset clears any_error");
        @(negedge clk) rst_n = 1'b1;
        @(negedge clk);

        // ---- reset DURING a collision ------------------------------------
        @(negedge clk) rst_n = 1'b0; clr = 1'b1; fe_evt = 1'b1;
        repeat (2) @(negedge clk);
        check(fe_st === 1'b0, "reset wins over a set/clear collision");
        @(negedge clk) rst_n = 1'b1; clr = 1'b0; fe_evt = 1'b0;
        @(negedge clk);

        $display("== %0d checks, %0d failures ==", checks, failures);
        if (failures == 0) $display("   RESULT: ALL VERILOG STATUS TESTS PASSED");
        else               $display("   RESULT: VERILOG STATUS TESTS FAILED");
        $finish;
    end
endmodule

//===========================================================================
//  tb_uart_err_status_sv — self-checking Verilog-2001 testbench
//
//  The interesting property is not "a flag sets". It is the COLLISION: what
//  happens when a software clear and a new hardware event land on the same
//  clock. This design is SET-DOMINANT, and that is a contract to be tested,
//  not an accident to be discovered.
//
//  INDEPENDENCE: the checker tracks which events it injected and which
//  clears it issued, and derives the expected flag state from that history
//  alone.
//===========================================================================
`timescale 1ns/1ps

module tb_uart_err_status_sv;

    logic clk = 1'b0, rst_n = 1'b0;
    always #5ns clk = ~clk;

    logic fe_evt = 1'b0, pe_evt = 1'b0, ov_evt = 1'b0, bk_evt = 1'b0, clr = 1'b0;
    logic fe_st, pe_st, ov_st, bk_st, any_err;

    uart_err_status dut (
        .clk(clk), .rst_n(rst_n),
        .frame_error_evt_i(fe_evt), .parity_error_evt_i(pe_evt),
        .overrun_evt_i(ov_evt), .break_evt_i(bk_evt), .clear_i(clr),
        .frame_error_sticky_o(fe_st), .parity_error_sticky_o(pe_st),
        .overrun_sticky_o(ov_st), .break_sticky_o(bk_st),
        .any_error_o(any_err)
    );

    int unsigned checks = 0, failures = 0;

    task automatic check(input bit cond, input string name);
        checks++;
        if (cond) $display("  PASS %0s", name);
        else begin failures++; $display("  FAIL %0s", name); end
    endtask

    task pulse_fe; begin @(negedge clk) fe_evt = 1'b1; @(negedge clk) fe_evt = 1'b0; end endtask
    task pulse_pe; begin @(negedge clk) pe_evt = 1'b1; @(negedge clk) pe_evt = 1'b0; end endtask
    task pulse_ov; begin @(negedge clk) ov_evt = 1'b1; @(negedge clk) ov_evt = 1'b0; end endtask
    task pulse_bk; begin @(negedge clk) bk_evt = 1'b1; @(negedge clk) bk_evt = 1'b0; end endtask
    task pulse_clr;begin @(negedge clk) clr    = 1'b1; @(negedge clk) clr    = 1'b0; end endtask

    initial begin
        #200us;
        $display("  FAIL watchdog: simulation did not finish");
        $display("== %0d checks, %0d failures ==", checks+1, failures+1);
        $display("   RESULT: SYSTEMVERILOG STATUS TESTS FAILED (timeout)");
        $finish;
    end

    initial begin
        $display("== uart_err_status : self-checking Verilog testbench ==");

        rst_n = 1'b0;
        repeat (4) @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0000, "reset: all flags clear");
        check(any_err === 1'b0,                      "reset: any_error clear");
        @(negedge clk) rst_n = 1'b1;
        @(negedge clk);

        // ---- each event sets ONLY its own flag ---------------------------
        pulse_fe; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b1000, "framing event sets only framing");
        check(any_err === 1'b1,                      "any_error follows");
        pulse_clr; @(negedge clk);

        pulse_pe; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0100, "parity event sets only parity");
        pulse_clr; @(negedge clk);

        pulse_ov; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0010, "overrun event sets only overrun");
        pulse_clr; @(negedge clk);

        pulse_bk; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0001, "break event sets only break");
        pulse_clr; @(negedge clk);
        check(any_err === 1'b0,                      "clear drops any_error");

        // ---- sticky: the flag outlives the event by design ---------------
        pulse_fe;
        repeat (20) @(negedge clk);
        check(fe_st === 1'b1, "sticky: flag survives long after the event");

        // ---- accumulation across different error types -------------------
        pulse_pe; pulse_ov; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b1110, "three distinct errors accumulate");
        pulse_clr; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0000, "one clear clears all four");

        // ---- THE COLLISION: clear and a new event on the same clock ------
        @(negedge clk) clr = 1'b1; fe_evt = 1'b1;
        @(negedge clk) clr = 1'b0; fe_evt = 1'b0;
        @(negedge clk);
        check(fe_st === 1'b1, "SET-DOMINANT: collision leaves the flag SET");

        // ---- and the same collision on a flag with nothing new -----------
        pulse_pe; @(negedge clk);
        @(negedge clk) clr = 1'b1; fe_evt = 1'b1;
        @(negedge clk) clr = 1'b0; fe_evt = 1'b0;
        @(negedge clk);
        check(fe_st === 1'b1, "collision: the colliding flag stays set");
        check(pe_st === 1'b0, "collision: other flags still clear normally");
        pulse_clr; @(negedge clk);

        // ---- a clear with no event clears cleanly ------------------------
        pulse_bk; @(negedge clk);
        check(bk_st === 1'b1, "break sticky set");
        pulse_clr; @(negedge clk);
        check(bk_st === 1'b0, "clear with no collision clears the flag");

        // ---- reset beats everything --------------------------------------
        pulse_fe; pulse_pe; pulse_ov; pulse_bk; @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b1111, "all four set before reset");
        @(negedge clk) rst_n = 1'b0;
        repeat (2) @(negedge clk);
        check({fe_st,pe_st,ov_st,bk_st} === 4'b0000, "reset clears all sticky flags");
        check(any_err === 1'b0,                      "reset clears any_error");
        @(negedge clk) rst_n = 1'b1;
        @(negedge clk);

        // ---- reset DURING a collision ------------------------------------
        @(negedge clk) rst_n = 1'b0; clr = 1'b1; fe_evt = 1'b1;
        repeat (2) @(negedge clk);
        check(fe_st === 1'b0, "reset wins over a set/clear collision");
        @(negedge clk) rst_n = 1'b1; clr = 1'b0; fe_evt = 1'b0;
        @(negedge clk);

        $display("== %0d checks, %0d failures ==", checks, failures);
        if (failures == 0) $display("   RESULT: ALL SYSTEMVERILOG STATUS TESTS PASSED");
        else               $display("   RESULT: SYSTEMVERILOG STATUS TESTS FAILED");
        $finish;
    end
endmodule

--==========================================================================
--  tb_uart_err_status -- self-checking VHDL-2008 testbench
--  Same 20 checks as the Verilog and SystemVerilog testbenches. The
--  collision case -- clear and a new event on the same clock -- is the one
--  this block exists to get right, so it is tested three different ways.
--==========================================================================
library ieee;
use ieee.std_logic_1164.all;
use std.env.finish;

entity tb_uart_err_status is
end entity tb_uart_err_status;

architecture sim of tb_uart_err_status is
    constant CLK_PERIOD : time := 10 ns;
    signal clk, rst_n, done : std_logic := '0';
    signal fe_evt, pe_evt, ov_evt, bk_evt, clr : std_logic := '0';
    signal fe_st, pe_st, ov_st, bk_st, any_err : std_logic;
begin
    clk <= not clk after CLK_PERIOD / 2 when done = '0' else '0';

    dut : entity work.uart_err_status
        port map (clk => clk, rst_n => rst_n,
                  frame_error_evt_i => fe_evt, parity_error_evt_i => pe_evt,
                  overrun_evt_i => ov_evt, break_evt_i => bk_evt, clear_i => clr,
                  frame_error_sticky_o => fe_st, parity_error_sticky_o => pe_st,
                  overrun_sticky_o => ov_st, break_sticky_o => bk_st,
                  any_error_o => any_err);

    watchdog : process
    begin
        wait for 200 us;
        report "watchdog: simulation did not finish" severity error;
        report "   RESULT: VHDL STATUS TESTS FAILED (timeout)" severity failure;
        wait;
    end process watchdog;

    stim : process
        variable checks, failures : natural := 0;
        procedure check(cond : boolean; name : string) is
        begin
            checks := checks + 1;
            if cond then report "  PASS " & name;
            else failures := failures + 1; report "  FAIL " & name severity error; end if;
        end procedure;
        procedure pulse(signal s : out std_logic) is
        begin
            wait until falling_edge(clk); s <= '1';
            wait until falling_edge(clk); s <= '0';
        end procedure;
        procedure step is begin wait until falling_edge(clk); end procedure;
    begin
        report "== uart_err_status (VHDL) : self-checking testbench ==";

        rst_n <= '0';
        for i in 0 to 3 loop step; end loop;
        check(fe_st = '0' and pe_st = '0' and ov_st = '0' and bk_st = '0',
              "reset: all flags clear");
        check(any_err = '0', "reset: any_error clear");
        rst_n <= '1'; step;

        pulse(fe_evt); step;
        check(fe_st = '1' and pe_st = '0' and ov_st = '0' and bk_st = '0',
              "framing event sets only framing");
        check(any_err = '1', "any_error follows");
        pulse(clr); step;

        pulse(pe_evt); step;
        check(fe_st = '0' and pe_st = '1' and ov_st = '0' and bk_st = '0',
              "parity event sets only parity");
        pulse(clr); step;

        pulse(ov_evt); step;
        check(fe_st = '0' and pe_st = '0' and ov_st = '1' and bk_st = '0',
              "overrun event sets only overrun");
        pulse(clr); step;

        pulse(bk_evt); step;
        check(fe_st = '0' and pe_st = '0' and ov_st = '0' and bk_st = '1',
              "break event sets only break");
        pulse(clr); step;
        check(any_err = '0', "clear drops any_error");

        pulse(fe_evt);
        for i in 0 to 19 loop step; end loop;
        check(fe_st = '1', "sticky: flag survives long after the event");

        pulse(pe_evt); pulse(ov_evt); step;
        check(fe_st = '1' and pe_st = '1' and ov_st = '1' and bk_st = '0',
              "three distinct errors accumulate");
        pulse(clr); step;
        check(fe_st = '0' and pe_st = '0' and ov_st = '0' and bk_st = '0',
              "one clear clears all four");

        -- THE COLLISION
        wait until falling_edge(clk); clr <= '1'; fe_evt <= '1';
        wait until falling_edge(clk); clr <= '0'; fe_evt <= '0';
        step;
        check(fe_st = '1', "SET-DOMINANT: collision leaves the flag SET");

        pulse(pe_evt); step;
        wait until falling_edge(clk); clr <= '1'; fe_evt <= '1';
        wait until falling_edge(clk); clr <= '0'; fe_evt <= '0';
        step;
        check(fe_st = '1', "collision: the colliding flag stays set");
        check(pe_st = '0', "collision: other flags still clear normally");
        pulse(clr); step;

        pulse(bk_evt); step;
        check(bk_st = '1', "break sticky set");
        pulse(clr); step;
        check(bk_st = '0', "clear with no collision clears the flag");

        pulse(fe_evt); pulse(pe_evt); pulse(ov_evt); pulse(bk_evt); step;
        check(fe_st = '1' and pe_st = '1' and ov_st = '1' and bk_st = '1',
              "all four set before reset");
        wait until falling_edge(clk); rst_n <= '0';
        for i in 0 to 1 loop step; end loop;
        check(fe_st = '0' and pe_st = '0' and ov_st = '0' and bk_st = '0',
              "reset clears all sticky flags");
        check(any_err = '0', "reset clears any_error");
        wait until falling_edge(clk); rst_n <= '1'; step;

        wait until falling_edge(clk); rst_n <= '0'; clr <= '1'; fe_evt <= '1';
        for i in 0 to 1 loop step; end loop;
        check(fe_st = '0', "reset wins over a set/clear collision");
        wait until falling_edge(clk); rst_n <= '1'; clr <= '0'; fe_evt <= '0';
        step;

        report "== " & integer'image(checks) & " checks, " &
               integer'image(failures) & " failures ==";
        if failures = 0 then report "   RESULT: ALL VHDL STATUS TESTS PASSED";
        else report "   RESULT: VHDL STATUS TESTS FAILED" severity error; end if;
        done <= '1'; finish;
    end process stim;
end architecture sim;

$ iverilog -g2001 -o sim uart_err_status_v.v tb_uart_err_status_v.v && ./sim
== uart_err_status_v : self-checking Verilog testbench ==
  PASS reset: all flags clear
  PASS framing event sets only framing
  PASS parity event sets only parity
  PASS overrun event sets only overrun
  PASS break event sets only break
  PASS sticky: flag survives long after the event
  PASS three distinct errors accumulate
  PASS one clear clears all four
  PASS SET-DOMINANT: collision leaves the flag SET
  PASS collision: other flags still clear normally
  PASS clear with no collision clears the flag
  PASS reset clears all sticky flags
  PASS reset wins over a set/clear collision
== 20 checks, 0 failures ==
   RESULT: ALL VERILOG STATUS TESTS PASSED

// SET-DOMINANT — the clear is written first, the set after, so the set wins.
if (clear_i)           err_q <= 1'b0;
if (error_event_i)     err_q <= 1'b1;     // later write wins on a collision

// CLEAR-DOMINANT — reverse the order.
if (error_event_i)     err_q <= 1'b1;
if (clear_i)           err_q <= 1'b0;     // later write wins on a collision

  cyc  evt clr  SET-dom  CLEAR-dom
   0    0   0      0         0
   1    1   0      0         0
   2    0   0      1         1      <- both set, one cycle after the event
   3    0   0      1         1
   4    1   1      1         1      <- the collision
   5    0   0      1         0      <- and here the policies diverge
   6    0   0      1         0
   7    0   0      1         0

// Assertion — SET-DOMINANT. A colliding clear must not destroy an event.
// This is the policy of §3 made executable; it fails on a reordering.
property p_set_dominant;
    @(posedge clk) disable iff (!rst_n)
        (clear_i && frame_error_evt_i) |=> frame_error_sticky_o;
endproperty
assert property (p_set_dominant);

// Assertion — a sticky flag never sets without a cause.
property p_sticky_needs_event;
    @(posedge clk) disable iff (!rst_n)
        $rose(frame_error_sticky_o) |-> $past(frame_error_evt_i);
endproperty
assert property (p_sticky_needs_event);

// Assertion — and never clears without a clear or a reset.
property p_sticky_holds;
    @(posedge clk) disable iff (!rst_n)
        $fell(frame_error_sticky_o) |-> $past(clear_i);
endproperty
assert property (p_sticky_holds);

// Assertion — the aggregate is exactly the OR of its inputs.
property p_any_error_is_or;
    @(posedge clk) disable iff (!rst_n)
        any_error_o == (frame_error_sticky_o | parity_error_sticky_o
                      | overrun_sticky_o     | break_sticky_o);
endproperty
assert property (p_any_error_is_or);

// Conceptual SystemVerilog — recovery as a gate on start acceptance,
// not as new states inside the receive FSM. Chapter 6.1 §3's argument:
// the frame's state graph must not depend on line history.
//
// The receiver of Module 6 is unchanged; this qualifies its input.
assign may_accept_start = start_cand_i
                        && !break_active_o        // not during a break
                        && (!recovery_armed_q || line_idle_o);

// Published as SystemVerilog Assertions. Icarus Verilog 13.0 supports
// neither named properties nor $past, so what was EXECUTED is the
// procedural equivalent inside each testbench; both forms are shown so the
// intent is portable and the evidence is real.

// p_event_is_one_cycle -- catches an error "event" that is really a level.
// A held event double-counts in any consumer that edge-detects it, and the
// symptom is an error rate that scales with how long the frame took.
property p_event_is_one_cycle;
    @(posedge clk) disable iff (!rst_n) frame_error_evt_o |=> !frame_error_evt_o;
endproperty

// p_event_only_at_sample -- catches a verdict latched at the wrong instant.
// The design still reports the right answer for every frame; only the
// TIMING is wrong, and nothing downstream notices until something else
// starts depending on the sample point.
property p_event_only_at_sample;
    @(posedge clk) disable iff (!rst_n) frame_error_evt_o |-> sample_stop_i;
endproperty

// p_sticky_holds -- catches a flag that decays. A status bit that clears
// itself loses the only record of a condition that has already passed.
property p_sticky_holds;
    @(posedge clk) disable iff (!rst_n)
        (frame_error_sticky_o && !clear_i) |=> frame_error_sticky_o;
endproperty

// p_set_dominant -- catches the collision policy being inverted. This is
// the property that two checks in twenty catch, and nothing else does.
property p_set_dominant;
    @(posedge clk) disable iff (!rst_n)
        (clear_i && frame_error_evt_i) |=> frame_error_sticky_o;
endproperty

// p_break_declared_once -- catches a wrapping break counter. See 9.4's
// callout: this property is protected by TWO mechanisms, and the assertion
// is what makes the protection explicit rather than incidental.
property p_break_declared_once;
    @(posedge clk) disable iff (!rst_n) break_evt_o |-> !break_active_o;
endproperty

// p_idle_needs_mark -- catches idle asserted on a line that is not at mark.
// The negative property; no positive test reaches it.
property p_idle_needs_mark;
    @(posedge clk) disable iff (!rst_n) line_idle_o |-> rx_sync_i;
endproperty