Packaging Fundamentals

Every chapter of this module has leaned on the same unexamined assumption. Compute dies "connect to" a system die. Memory is "reached through" a controller. An accelerator's operands "cross a boundary". Each of those phrases describes something physical that has to exist — actual conductors, running an actual distance, through an actual structure — and so far that structure has been a word. This chapter is about the thing doing the connecting, and the reason it needs a chapter of its own is that in a chiplet system it stops being a passive component and becomes an architectural resource you can run out of.

1. The Package Stopped Being a Container

For a monolithic die, the package's job is easy to state: protect the silicon, get its signals out to the board, deliver power in, and conduct heat away. Nothing about the chip's internal architecture depends on it. A different package might change cost or thermal headroom, but the design inside is unaffected because every internal connection is on the die.

Partition that die and the situation inverts. Connections that used to be on-die metal now have to be carried by something outside the die — and the only thing between two dies in a package is the package. Its routing capability therefore sets how many signals can cross between any two dies, how far apart they can sit, how fast those connections can run, and how much energy each transfer costs.

In a chiplet system the package is not a container. It is the physical interconnect fabric, and it simultaneously carries signals, delivers power, and conducts heat.

That is the mental shift, and it has a practical consequence worth stating immediately: the package can make an architecture impossible. Not expensive, not slower — unbuildable, because the connections the partition requires cannot be physically routed between the positions the dies must occupy.

2. The Physical Hierarchy

Before the taxonomy, get the spatial picture right, because most confusion here is people picturing the wrong stack.

Working outward from the silicon:

• The die itself, with its own on-die metal layers — the densest, shortest, cheapest wiring available anywhere in the system.
• Bumps on the die's surface, which are how it connects to whatever it sits on. Connections intended for die-to-die traffic generally use much finer, more numerous micro-bumps; connections carrying power and board-bound signals use coarser, sparser bumps. Finer pitch means more connections in the same edge or area, which is exactly the currency die-to-die interfaces spend.
• A die-to-die routing structure where high-density connection is needed — an interposer or a bridge (§4 and §5).
• The package substrate, which routes between dies at moderate density, distributes power, and brings signals out to the package's external connections.
• The PCB, the system board the package is mounted on.

Two things to notice. The wiring gets coarser and longer at every step outward — on-die metal is finer than anything in the package, which is finer than the board. And the structures serve different jobs: some exist to connect dies to each other, others to connect dies to the outside world. Conflating those two jobs is the single most common error in this subject, which is why §6 is dedicated to it.

3. Organic Substrate

The conventional package substrate is built from organic laminate materials — layered dielectric with patterned copper, conceptually similar in construction to a very fine printed circuit board.

Its properties, at the level an architect needs:

• It is the lower-cost class of package routing, and it is mature, high-volume manufacturing.
• Its routing is coarser than what can be patterned in silicon. Feature sizes and layer-to-layer alignment achievable in organic laminate are considerably less fine than a silicon process, so a given area supports far fewer connections.
• It can span the whole package and reach the external connections, which the denser silicon structures generally cannot.
• It carries power, which is a substantial part of its job and competes with signal routing for layers and space.

So an organic substrate is entirely adequate for moderate connection density — and it is what every package needs regardless, because something has to deliver power and reach the board. What it struggles with is a die-to-die interface wanting a very large number of connections across a short distance. That is the gap the silicon structures fill.

4. Silicon Interposer

A silicon interposer is a piece of silicon that dies are mounted on, which routes between them using silicon-process wiring rather than laminate.

The reason to do this follows directly from §3: because it is patterned with semiconductor lithography, an interposer supports much denser wiring than organic laminate, and therefore far more connections between two dies in a given amount of space. That is what makes very wide die-to-die interfaces practical — thousands of short parallel connections instead of a smaller number of faster serial ones.

Two structural points matter architecturally:

• The dies sit on the interposer, and the interposer sits on the substrate. Signals that need to leave the package pass through the interposer to the substrate below via vertical connections through the silicon. This is the arrangement usually described as 2.5D integration — several dies side by side on a shared routing layer, as distinct from stacking dies directly on top of one another.
• It is a large piece of silicon. An interposer big enough to host several dies is itself a sizeable die, with the cost, yield, and (as Chapter 1.2 established) reticle-field consequences that implies. A routing structure has to be manufactured like anything else.

That last point is the honest cost, and it is why the third option exists.

5. Silicon Bridge

A silicon bridge applies the interposer's insight selectively. Instead of mounting everything on one large silicon routing layer, a small piece of silicon is embedded in the substrate only where two dies need to talk densely — spanning the gap at their shared edge.

The dies then sit on the substrate as usual, with the bridge beneath the region where they meet. Dense die-to-die connections use the bridge; power and board-bound signals use the substrate directly.

The reasoning is straightforwardly economic and physical: dense routing is only needed where two dies actually interface, which is a small fraction of the package area. Paying for a large interposer to serve a few narrow interface regions is buying silicon that mostly routes nothing. A bridge provides local high density without making the whole package a silicon substrate.

Intel's EMIB (Embedded Multi-die Interconnect Bridge) is the best-known implementation of this approach — a silicon bridge embedded in the package substrate, connected to the dies with micro-bumps, providing high-density interconnect locally between adjacent dies. The name is worth knowing because it is the term you will meet; treat it as the reference example of the category. The detailed comparison of packaging technologies belongs to the later packaging module, not here.

6. Substrate and Interposer Are Not the Same Thing — and Not Alternatives

This distinction is worth being pedantic about, because the terms are used loosely and the loose usage hides an architectural fact.

They coexist. An interposer does not replace the substrate: the package still needs power delivered and signals brought out to the board, and a silicon routing layer between dies does neither of those things. A package using an interposer or bridge has both, doing different jobs.

Getting this wrong leads directly to a bad instinct — "use an interposer and routing stops being a constraint". It does not. It raises the ceiling on die-to-die connection density in the regions it covers, while power delivery, board escape, thermal behaviour, and the physical arrangement of the dies all remain exactly as constraining as before.

7. The Package Prices Every Boundary

Now connect this to everything the module has argued. A die boundary is only real if the package can carry what crosses it — and "what crosses it" is more than data signals:

• The number of connections the interface needs, which must fit in the available routing and, critically, along the die edge where the interface sits. Edge length is finite, and every interface competes for it.
• The distance those connections must run, which depends on where the dies can physically be placed.
• Clocks and any sideband or control signals, which need their own connections and often have their own integrity requirements.
• Power for every die, delivered through the same structure that is routing all of this.

Which means the package directly determines achievable interface width, bandwidth density, the energy cost per transfer, latency across the boundary, and ultimately whether the routing closes at all. Chapter 2.4 said memory architecture and package architecture are one problem; the general statement is that any die-to-die architecture and package architecture are one problem.

8. Reach and Density Pull Against Each Other

One model here is worth carrying permanently, because it explains an assumption the UCIe chapters will later rely on:

High-density interconnect is easiest over short distances.

As two dies move farther apart, several things get harder at once. The routing has to traverse more structure, so it consumes more package resource and competes with everything else needing to pass through the same region. Signal integrity degrades over distance, which constrains how fast each connection can run or forces more elaborate circuitry at the ends. And keeping a very large number of connections well matched over a longer run is harder than over a short one.

The practical consequence: the highest-density interfaces are for immediate neighbours. A die that must exchange enormous traffic with another die needs to be placed next to it — which turns interface bandwidth into a placement constraint, and placement into an architectural one. You cannot give every die a wide, fast connection to every other die, because they cannot all be adjacent.

This is also why die-to-die interface standards are specified against assumptions about channel reach. An interface designed for a short, dense, silicon-routed channel and one designed to cross a longer organic path are solving measurably different physical problems.

9. Routing, Power, and Heat Share One Structure

The package is not three independent designs that happen to occupy the same space. It is one structure asked to do three things, and they compete.

Power delivery. Every die needs current supplied with acceptable voltage stability, which requires conductor cross-section, return paths, and decoupling placed close enough to be effective. All of that consumes layers, area, and via space — the same resources signal routing wants.

Thermal conduction. Heat generated in each die has to reach a cooling solution. That path runs through the package, so package structure and die placement determine how effectively each die is cooled and how much neighbouring dies affect each other. Chapter 2.4 noted this for memory specifically; it applies to every die.

Signal routing. Everything in §7 and §8.

A package floorplan is simultaneously a signal-routing plan, a power-delivery plan, and a thermal plan — and improving one usually costs something in the others.

Moving two dies closer improves their interface and worsens their thermal interaction. Adding routing layers for signals adds cost and can complicate the power and thermal path. Spreading dies out for cooling lengthens every connection between them. There is no arrangement that optimises all three, which is exactly why package design is an engineering discipline rather than a layout step.

10. "Just Add Another Chiplet" — Why It Fails Physically

Make this concrete, because it is the moment the abstraction becomes real.

An architect has a system with three compute dies and a system die. Performance targets rise, and the logical answer is obvious: add a fourth compute die. The block diagram change is trivial — one more box, one more link into the system die. Chapter 2.2 even established that replication is the point of the partition.

Now ask the package:

• Is there a routing path? The fourth die needs its interface routed to the system die. If the three existing links already consume the available corridors into that die's region, there may be nowhere for a fourth to go.
• Is there die edge left? The system die's interfaces occupy its perimeter. A fourth interface needs edge space, and edge is finite regardless of how much area the die has.
• Is there physical area, at usable reach? The fourth die must sit somewhere close enough for its interface to work at the intended rate (§8). "Somewhere in the package" is not the same as "adjacent to the system die".
• Can power be delivered? Another die is another current demand through the same structure.
• Can the heat get out? Another heat source in the same thermal envelope, possibly worsening its neighbours.

Any one of those can be the binding constraint, and none of them is visible in the logical diagram.

Logical composability is limited by physical package feasibility.

Which is precisely why the next chapter treats package feasibility as one axis of the partitioning decision rather than as a check performed after the partition is chosen.

11. What This Means for Digital Design and Verification

Package constraints do not stay in the package. They arrive in the RTL as fixed assumptions:

• Maximum interface width is set by available connections and die edge — so the interface's width, and therefore its bandwidth at a given rate, is a package-derived number the logic must live within.
• Link topology follows from which dies can physically be adjacent. If two dies cannot be neighbours, traffic between them routes through a third, and that hop is now in the architecture.
• Chiplet adjacency constrains which functions can afford to talk heavily to which others.
• Latency assumptions baked into the design depend on physical distance and the number of hops.
• Redundancy and degraded operation may be required because physical connections can fail, so the design may need to work with fewer usable connections than nominal.
• Topology configuration must be discoverable and handled, since one design may ship in several package arrangements.

For verification, the consequence is that the physical arrangement is part of the test space. A design intended for several package configurations must be verified across them: different numbers of dies populated, different interface widths, degraded configurations where some connections are unusable, and arrangements where an expected die is absent. Those are not exotic corner cases — they are the supported product matrix, and they exist because packaging made them possible.

12. Common Misconceptions

13. Understanding Check

14. Summary and What Comes Next

For a monolithic die the package protects silicon and escapes signals. For a chiplet system it is the interconnect fabric, and it does three competing jobs at once: routing signals, delivering power, and conducting heat.

The taxonomy is three structures with two distinct roles. The organic substrate — lower-cost, moderate density, spanning the package — routes to the outside world and delivers power, and every package has one. A silicon interposer hosts dies on a silicon routing layer, giving much higher die-to-die density at the cost of being a large die itself. A silicon bridge embeds that density only where two dies meet, avoiding a package-wide silicon layer. Substrate and interposer are not alternatives — the dense structures raise die-to-die density; they never remove the substrate's jobs.

Two models carry forward. Reach and density pull against each other, so the widest interfaces belong to immediate neighbours, which makes bandwidth a placement question. And logical composability is limited by physical feasibility — adding a die can fail on routing corridors, die edge, usable placement, power delivery, or cooling while area is still free.

Which sets up the hardest question in chiplet architecture. Every boundary now has a known physical price:

• 2.7 — System Partitioning — given that each die boundary consumes real package resources and creates a real contract, where should the boundaries be at all?

Browse the full path on the UCIe tutorials index.