Routing — How a Switch Decides Which Port a Packet Leaves By

                    upstream port
                 (virtual P2P bridge)
                          │
                 ─────────┴─────────  internal virtual PCI bus
                    │     │     │
                   P2P   P2P   P2P     downstream ports
                    │     │     │       (virtual P2P bridges)

downstream   if the address falls within a downstream bridge's Base..Limit window
upstream     if it does not fall within the upstream bridge's window

Secondary Bus Number    the bus immediately below this bridge
Subordinate Bus Number  the highest bus number reachable below it

target Bus == this port's Secondary Bus Number
        →  CONVERT the Type 1 Request into a Type 0 Request
           (the target is ON the bus directly below this bridge)
 
Secondary < target Bus ≤ Subordinate
        →  FORWARD the Type 1 Request unchanged
           (the target is further down; some bridge below will convert it)
 
anything else
        →  UNSUPPORTED REQUEST

// SYNTHESIZABLE. Normalized switch-routing types.
// THE ROUTING METHODS are canonical (§3, §1's three CAMs). The struct
// layouts and widths here are internal; no TLP header encoding is
// published in this chapter.
package switch_route_pkg;
 
  parameter int N_DOWN = 4;                       // downstream ports
  parameter int PW = (N_DOWN <= 1) ? 1 : $clog2(N_DOWN);
 
  typedef enum logic [1:0] {
    RM_ADDRESS  = 2'd0,   // Memory / I/O Requests      -> AMCAM / IOAMCAM
    RM_ID       = 2'd1,   // Completions, Config        -> BusNoCAM
    RM_IMPLICIT = 2'd2    // certain Messages           -> by TLP type
  } route_method_e;
 
  typedef enum logic [2:0] {
    TT_MEM_REQ = 3'd0, TT_IO_REQ = 3'd1, TT_CFG0 = 3'd2,
    TT_CFG1    = 3'd3, TT_CPL    = 3'd4, TT_MSG  = 3'd5
  } tlp_kind_e;
 
  // Per-port window set. Section 1: "each downstream bridge has its own
  // Base and Limit", and there are separate non-prefetchable and
  // prefetchable Memory windows plus an I/O window.
  typedef struct packed {
    logic [63:0] mem_base,  mem_limit;
    logic [63:0] pref_base, pref_limit;
    logic [31:0] io_base,   io_limit;
    logic [7:0]  sec_bus,   sub_bus;      // ID routing (§5)
  } port_cfg_t;
 
  // ==================================================================
  // A WINDOW IS ENABLED ONLY WHEN Base <= Limit.
  //
  // Section 1: "when the Base is less than or equal to the Limit".
  // Section 12 measured the alternative -- treating Base > Limit as a
  // WRAPPED range -- at 33.3% spurious matches, so a disabled window
  // would capture a third of all traffic.
  // ==================================================================
  function automatic bit win_hit(input logic [63:0] base,
                                 input logic [63:0] limit,
                                 input logic [63:0] addr);
    return (base <= limit) && (addr >= base) && (addr <= limit);
  endfunction
 
  // Section 1: "If the Bus Number is in the Secondary or Subordinate
  // range, the packet goes downstream; otherwise, the packet goes
  // upstream." Note the range is INCLUSIVE at both ends.
  function automatic bit bus_hit(input logic [7:0] sec,
                                 input logic [7:0] sub,
                                 input logic [7:0] bus);
    return (bus >= sec) && (bus <= sub);
  endfunction
 
endpackage

import switch_route_pkg::*;
 
// SYNTHESIZABLE. Address routing -- section 1's AMCAM / IOAMCAM.
// THREE OUTCOMES, never a priority encode (§8). Section 12 measured
// randomized configurations: 26.1% one match, 67.3% NO match (upstream by
// default), 6.6% MORE THAN ONE -- and the last is a misconfiguration that
// a priority encoder would answer silently.
module route_address (
  input  port_cfg_t [N_DOWN-1:0] cfg,
  input  logic                   port_enabled [N_DOWN],
  input  tlp_kind_e              kind,
  input  logic [63:0]            addr,
 
  output logic [N_DOWN-1:0] match_vec,
  output logic              hit_down,
  output logic              route_upstream,
  output logic              ambiguous,
  output logic [PW-1:0]     egress
);
  wire is_mem = (kind == TT_MEM_REQ);
  wire is_io  = (kind == TT_IO_REQ);
 
  always_comb begin
    for (int i = 0; i < N_DOWN; i++) begin
      match_vec[i] = port_enabled[i] && (
          (is_mem && (win_hit(cfg[i].mem_base,  cfg[i].mem_limit,  addr)
                   || win_hit(cfg[i].pref_base, cfg[i].pref_limit, addr)))
       || (is_io  &&  win_hit({32'd0, cfg[i].io_base},
                              {32'd0, cfg[i].io_limit}, addr)));
    end
  end
 
  // ==================================================================
  // NO MATCH IS AN ANSWER, NOT AN ERROR (§4).
  //
  // Section 1: "The Request goes upstream if it does not target anything
  // within the upstream bridge's Base and Limit range." A bridge knows
  // only what is BELOW it; anything else is somebody else's problem.
  // Section 12: this is the majority path at 67.3%.
  // ==================================================================
  assign hit_down       = (is_mem || is_io) && $onehot(match_vec);
  assign route_upstream = (is_mem || is_io) && (match_vec == '0);
  assign ambiguous      = (is_mem || is_io) && !$onehot0(match_vec);
 
  // Meaningful ONLY on hit_down -- an ambiguous vector must not produce a
  // plausible index that downstream logic might use anyway.
  always_comb begin
    egress = '0;
    if (hit_down)
      for (int i = 0; i < N_DOWN; i++) if (match_vec[i]) egress = PW'(i);
  end
endmodule

import switch_route_pkg::*;
 
// SYNTHESIZABLE. ID routing -- section 1's BusNoCAM.
// Same three-outcome shape, different registers: Secondary and
// Subordinate Bus Number rather than Base and Limit (§5).
module route_id (
  input  port_cfg_t [N_DOWN-1:0] cfg,
  input  logic                   port_enabled [N_DOWN],
  input  logic [7:0]             target_bus,
 
  output logic [N_DOWN-1:0] match_vec,
  output logic              hit_down,
  output logic              route_upstream,
  output logic              ambiguous,
  output logic [PW-1:0]     egress
);
  always_comb
    for (int i = 0; i < N_DOWN; i++)
      match_vec[i] = port_enabled[i]
                  && bus_hit(cfg[i].sec_bus, cfg[i].sub_bus, target_bus);
 
  assign hit_down       = $onehot(match_vec);
  assign route_upstream = (match_vec == '0);      // §1: "otherwise... upstream"
  assign ambiguous      = !$onehot0(match_vec);
 
  always_comb begin
    egress = '0;
    if (hit_down)
      for (int i = 0; i < N_DOWN; i++) if (match_vec[i]) egress = PW'(i);
  end
  // Section 12: with properly nested ranges, 0 ambiguity across 200,000
  // lookups. With deliberately overlapping ranges (1-5 and 3-8), 29.9%.
endmodule

import switch_route_pkg::*;
 
// SYNTHESIZABLE. Section 1's three-way Configuration Request rule.
// This is the most precisely sourced decision in the chapter, and the
// boundaries matter: section 12 walked them.
module route_config (
  input  tlp_kind_e   kind,
  input  logic [7:0]  target_bus,
  input  logic [7:0]  this_sec_bus,      // this bridge's Secondary
  input  logic [7:0]  this_sub_bus,      // this bridge's Subordinate
 
  output logic convert_to_type0,
  output logic forward_type1,
  output logic unsupported_request
);
  wire is_cfg1 = (kind == TT_CFG1);
 
  // ==================================================================
  // EXACTLY AT THE SECONDARY BUS NUMBER -> CONVERT.
  //
  // Section 1: "If the Configuration Request matches the ... downstream
  // port Secondary Bus Number, the [switch] converts the Type 1
  // Configuration Request into a Type 0 Configuration Request."
  //
  // Type 0 means "you are the target", and only devices on the
  // immediately-adjacent bus are. Converting across the whole range
  // would address the wrong devices entirely (§13, mutation 6).
  // ==================================================================
  assign convert_to_type0 = is_cfg1 && (target_bus == this_sec_bus);
 
  // Section 1: "if the Bus Number does not match the Secondary Bus
  // Number, but falls within the Subordinate Bus Number range, the
  // Type 1 Configuration Request is forwarded ... unchanged."
  assign forward_type1    = is_cfg1 && (target_bus > this_sec_bus)
                                    && (target_bus <= this_sub_bus);
 
  // Section 1: "A Type 1 Configuration Request that targets a Bus Number
  // that is not within range is invalid, and is terminated ... as an
  // Unsupported Request (UR)."
  //
  // A DEFINED RESPONSE, not a drop -- which is what lets enumeration
  // discover the hierarchy by probing (§6).
  assign unsupported_request = is_cfg1 && !convert_to_type0 && !forward_type1;
endmodule

import switch_route_pkg::*;
 
// SYNTHESIZABLE. Combine the three methods into ONE egress decision.
// Exactly one lookup is consulted per packet, chosen by TLP type (§3).
module egress_resolver (
  input  tlp_kind_e     kind,
 
  input  logic          addr_hit,  addr_up,  addr_amb,
  input  logic [PW-1:0] addr_port,
  input  logic          id_hit,    id_up,    id_amb,
  input  logic [PW-1:0] id_port,
 
  // Implicit: section 1 states PM_PME "always routed toward the Root
  // Complex". No window is consulted; the TLP type IS the routing
  // information (§7).
  input  logic          msg_toward_root,
 
  output route_method_e method,
  output logic          egress_valid,
  output logic          egress_upstream,
  output logic [PW-1:0] egress_port,
  output logic          err_ambiguous,
  output logic          err_no_route
);
  always_comb begin
    method          = RM_ADDRESS;
    egress_valid    = 1'b0;
    egress_upstream = 1'b0;
    egress_port     = '0;
    err_ambiguous   = 1'b0;
    err_no_route    = 1'b0;
 
    unique case (kind)
      TT_MEM_REQ, TT_IO_REQ : begin
        method          = RM_ADDRESS;
        egress_valid    = addr_hit;
        egress_port     = addr_port;
        egress_upstream = addr_up;        // §4's default, NOT an error
        err_ambiguous   = addr_amb;
      end
 
      TT_CPL, TT_CFG1 : begin
        method          = RM_ID;
        egress_valid    = id_hit;
        egress_port     = id_port;
        egress_upstream = id_up;
        err_ambiguous   = id_amb;
      end
 
      TT_MSG : begin
        method          = RM_IMPLICIT;
        // No lookup, no comparison -- the type decides.
        egress_upstream = msg_toward_root;
        egress_valid    = !msg_toward_root;
        err_no_route    = 1'b0;
      end
 
      // A Type 0 Configuration Request targets THIS bridge's own
      // registers; it is not forwarded anywhere (§2).
      TT_CFG0 : begin
        method       = RM_ID;
        egress_valid = 1'b0;
        egress_upstream = 1'b0;
      end
 
      default : err_no_route = 1'b1;
    endcase
  end
  // INVARIANT (§8): at most one of {egress_valid, egress_upstream,
  // err_ambiguous} is ever true. P7 asserts it.
endmodule

// SVA over the routing blocks. LOCAL contract only. Nothing asserts that
// software configures the windows correctly, that a downstream port
// accepts, or that any packet is ever delivered.
 
// ---- WINDOW SEMANTICS -------------------------------------------------
 
// P1: A WINDOW WITH Base > Limit IS DISABLED, not wrapped. Section 12
// measured the wrap interpretation at 33.3% spurious matches.
property p_disabled_window;
  @(posedge clk) disable iff (!rst_n)
  (cfg[i].mem_base > cfg[i].mem_limit) |-> !addr_match_mem[i];
endproperty
a_dis : assert property (p_disabled_window);
 
// P2: a match means the address really is inside an enabled window.
property p_match_sound;
  @(posedge clk) disable iff (!rst_n)
  match_vec[i] |-> (win_hit(cfg[i].mem_base,  cfg[i].mem_limit,  addr)
                 || win_hit(cfg[i].pref_base, cfg[i].pref_limit, addr)
                 || win_hit({32'd0,cfg[i].io_base}, {32'd0,cfg[i].io_limit}, addr));
endproperty
a_sound : assert property (p_match_sound);
 
// P2b: BOTH memory windows participate -- ignoring the prefetchable range
// misroutes half the address map (mutation 5).
property p_pref_window_used;
  @(posedge clk) disable iff (!rst_n)
  (win_hit(cfg[i].pref_base, cfg[i].pref_limit, addr) && port_enabled[i]
                                                     && (kind == TT_MEM_REQ))
    |-> match_vec[i];
endproperty
a_pref : assert property (p_pref_window_used);
 
// ---- THE THREE OUTCOMES -----------------------------------------------
 
// P3: NO MATCH ROUTES UPSTREAM. Section 1's default, and section 12's
// majority path at 67.3% -- it must never be an error.
property p_miss_is_upstream;
  @(posedge clk) disable iff (!rst_n)
  ((kind inside {TT_MEM_REQ, TT_IO_REQ}) && (match_vec == '0))
    |-> (route_upstream && !err_no_route);
endproperty
a_up : assert property (p_miss_is_upstream);
 
// P4: MORE THAN ONE MATCH IS REPORTED, NOT RESOLVED. Section 12: 29.9%
// against deliberately overlapping ranges.
property p_ambiguity_reported;
  @(posedge clk) disable iff (!rst_n)
  !$onehot0(match_vec) |-> (ambiguous && !hit_down);
endproperty
a_amb : assert property (p_ambiguity_reported);
 
// P5: a downstream route implies exactly one match, and the index is in
// range and actually set.
property p_onehot_egress;
  @(posedge clk) disable iff (!rst_n)
  hit_down |-> ($onehot(match_vec) && (egress < PW'(N_DOWN))
                                   && match_vec[egress]);
endproperty
a_one : assert property (p_onehot_egress);
 
// ---- ID ROUTING -------------------------------------------------------
 
// P6: the bus range is INCLUSIVE at both ends (§1, §5).
property p_bus_range_inclusive;
  @(posedge clk) disable iff (!rst_n)
  ((target_bus == cfg[i].sec_bus) || (target_bus == cfg[i].sub_bus))
    && port_enabled[i] |-> id_match_vec[i];
endproperty
a_incl : assert property (p_bus_range_inclusive);
 
// ---- RESOLUTION -------------------------------------------------------
 
// P7: AT MOST ONE OUTCOME. valid, upstream and ambiguous are mutually
// exclusive -- the resolver's core invariant (§11).
property p_exclusive_outcome;
  @(posedge clk) disable iff (!rst_n)
  $onehot0({egress_valid, egress_upstream, err_ambiguous});
endproperty
a_excl : assert property (p_exclusive_outcome);
 
// P8: THE METHOD IS CHOSEN BY TLP TYPE, and only that method's result is
// used (§3).
property p_method_by_type;
  @(posedge clk) disable iff (!rst_n)
  ((kind inside {TT_MEM_REQ, TT_IO_REQ}) |-> (method == RM_ADDRESS))
  && ((kind inside {TT_CPL, TT_CFG1})    |-> (method == RM_ID))
  && ((kind == TT_MSG)                   |-> (method == RM_IMPLICIT));
endproperty
a_meth : assert property (p_method_by_type);
 
// P8b: an implicitly-routed Message consults NO window (§7).
property p_implicit_no_lookup;
  @(posedge clk) disable iff (!rst_n)
  (kind == TT_MSG) |-> (!err_ambiguous && (egress_upstream == msg_toward_root));
endproperty
a_imp : assert property (p_implicit_no_lookup);
 
// ---- CONFIGURATION REQUESTS -------------------------------------------
 
// P9: THE THREE OUTCOMES ARE MUTUALLY EXCLUSIVE AND EXHAUSTIVE for a
// Type 1 Configuration Request (§6).
property p_cfg_exclusive;
  @(posedge clk) disable iff (!rst_n)
  (kind == TT_CFG1) |-> $onehot({convert_to_type0, forward_type1,
                                 unsupported_request});
endproperty
a_cfg : assert property (p_cfg_exclusive);
 
// P10: CONVERSION HAPPENS EXACTLY AT THE SECONDARY BUS NUMBER -- not
// across the range (mutation 6).
property p_convert_exact;
  @(posedge clk) disable iff (!rst_n)
  convert_to_type0 |-> (target_bus == this_sec_bus);
endproperty
a_conv : assert property (p_convert_exact);
 
// P10b: forwarding is strictly ABOVE the Secondary and at most the
// Subordinate -- so the two never both fire (mutation 7).
property p_forward_range;
  @(posedge clk) disable iff (!rst_n)
  forward_type1 |-> ((target_bus > this_sec_bus) && (target_bus <= this_sub_bus));
endproperty
a_fwd : assert property (p_forward_range);
 
// P11: AN OUT-OF-RANGE CONFIGURATION REQUEST IS TERMINATED, NOT DROPPED.
// Section 1: "terminated ... as an Unsupported Request (UR)". Enumeration
// depends on getting a response (§6).
property p_ur_not_dropped;
  @(posedge clk) disable iff (!rst_n)
  ((kind == TT_CFG1) && (target_bus != this_sec_bus)
                     && !((target_bus > this_sec_bus) && (target_bus <= this_sub_bus)))
    |-> unsupported_request;
endproperty
a_ur : assert property (p_ur_not_dropped);
 
// P12: a Type 0 Configuration Request is NOT forwarded -- it targets this
// bridge's own registers (§2).
property p_type0_not_forwarded;
  @(posedge clk) disable iff (!rst_n)
  (kind == TT_CFG0) |-> (!egress_valid && !egress_upstream);
endproperty
a_t0 : assert property (p_type0_not_forwarded);
 
// P13: routing is COMBINATIONAL and stateless here -- the same inputs
// always give the same egress. Any future pipelining must snapshot the
// configuration, which is Chapter 19.4 P5's rule.
property p_deterministic;
  @(posedge clk) disable iff (!rst_n)
  ($stable(kind) && $stable(addr) && $stable(target_bus) && $stable(cfg))
    |-> $stable({egress_valid, egress_upstream, egress_port});
endproperty
a_det : assert property (p_deterministic);
 
// P14: reset leaves no route asserted.
property p_reset;
  @(posedge clk) !rst_n |=> (!egress_valid && !err_ambiguous);
endproperty
a_reset : assert property (p_reset);