189Total chapters
31Modules
189Chapters live
31 / 31Active modules
Architecture before lanes
Why shared buses stopped scaling and why a switched serial fabric won — the root complex, endpoints, switches, and layered stack come before lanes and speeds.
Interview-ready depth
A leveled interview module plus per-chapter interview weighting — enumeration, BARs, TLPs, flow control, LTSSM, MSI-X, and the misconceptions that trip candidates.
Design → verify → debug
Endpoint RTL (BAR logic, DMA engines, TLP generation), a layered UVM environment, and protocol-analyzer debugging for enumeration, link-training, and credit deadlocks.
PCI Express Complete Curriculum
Your Learning Roadmap
189 chapters · 31 modules — root complex, endpoints, TLPs, LTSSM, and DMA — architecture to verification.
189of 189 chapters live
100% complete
Module 1
Why PCIe Exists
Module 2
PCIe Architecture Overview
Module 3
PCIe Layered Architecture
Module 4
PCIe Topology
Module 5
PCIe Generations
Module 6
Lanes and Link Widths
Module 7
PCIe Enumeration
Module 8
Configuration Space
Module 9
Base Address Registers (BARs)
Module 10
Transaction Layer Overview
Module 11
Transaction Layer Packets (TLPs)
Module 12
Memory Transactions
Module 13
Completion Packets
Module 14
Data Link Layer
Module 15
DLLPs
Module 16
Flow Control
Module 17
Physical Layer
Module 18
LTSSM
Module 19
PCIe Interrupts
Module 20
DMA over PCIe
Module 21
PCIe Switches
Module 22
PCIe Performance
Module 23
PCIe RTL Design
Module 24
PCIe Verification
Module 25
PCIe Debugging
Module 26
PCIe in SoCs and Systems
Module 27
PCIe Interview Mastery
Module 28
PCIe vs Other Interconnects
Module 29
Real Industry Case Studies
Module 30
PCIe Design Review Checklist