189Total chapters
31Modules
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Architecture before lanes
Why shared buses stopped scaling and why a switched serial fabric won — the root complex, endpoints, switches, and layered stack come before lanes and speeds.
Interview-ready depth
A leveled interview module plus per-chapter interview weighting — enumeration, BARs, TLPs, flow control, LTSSM, MSI-X, and the misconceptions that trip candidates.
Design → verify → debug
Endpoint RTL (BAR logic, DMA engines, TLP generation), a layered UVM environment, and protocol-analyzer debugging for enumeration, link-training, and credit deadlocks.
PCI Express Complete Curriculum
Your Learning Roadmap
189 chapters · 31 modules — root complex, endpoints, TLPs, LTSSM, and DMA — architecture to verification.
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Module 1
Why PCIe Exists
1.1Evolution of System InterconnectsPlanned1.2ISAPlanned1.3PCIPlanned1.4AGPPlanned1.5PCI LimitationsPlanned1.6Shared Bus ProblemsPlanned1.7Scalability ChallengesPlanned1.8The Emergence of PCIePlanned
Module 2
PCIe Architecture Overview
2.1PCIe Architecture OverviewPlanned2.2Root ComplexPlanned2.3EndpointPlanned2.4SwitchPlanned2.5BridgePlanned2.6Hierarchy DomainsPlanned2.7The PCIe FabricPlanned2.8Point-to-Point LinksPlanned2.9Switched ArchitecturePlanned
Module 3
PCIe Layered Architecture
3.1Transaction LayerPlanned3.2Data Link LayerPlanned3.3Physical LayerPlanned3.4Layer ResponsibilitiesPlanned3.5Layer InteractionsPlanned
Module 4
PCIe Topology
4.1Root Complex TopologyPlanned4.2EndpointsPlanned4.3SwitchesPlanned4.4Multi-Level FabricsPlanned4.5Real System ExamplesPlanned
Module 5
PCIe Generations
5.1PCIe Gen1 (2.5 GT/s)Planned5.2PCIe Gen2 (5 GT/s)Planned5.3PCIe Gen3 (8 GT/s)Planned5.4PCIe Gen4 (16 GT/s)Planned5.5PCIe Gen5 (32 GT/s)Planned5.6PCIe Gen6 (64 GT/s, PAM4)Planned
Module 6
Lanes and Link Widths
6.1x1 LinksPlanned6.2x2 LinksPlanned6.3x4 LinksPlanned6.4x8 LinksPlanned6.5x16 LinksPlanned6.6Lane AggregationPlanned6.7Throughput CalculationsPlanned6.8Real System Trade-offsPlanned
Module 7
PCIe Enumeration
7.1Enumeration OverviewPlanned7.2Power-UpPlanned7.3Device DiscoveryPlanned7.4Bus Number AssignmentPlanned7.5Device Number AssignmentPlanned7.6Function Number AssignmentPlanned7.7Configuration AccessPlanned7.8Resource AllocationPlanned
Module 8
Configuration Space
8.1Configuration MechanismPlanned8.2Device IDsPlanned8.3Vendor IDsPlanned8.4Command RegisterPlanned8.5Status RegisterPlanned8.6Configuration HeaderPlanned
Module 9
Base Address Registers (BARs)
9.1What BARs ArePlanned9.2Memory BARsPlanned9.3IO BARsPlanned9.4BAR SizingPlanned9.5Address AssignmentPlanned9.6Host AccessPlanned
Module 10
Transaction Layer Overview
10.1RequestsPlanned10.2CompletionsPlanned10.3Posted TransactionsPlanned10.4Non-Posted TransactionsPlanned10.5Transaction FlowPlanned
Module 11
Transaction Layer Packets (TLPs)
11.1TLP OverviewPlanned11.2TLP StructurePlanned11.3HeadersPlanned11.4PayloadsPlanned11.5Routing InformationPlanned11.6AttributesPlanned11.7Packet TypesPlanned
Module 12
Memory Transactions
12.1Memory ReadPlanned12.2Memory WritePlanned12.3Completion FlowPlanned12.4ExamplesPlanned12.5Performance ImplicationsPlanned
Module 13
Completion Packets
13.1Completion TypesPlanned13.2Completion StatusPlanned13.3Split CompletionsPlanned13.4OrderingPlanned
Module 14
Data Link Layer
14.1Reliability GoalsPlanned14.2ACKPlanned14.3NAKPlanned14.4Replay BufferPlanned14.5Sequence NumbersPlanned
Module 15
DLLPs
15.1DLLP TypesPlanned15.2Flow Control UpdatesPlanned15.3ACK PacketsPlanned15.4NAK PacketsPlanned15.5Power Management DLLPsPlanned
Module 16
Flow Control
16.1CreditsPlanned16.2Posted CreditsPlanned16.3Non-Posted CreditsPlanned16.4Completion CreditsPlanned16.5Credit ConsumptionPlanned16.6Credit UpdatesPlanned
Module 17
Physical Layer
17.1SerializationPlanned17.2DeserializationPlanned17.3Link TrainingPlanned17.4EqualizationPlanned17.5Electrical ConceptsPlanned
Module 18
LTSSM
18.1LTSSM OverviewPlanned18.2DetectPlanned18.3PollingPlanned18.4ConfigurationPlanned18.5RecoveryPlanned18.6L0Planned18.7L0sPlanned18.8L1Planned18.9DisabledPlanned18.10Hot ResetPlanned
Module 19
PCIe Interrupts
19.1Legacy Interrupts (INTx)Planned19.2MSIPlanned19.3MSI-XPlanned19.4Interrupt RoutingPlanned19.5Performance AdvantagesPlanned
Module 20
DMA over PCIe
20.1DMA over PCIe OverviewPlanned20.2DMA ConceptsPlanned20.3Host Memory AccessPlanned20.4Scatter-GatherPlanned20.5High-Speed Data MovementPlanned20.6FPGA ExamplesPlanned
Module 21
PCIe Switches
21.1RoutingPlanned21.2Packet ForwardingPlanned21.3Fabric ScalingPlanned21.4Multi-Endpoint SystemsPlanned
Module 22
PCIe Performance
22.1ThroughputPlanned22.2LatencyPlanned22.3Credit BottlenecksPlanned22.4Payload Size EffectsPlanned22.5Link EfficiencyPlanned22.6Benchmark InterpretationPlanned
Module 23
PCIe RTL Design
23.1Endpoint ArchitecturePlanned23.2BAR LogicPlanned23.3DMA EnginesPlanned23.4TLP GenerationPlanned23.5Completion LogicPlanned23.6Design PatternsPlanned
Module 24
PCIe Verification
24.1Protocol VerificationPlanned24.2AssertionsPlanned24.3ScoreboardsPlanned24.4CoveragePlanned24.5VIPPlanned24.6UVM ArchitecturePlanned24.7Error InjectionPlanned
Module 25
PCIe Debugging
25.1PCIe Debugging OverviewPlanned25.2Enumeration FailuresPlanned25.3Link Training FailuresPlanned25.4LTSSM IssuesPlanned25.5BAR ProblemsPlanned25.6DMA FailuresPlanned25.7Completion TimeoutsPlanned25.8Credit DeadlocksPlanned25.9Protocol Analyzer DebugPlanned
Module 26
PCIe in SoCs and Systems
26.1CPUsPlanned26.2GPUsPlanned26.3SSD ControllersPlanned26.4Network AdaptersPlanned26.5FPGA CardsPlanned26.6AI AcceleratorsPlanned
Module 27
PCIe Interview Mastery
27.1Beginner QuestionsPlanned27.2Intermediate QuestionsPlanned27.3Advanced QuestionsPlanned27.4Senior QuestionsPlanned
Module 28
PCIe vs Other Interconnects
28.1PCIe vs AXIPlanned28.2PCIe vs EthernetPlanned28.3PCIe vs USBPlanned28.4PCIe vs CXLPlanned
Module 29
Real Industry Case Studies
29.1NVMe SSDPlanned29.2GPU InterfacePlanned29.3FPGA Accelerator CardPlanned29.4SmartNICPlanned29.5AI AcceleratorPlanned29.6Data Center SystemsPlanned
Module 30
PCIe Design Review Checklist
30.1Architecture ChecklistPlanned30.2RTL ChecklistPlanned30.3Verification ChecklistPlanned30.4Integration ChecklistPlanned30.5Performance ChecklistPlanned30.6Debug ChecklistPlanned30.7Interview ChecklistPlanned
Module 31
PCIe Misconceptions Engineers Have
31.1"PCIe Is Just a Faster PCI"Planned31.2"PCIe Is Memory-Mapped Only"Planned31.3"BARs Contain Memory"Planned31.4"DMA Bypasses PCIe Protocol"Planned31.5"MSI Is Just a Software Interrupt"Planned31.6"LTSSM Only Matters During Boot"Planned