PCIe · Module 1

PCI — A Standardized, Processor-Independent Local Bus

How PCI answered ISA's limits with a processor-independent local bus, initiator/target transactions, arbitration, bus mastering, bursts, and standardized configuration — while still keeping one shared parallel medium.

Chapter 1.2 ended with four constraints that made ISA unfixable: a deliberately frozen clock, a 16 MB address reach, resource assignment that was never part of the bus model, and a scarce supply of interrupt and DMA lines. Those weaknesses were obvious to the engineers of the time. So this chapter answers the question that follows: how much could they actually fix while still keeping a shared parallel bus?

The answer is: a great deal. PCI — Peripheral Component Interconnect — is not a failed intermediate step or a stopgap. It is a serious architectural redesign that fixed nearly every ISA-era problem that could be fixed within the shared-bus model, and it carried the industry for well over a decade. What it did not change is the model itself, and that is the thread this module follows into later chapters.

1. The Architectural Reset — A Bus of Its Own

The most important thing PCI changed is not a number. It is what the bus is.

ISA exposed a system-bus-like interface at the slots, so cards were coupled to the conventions of a particular processor family. PCI broke that coupling. It defines a bus with its own protocol, its own timing rules, and its own signalling — and connects it to the processor through a host bridge. The bridge translates between whatever the CPU side does and what the PCI side requires.

That indirection is the whole point. A PCI device is designed against the PCI specification, not against a CPU's bus. The same card can work in systems built around entirely different processor architectures, because nothing in its interface assumes one. This is what processor independence means in practice, and it is the property ISA structurally could not have.

A note on configurations, because it is easy to over-generalise: the familiar 32-bit, 33 MHz arrangement is the common baseline implementation, not the definition of PCI. The architecture also defines a 64-bit data path and a 66 MHz clock, and real systems shipped various combinations across successive revisions of the specification. When you see a single width-and-clock pair quoted as "PCI," read it as one widely-deployed configuration rather than the only one.

2. The Shape That Stayed — One Shared Parallel Bus

Underneath the redesign, the topology is the one Chapter 1.1 described: several devices attached to a common set of parallel wires, with address and data carried across the bus and a control mechanism deciding who may drive it.

PCI refines this considerably. Address and data share the same lines across different phases of a transaction rather than occupying separate wires, which holds the pin and trace count down for a given data width. But refinement is not replacement. Every attached device still connects to the same medium, and every transfer still consumes capacity that no other device can use at that moment.

Figure 1 — the PCI shared local bus. The host bridge connects the processor and memory side to a PCI bus that every device attaches to as a peer. A central arbiter decides which requester may drive the bus. Here Device A has been granted ownership and is initiating a transfer to Device B, while Device C waits its turn — one shared medium, one owner at a time, and one pool of bandwidth divided among all of them.

3. Initiators and Targets

PCI describes a transfer using two roles. The initiator starts a transaction: it acquires the bus, drives the address and the command that says what kind of access this is, and drives or receives the data. The target is the device that owns the addressed resource and claims the transaction, then supplies or accepts the data.

Two things make this more than vocabulary.

First, the roles are per-transaction, not per-device. A device that acts as the initiator for one transfer may be the target of the next. There is no permanent hierarchy in which one component is forever the requester and the rest forever respond.

Second, the target claims the transaction by recognising the address as its own. This is the same decoding responsibility ISA cards had, but it now operates on address ranges the system assigned rather than ranges a person chose with jumpers — which is what §6 is about.

4. Arbitration — Who Gets to Drive

Several devices on the bus may want to initiate a transfer at the same time. Something has to decide between them, and on PCI that something is a central arbiter: a device requests the bus, and the arbiter grants ownership to one requester.

The architectural lesson is worth stating plainly, because it outlives every detail of how arbitration is implemented:

Multiple potential initiators exist, but they still contend for one shared medium.

Keep two refinements in view so the picture stays accurate. Arbitration governs which device drives the bus, and it can overlap with work already in progress — a request for the next ownership can be resolved while the current transfer is still running, so the changeover need not stall the bus. And "one owner at a time" is a statement about driving the wires, not a claim that the system can only ever have one operation conceptually in flight; PCI has mechanisms by which a target can defer a slow access so the bus is not held idle waiting for it. What remains true regardless is the contention itself: bus ownership is a resource that devices compete for.

5. Bus Mastering — Devices That Move Their Own Data

A bus master is a device capable of acting as an initiator: it can acquire the bus and drive transfers on its own behalf rather than waiting for the processor to move data for it.

The payoff is systemic. If a network controller or a disk controller can transfer data into memory itself, the CPU is not obliged to mediate every word — it can set up a transfer, do other work, and be notified on completion. That is the same class of benefit DMA provides, and it is why bus-master-capable peripherals matter far beyond their own throughput: they change what the processor is free to do.

Be careful with the history here. Neither DMA nor the idea of a peripheral initiating its own transfers originated with PCI — ISA-era systems had DMA channels and a limited notion of bus masters. What PCI did was standardize and generalize the capability: mastering is a normal, well-defined part of the architecture available to devices generally, rather than an awkward facility constrained by a handful of shared channels.

6. Bursts — Paying the Setup Cost Once

Acquiring the bus and establishing an address costs time. If a device paid that cost for every single word, most of the bus's capacity would go to overhead rather than data.

A burst amortises it. The initiator establishes the address once and then transfers a sequence of data phases to consecutive locations while retaining ownership. One setup, many words moved. The longer the burst, the smaller the share of bus time spent on overhead rather than payload.

This is the same efficiency principle that shows up in every interconnect you will study, including the one this curriculum is building toward: the cost of starting a transfer is fixed, so moving more data per setup raises efficiency. Bursts do not make the wires faster; they raise the fraction of the wire's time spent carrying data.

7. Standardized Configuration and Discovery

This is the change users felt most, and architecturally it is the sharpest break from ISA.

Every PCI function exposes a standardized configuration space — a defined region, separate from ordinary memory and I/O access, holding information about the device in a layout every device follows. Firmware and system software can read it to determine what a device is and what resources it needs, and can then write to it to assign those resources.

Two consequences follow:

Devices become discoverable. The system can scan the bus and find out what is present without being told in advance. Identification is part of the architecture, not a matter of the user knowing what they installed.
Resource assignment becomes software's job. Rather than a person choosing address ranges and interrupt assignments on a card, the device describes what it requires and the system decides where those requirements land.

That is the whole point of covering configuration in this chapter, and it is deliberately kept at this level. The specific structure of the configuration header, how address windows are sized and programmed, and how the enumeration process actually walks a hierarchy are subjects of their own later in this curriculum — Modules 7, 8, and 9 take them up properly.

Standardized configuration is not the same as PCIe enumeration

PCI established the model: devices are self-describing, and software assigns their resources. PCIe inherits that model and the software-visible compatibility that comes with it, which is exactly why the two feel similar from an operating system's point of view.

But inheriting a model is not the same as being the same mechanism. Do not read "PCI has configuration space" as "PCI enumerates the way PCIe does." The topology being walked, and the means by which configuration accesses reach a device, differ substantially — and those differences only make sense after the PCIe fabric itself has been introduced. Hold the historical point: PCI made discovery and resource management part of the standardized architecture rather than a matter of jumpers and prior assumptions.

8. What PCI Achieved — and What It Left Untouched

Set against Chapter 1.2's four constraints, the scorecard is strong. Devices stopped being tied to one processor family's bus conventions. Configuration stopped depending on a human with a manual and a set of jumpers. Peripherals could move their own data as a matter of course. Bursts made transfers efficient rather than word-at-a-time. Address reach and bus performance both improved substantially over the ISA baseline. PCI deserves to be understood as a success — the shared parallel bus done properly.

What it did not change is the shape. There is still one medium that every device attaches to, still one pool of bandwidth divided among all of them, and still arbitration deciding who may drive. Those are properties of the shared-bus model, not defects in PCI's execution of it, and they are exactly what the rest of this module examines: Chapter 1.5 takes up PCI's limitations directly, Chapter 1.6 the problems inherent to shared buses, and Chapter 1.7 the scaling wall that follows. Chapter 1.4 covers AGP, the response when one device's appetite outgrew what a shared bus could give it.

The bridge to everything after this module is a single distinction:

ISA — a device participates in a system-bus-like expansion interface.
PCI — devices participate in a standardized, processor-independent shared local bus.
PCIe — devices become endpoints connected through dedicated point-to-point links in a switched fabric.

PCI moved the industry from the first to the second. The move to the third is what the remainder of this curriculum is about.

9. Common Misconceptions

Myths to unlearn

"PCI was just a faster ISA." The clock and width improved, but the substantive change is architectural: a bus with its own protocol reached through a host bridge, rather than a slot-level extension of the processor's bus, plus standardized configuration and general bus mastering. Reading PCI as "ISA, quicker" misses everything that made it matter.
"PCI solved the shared-bus problem." It solved a great many problems within the shared-bus model. The model itself — one medium, one bandwidth pool, arbitration for ownership — is untouched, which is why later chapters still have something to explain.
"PCI configuration means it worked like PCIe enumeration." PCI established self-describing devices and software-assigned resources, and PCIe inherited that model. The mechanisms and the topology being traversed are not the same thing, and later modules treat PCIe's properly.
"Bus mastering means a device transfers whenever it wants." A master may request the bus; the arbiter decides when it gets it. Mastering removes the processor from the data path, not contention from the medium.
"PCI and PCIe are electrically related because the names are similar." They share a lineage and a software-compatibility model, not an electrical or topological one. PCIe is not PCI's parallel wires serialised — it is a different interconnect model, as Chapter 1.1 laid out.
"PCI removed manual configuration everywhere." It made automatic configuration the architectural norm, which is the durable point. In practice, systems ran PCI alongside legacy slots for years, and particular devices and firmware still needed manual attention. The model changed decisively; the field took longer.

10. Real Engineering Relevance

The reason this chapter is not merely history is that PCI is where several ideas a modern RTL or verification engineer works with every day first became standard architecture:

Discoverable devices. A device that announces what it is, rather than being declared by configuration files or assumed by the system.
Software-assigned, memory-mapped resources. A device requesting address space and the system deciding where it lands.
Autonomous device-initiated traffic. Peripherals that move their own data and interrupt when finished — the model behind essentially every high-throughput device you will verify.
Explicit transaction roles. A requester and a responder per transaction, which is the frame nearly every interconnect protocol uses, AXI included.

Keep the continuity honest, though. These concepts survive into PCIe; the protocol and electrical design do not. PCIe did not serialise PCI's wires — it replaced the shared parallel medium with point-to-point links and switching, and rebuilt the transaction machinery on top of that. Conceptual inheritance and implementation inheritance are different claims, and conflating them is one of the more common ways engineers go wrong when reasoning about PCIe from PCI experience.

11. Understanding Check

12. Summary

PCI answered the ISA-era problems that could be answered without abandoning the shared parallel bus — and it answered most of them well. It defines a bus with its own protocol reached through a host bridge, which makes devices processor-independent rather than tied to one CPU family's conventions. Transactions are described by initiator and target roles held per transfer. A central arbiter decides which requester drives the shared medium. Bus mastering lets capable devices move their own data instead of routing everything through the processor, and bursts amortise the fixed setup cost across many data phases. Standardized configuration space made devices self-describing and turned resource assignment into a software responsibility instead of a jumper-setting exercise. The widely-deployed 32-bit, 33 MHz form is one common configuration, not the definition — the architecture spans wider paths and higher clocks across its revisions.

What PCI did not change is the shape of the thing: one shared medium, one bandwidth pool, and arbitration for the right to drive it. Hold the durable model — PCI decoupled expansion devices from the CPU's native bus and standardized how devices share a local bus, but the bus itself was still one shared electrical and bandwidth resource — and both the achievement and the eventual limit stay in view at once.

13. What Comes Next

Chapter 1.4 — AGP takes up what happened when a single device's bandwidth appetite outgrew what a shared bus could offer it. Chapters 1.5 through 1.7 then examine PCI's limitations, the problems inherent to shared buses, and the scaling wall that ended the model — the analysis this chapter deliberately left alone so that PCI could first be understood on its own terms.

Revisit ISA for the interconnect PCI replaced, or Evolution of System Interconnects for the whole arc in one view. Browse the full path on the PCIe tutorials index.