PCIe · Module 27
Beginner PCIe Interview Questions — The Openers, Answered Properly
The first four questions of a PCIe interview are graded on whether you know what kind of thing PCIe is. Model answers at two depths, the plausible wrong answer for each, the follow-up that exposes it, and a trace to read.
Module 26 read six systems. This module asks whether you can explain them in a room, and it starts where every PCIe interview starts — with questions that look like definitions and are graded as diagnostics.
1. Sources, Scope, and What This Chapter Refuses to Do
2. What a Beginner Interview Is Actually Testing
Not whether you can define PCIe. Whether you know what kind of thing it is.
| The interviewer is checking | A candidate who lacks it says |
|---|---|
| point-to-point versus shared | "PCIe is a bus" (§4) |
| serial lanes versus a parallel bus | "x16 means a 16-bit bus" (§5) |
| that there are layers | describes wires and software with nothing between |
| that transactions have kinds | treats a read and a write as symmetric (§8) |
| that discovery is a process | assumes the host "just knows" what is plugged in (§9) |
| calibrated confidence | invents an encoding rather than saying they would check (§14) |
Three readings.
Every row is a category understanding, not a fact. That is deliberate on the interviewer's part: facts can be revised the night before, and category errors survive months of study — which is why the openers are worth taking seriously rather than rushing past.
The last row is graded even at beginner level, and it is the one candidates least expect. Inventing a plausible-sounding field layout is worse than saying you would check the specification revision, and an interviewer who knows the answer will notice.
And the openers set the interview's depth. A crisp, correctly-scoped answer to "what is PCIe?" buys harder and more interesting questions. A vague one buys twenty more minutes of definitions.
3. The Two Depths
Answer at the size you are asked. Practise both, because the interviewer picks.
| Depth | Purpose | Failure mode |
|---|---|---|
| ~15 seconds | identify and scope | drifting into detail nobody requested |
| ~60 seconds | the problem it solves, plus the structure | listing features instead of the problem |
And a rule that applies to all of §4–§10: the 60-second version should contain at least one negation — what the thing is not. That is where the misconception lives, and volunteering it demonstrates you have hit the confusion yourself.
4. "What is PCIe?"
15 seconds. "A high-speed serial interconnect for attaching devices to a host. It's point-to-point and switched — each device gets its own link to a switch or to the root complex — and it's layered, with a transaction layer, a data link layer and a physical layer."
60 seconds. Add the problem it solves: "the interconnects it replaced were shared parallel buses — every device on the same wires, arbitrating for access, with the whole bus limited by its slowest member and by how far a wide parallel bus can be routed at speed. PCIe gives each device a dedicated point-to-point link and scales by adding lanes and generations rather than by widening a shared bus." Then the structure: "transactions are carried in packets — TLPs — over a link layer that handles reliability, over a serial physical layer" (3.2, 11.1).
The weak answer. "PCIe is a fast bus for connecting graphics cards and SSDs."
Why the interviewer probes. The word "bus" is the tell, and the examples suggest the candidate knows PCIe as a slot rather than as an architecture.
The follow-up. "Is it a bus?" — which is §5.
5. "Is PCIe a Bus?"
The answer is no, and the reasoning matters more than the word.
15 seconds. "No — it's point-to-point and switched. Each link connects exactly two components. Fan-out comes from switches, not from more devices sharing wires."
60 seconds. Add what changes as a consequence: "because there's no shared medium there's no bus arbitration for access — the contention moves into switches and into flow control instead" (21.1, 16.1). "Each link has its own bandwidth rather than a share of a common pool, so adding a device doesn't slow the others down on their own links. And the topology becomes a tree with a root, which is why enumeration works the way it does" (2.9, 4.1).
| The weak answer | Why it is incomplete |
|---|---|
| "It's a bus but faster" | the topology changed, not just the rate — and every consequence in the 60-second answer follows from the topology |
| "It's a bus because the OS calls it a bus" | bus numbers are an addressing concept (8.1), inherited for software compatibility — they do not describe a shared medium |
And the second row is worth knowing because it is a genuinely confusing artefact. PCIe uses bus/device/function numbering in configuration space — so software and tools say "bus" constantly. The numbering is an address space; the electrical topology is point-to-point. A candidate who can separate those two has answered the question well.
The follow-up to expect. "Then what does a switch do that a bus did not?" — it routes, per transaction, rather than broadcasting to a shared medium (21.1).
6. "What Is a Lane, and What Does x16 Mean?"
15 seconds. "A lane is one differential pair in each direction — so it's full-duplex on its own. A link is one or more lanes, and x16 means sixteen lanes in parallel. Bytes are striped across the lanes."
60 seconds. Add the distinction that is actually being tested: "these are independent serial lanes, not a 16-bit parallel bus. Each lane carries its own serial stream with its own clock recovery, and the link layer stripes data across whatever lanes are trained. That's why a link can negotiate down — x16 can operate as x8 or x4 if lanes are unavailable — and why lane count and per-lane rate are separate scaling axes" (6.5, 6.8).
Then the consequence worth volunteering: "and width buys bandwidth, not latency" — a wider link moves more per second and does not shorten a round trip (22.2).
| Weak answer | What is missing |
|---|---|
| "x16 is a 16-bit bus" | independent serial lanes with per-lane clock recovery, not parallel bits sharing a clock |
| "more lanes means lower latency" | width and latency are separate; a round trip is unchanged |
| "a lane is a wire" | a differential pair in each direction — full-duplex per lane |
The follow-up. "How do you calculate a link's throughput?" — do not quote a headline figure. Say "generation gives a per-lane rate, multiply by lanes, then subtract encoding and protocol overhead — the method is what matters and the encoding differs by generation" (6.7, 22.5). Naming the method and declining to quote a rate from memory is the stronger answer (§14).
7. "Root Complex, Endpoint, Switch — What Are They?"
| Component | One sentence | Owns |
|---|---|---|
| Root Complex | the host's connection to the fabric, and the topology's root | generates Configuration Requests; owns enumeration (2.2) |
| Endpoint | a device that terminates transactions | responds to configuration; may originate DMA (2.3) |
| Switch | fan-out; routes transactions between links | routing, not broadcasting (2.4) |
60 seconds. "The Root Complex is the host side — it's the only component that generates Configuration Requests, so it's the one that discovers and configures everything else. Endpoints are the devices. Switches provide fan-out, and each of their ports is a separate link. The result is a tree rooted at the Root Complex, and that structure is exactly what enumeration walks" (4.1, 7.1).
The addition that marks a candidate who has read further (26.1 §2): "and the Root Complex is usually a function inside the CPU rather than a separate chip — which matters because its obligations end up distributed across blocks."
Weak answer. "The Root Complex is the chipset." — it may not be a separate component at all, and the answer describes an implementation of a topology role.
8. "What Is a TLP? And Posted Versus Non-Posted?"
15 seconds. "A TLP is a Transaction Layer Packet — the unit the transaction layer moves. It has a header describing the transaction and optionally a payload. Posted transactions expect no response; non-posted expect a Completion."
60 seconds. Add why the distinction exists: "a memory write is posted — it is sent and not acknowledged at the transaction layer, so the requester does not wait. A memory read is non-posted: the requester issues a Read Request and the data comes back later in one or more Completions. That asymmetry is why reads and writes have completely different performance characteristics, and why a read's cost includes a round trip" (10.3, 10.4, 13.1).
| Weak answer | The follow-up that exposes it |
|---|---|
| "posted is faster" | "faster at what? What does the requester wait for in each case?" |
| "a read returns its data in the response" | "is it always one Completion?" — it may be several (13.3, 26.2 §6) |
| "an ACK means the write arrived at the device" | "which component sent the ACK?" — it is link-local (14.2, 25.9 §8) |
The third row is the most valuable thing on this page, and it is often asked at beginner level as a trap: an ACK is a Data Link Layer acknowledgement to the immediate neighbour, not a delivery receipt for the destination. A candidate who volunteers that has answered an advanced question early.
9. "How Does the Host Know What Is Plugged In?"
15 seconds. "Enumeration. The Root Complex walks the topology issuing Configuration Requests, discovers what responds, assigns bus numbers, then reads each function's BARs to find out how much address space it needs and assigns it."
60 seconds. Add the sequence and its one-shot nature: "the Root Complex is the only source of Configuration Requests. It discovers a device by getting a valid response at a bus/device/function address. Then it reads the configuration header to learn what the device is, and reads and writes the BARs to size and place its memory windows. Once that's done the device is reachable at real addresses and the driver can map it" (7.1, 8.1, 8.6, 9.4, 9.5).
The addition worth volunteering (26.5 §5): "and it has a deadline — a device that isn't answering when the host scans is indistinguishable from an empty slot. There's no error; it just isn't in the topology."
"What is a BAR?" — "a Base Address Register. The device advertises how much space it needs and of what kind; the host assigns a base address; accesses to that window reach the device" (9.1, 9.6).
Weak answer. "The BIOS scans the PCI bus." — true and uninformative. The interviewer wants the mechanism: who issues what, and what the device does in response.
10. Read the Trace
PCIe interviews frequently put a trace in front of you. This one is deliberately simple, and it still has three questions in it.
One read, and one thing happening in the gap
10 cyclesThe three questions, and what a good answer says.
"What transaction is this?" "A non-posted memory read. The request carries no data; the data comes back in the completion several cycles later" (10.4).
"What is the gap between cycle 1 and cycle 6?" "The round trip — request out, completion back. It's latency, and it is not something link width changes" (22.2, §6).
"Why is there a second request at cycle 3?" This is the real question. "Because the requester doesn't have to wait. It has two reads outstanding at cycle 3–5, which is how you get throughput out of a path with latency — otherwise you'd be limited to one transaction per round trip" (26.2 §5 does the arithmetic).
And the marker at cycle 7 is the one to notice unprompted: outstanding falls on completion, not on issue. A count that decremented at issue would report the pipe as empty while two reads were still in flight — which is the beginner form of a mistake that recurs at every level (23.3).
11. The Five Traps
| Trap | Why it is plausible | The correction in one line |
|---|---|---|
| "PCIe is a bus" | software and tools say bus constantly | bus numbers are an address space; the topology is point-to-point (§5) |
| "x16 is a 16-bit bus" | width implies parallel bits | independent serial lanes, striped, per-lane clock recovery (§6) |
| "more lanes reduce latency" | wider feels faster in every way | width is bandwidth; latency is a round trip (§6) |
| "an ACK means it arrived" | the word means that in ordinary use | link-local acknowledgement to the immediate neighbour (§8) |
| "a read returns its data" | it is how a function call behaves | one request, one or more Completions (§8) |
And the honest observation about all five: each is a nearly correct statement. That is what makes them traps rather than errors — they are the sentences a careful person produces when they have read about PCIe and not yet had to build against it.
12. The Whiteboard Opener
"Draw me a small PCIe topology."
A weak answer draws a CPU and some boxes on a line.
A strong answer draws a tree and labels the roles (§7): Root Complex at the top, a switch below it, endpoints on the switch's downstream ports, and one link per connection — each link its own point-to-point pair. Then say the sentence that shows you know why the shape matters: "the tree has a root because the Root Complex is the only thing that generates Configuration Requests, so enumeration walks down from there" (7.1).
Two additions that cost nothing and demonstrate depth. Mark that each link may be a different width — x16 to one endpoint, x4 to another (6.8). And mark that a switch routes rather than broadcasts (21.1), which is the point that distinguishes the drawing from a bus diagram.
13. Assembling the Answers
A short drill, because these questions arrive in sequence and the transitions are graded too.
| If you just said… | The natural next question is | Have ready |
|---|---|---|
| "point-to-point and switched" | "so what does a switch do?" | routing, per transaction (§5) |
| "lanes are serial" | "how do you compute throughput?" | the method, not a figure (§6) |
| "the Root Complex enumerates" | "what does it actually send?" | Configuration Requests (§9) |
| "reads are non-posted" | "so what limits read throughput?" | outstanding capacity (§10) |
| "a BAR is a window" | "who assigns the address?" | the host, at enumeration (§9) |
And the pattern is worth internalising: every good beginner answer ends on a noun the interviewer can pull. Switch. Method. Configuration Request. Outstanding. Enumeration. Answers that end on an adjective — "fast", "efficient", "modern" — give the interviewer nothing to follow, and the interview stalls.
14. When You Do Not Know
Asked for an exact encoding, register offset, timer value or generation-specific rate, the correct answer is not a guess.
The shape that works has two parts. "That's revision-specific and I'd check the specification revision we're building to. What I can tell you is what the field has to accomplish, and what breaks if it's wrong…" — then continue with the part you can reason about.
Three readings.
Stopping at "I don't know" gives up the question; guessing risks being confidently wrong in front of someone who knows. The combination is what a senior colleague sounds like, and it is available at beginner level.
One invented field layout costs more than it saves. It casts doubt on every correct answer that preceded it, and an interviewer who tests one fact often tests two.
And if you are corrected, update immediately and follow the new information. Defending a wrong position costs far more than the original error — and an interviewer offering a correction is frequently testing exactly that.
15. Readiness Markers
You are ready for this level when you can, without preparation:
- state what PCIe is in one sentence that includes point-to-point and layered (§4)
- explain why it is not a bus, and separate bus numbers from a shared medium (§5)
- explain a lane as a differential pair per direction, and x16 as independent serial lanes (§6)
- say that width buys bandwidth and not latency (§6)
- name the method for computing throughput without quoting a rate (§6)
- distinguish Root Complex, endpoint and switch by what each owns (§7)
- explain posted versus non-posted in terms of what the requester waits for (§8)
- say that an ACK is link-local, unprompted (§8)
- say that a read may return more than one Completion (§8)
- describe enumeration as a mechanism — who issues what, and what responds (§9)
- explain what a BAR is and who assigns its address (§9)
- read a simple trace and identify the round trip and the outstanding count (§10)
- explain why a second request appears before the first completion (§10)
- decline to invent an encoding, and continue usefully afterwards (§14)
If any of those needs a pause, the fix is the chapter cited beside it — not more revision of this page.
16. What Comes Next
These questions tested what kind of thing PCIe is. The next level tests whether you know how it is put together.
27.2 moves to enumeration, BARs and TLPs at mechanism depth: what a Configuration Request actually is, how a BAR is sized rather than simply assigned, how a TLP is routed, and why posted and non-posted ordering rules exist. The trace gets harder too — the intermediate reading exercise has a wrong answer that looks correct.