Equalization — Undoing a Channel That Remembers

transmitted:   0    0    1    0    0
received:      0    0    █    0    0        ideal

transmitted:   0    0    1    0    0
received:      ·    ▁    █    ▄    ▂        real, lossy
                   pre   main post post

h = [ 0.10,  1.00,  0.30,  0.10 ]
      pre    main   post1  post2

r[2] = 1.00·x[2] + 0.30·x[1] + 0.10·x[0] + 0.10·x[3]
     = 1.00·(−1) + 0.30·(−1) + 0.10·(+1) + 0.10·(+1)
     = −1.00 − 0.30 + 0.10 + 0.10
     = −1.10

r[2] = 1.00·(+1) + 0.30·(+1) + 0.10·(−1) + 0.10·(−1)
     = +1.00 + 0.30 − 0.10 − 0.10  =  +1.10
r[3] = 1.00·(−1) + 0.30·(+1) + 0.10·(+1) + 0.10·(−1)
     = −1.00 + 0.30 + 0.10 − 0.10  =  −0.70

y[n] = c_pre · x[n+1] + c_main · x[n] + c_post · x[n-1]

corrected[n] = sample[n] − Σ tap[k] · decision[n−k]

Port A transmitter setting  →  channel  →  Port B receiver quality
Port B evaluates                          Port B requests a change
Port A applies                            ← the request travels back

// SYNTHESIZABLE. Transmitter equalization setting ownership.
// THAT A TRANSMITTER HAS A SELECTABLE SHAPING SETTING is vendor-verified
// (section 1: TXDEEMPH, and emphasis controlled via driver segments). The
// PRESET/COEFFICIENT SPLIT is the architectural shape; the numeric preset
// values are NOT published here (section 6). Validation policy and the
// same-cycle priority are ILLUSTRATIVE.
package tx_eq_pkg;
 
  localparam int COEF_W   = 8;      // signed tap, Q1.7-style
  localparam int PRESET_W = 4;      // opaque preset identifier
 
  typedef struct packed {
    logic signed [COEF_W-1:0] pre;
    logic signed [COEF_W-1:0] main;
    logic signed [COEF_W-1:0] post;
  } tx_taps_t;
 
endpackage

import tx_eq_pkg::*;
 
module tx_eq_config #(
  // Bitmap of preset IDs this macro supports, supplied by the integrator
  // from the device datasheet -- not published here (section 6).
  parameter logic [(1<<PRESET_W)-1:0] SUPPORTED_PRESETS = '1,
  parameter int signed COEF_MIN = -64,
  parameter int signed COEF_MAX =  127
) (
  input  logic clk,
  input  logic rst_n,
 
  input  logic                  preset_valid,
  input  logic [PRESET_W-1:0]   preset_id,
  input  logic                  coeff_valid,
  input  tx_taps_t              coeff_req,
 
  // ---- To the transmitter macro -------------------------------------------
  output logic                  cfg_valid,
  output tx_taps_t              cfg_taps,
  output logic [PRESET_W-1:0]   cfg_preset,
  output logic                  cfg_is_preset,
 
  output logic                  reject_unsupported,
  output logic                  reject_range
);
 
  // RANGE CHECK IN SIGNED ARITHMETIC. An unsigned comparison here accepts
  // every negative coefficient as a huge positive one -- and negative taps
  // are the useful ones (section 18, mutation 2).
  function automatic bit coef_ok(input logic signed [COEF_W-1:0] c);
    return (c >= COEF_W'(COEF_MIN)) && (c <= COEF_W'(COEF_MAX));
  endfunction
 
  wire taps_in_range = coef_ok(coeff_req.pre)
                    && coef_ok(coeff_req.main)
                    && coef_ok(coeff_req.post);
  wire preset_supported = SUPPORTED_PRESETS[preset_id];
 
  // ==================================================================
  // SAME-CYCLE PRIORITY, DECLARED.
  // A preset and a coefficient request together is a caller error, not a
  // design case. COEFFICIENTS WIN, being the more specific request, and
  // the conflict is reported rather than silently resolved. Leaving this
  // to `if` ordering is how two blocks come to disagree about which
  // request applied.
  // ==================================================================
  wire take_coeff  = coeff_valid && taps_in_range;
  wire take_preset = preset_valid && !coeff_valid && preset_supported;
 
  tx_taps_t            taps_q;
  logic [PRESET_W-1:0] preset_q;
  logic                is_preset_q, v_q, rej_uns_q, rej_rng_q;
 
  assign cfg_valid          = v_q;
  assign cfg_taps           = taps_q;
  assign cfg_preset         = preset_q;
  assign cfg_is_preset      = is_preset_q;
  assign reject_unsupported = rej_uns_q;
  assign reject_range       = rej_rng_q;
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      // A DEFINED SAFE STATE, not a stale one. cfg_valid low means the
      // macro runs its own default, which is the only honest thing to say
      // before anything has been applied.
      taps_q <= '0; preset_q <= '0; is_preset_q <= 1'b0; v_q <= 1'b0;
      rej_uns_q <= 1'b0; rej_rng_q <= 1'b0;
    end else begin
      // ==============================================================
      // ATOMIC COMMIT: ALL THREE TAPS IN ONE NONBLOCKING ASSIGNMENT.
      //
      // The wrong architecture writes pre, then main, then post under
      // separate conditions. For at least one cycle the transmitter then
      // drives a MIXED old/new tap set -- a shape nobody requested, onto
      // a live lane. Holding them in one packed struct makes that
      // unconstructable rather than merely unlikely.
      // ==============================================================
      if (take_coeff) begin
        taps_q      <= coeff_req;
        is_preset_q <= 1'b0;
        v_q         <= 1'b1;
      end else if (take_preset) begin
        preset_q    <= preset_id;
        is_preset_q <= 1'b1;
        v_q         <= 1'b1;
      end
 
      // Rejections are STICKY. A request the macro cannot honour must
      // never be indistinguishable from one it did.
      if (preset_valid && !coeff_valid && !preset_supported) rej_uns_q <= 1'b1;
      if (coeff_valid && !taps_in_range)                     rej_rng_q <= 1'b1;
    end
  end
 
endmodule

import tx_eq_pkg::*;
 
// SYNTHESIZABLE. Hold an equalization request while the macro control
// path is busy. The need follows from the macro interface being
// backpressurable while the requesting logic is not. Depth and the
// lane-stability contract are ILLUSTRATIVE.
module eq_request_hold #(
  parameter int LANES  = 16,
  // GUARDED. $clog2(1) is zero; LANES = 1 is a legal configuration.
  parameter int LANE_W = (LANES <= 1) ? 1 : $clog2(LANES)
) (
  input  logic clk,
  input  logic rst_n,
 
  input  logic                in_valid,
  output logic                in_ready,
  input  logic [LANE_W-1:0]   in_lane,
  input  logic                in_is_preset,
  input  logic [PRESET_W-1:0] in_preset,
  input  tx_taps_t            in_taps,
 
  output logic                out_valid,
  input  logic                out_ready,
  output logic [LANE_W-1:0]   out_lane,
  output logic                out_is_preset,
  output logic [PRESET_W-1:0] out_preset,
  output tx_taps_t            out_taps,
 
  output logic                lane_range_error
);
 
  generate
    if (LANES  < 1) $error("LANES must be at least 1");
    if (LANE_W < 1) $error("LANE_W must be at least 1");
    if ((LANES > 1) && ((1 << LANE_W) < LANES))
      $error("LANE_W too narrow to index LANES");
  endgenerate
 
  // RANGE SAFETY on an externally-supplied lane id. Never rely on "the
  // controller will not send that" -- a request naming a lane that does
  // not exist must be refused, not applied to whatever the index aliases.
  localparam int CHK = LANE_W + 1;
  wire lane_legal = (CHK'(in_lane) < CHK'(LANES));
 
  logic                v_q, isp_q, err_q;
  logic [LANE_W-1:0]   lane_q;
  logic [PRESET_W-1:0] pre_q;
  tx_taps_t            taps_q;
 
  assign out_valid        = v_q;
  assign out_lane         = lane_q;
  assign out_is_preset    = isp_q;
  assign out_preset       = pre_q;
  assign out_taps         = taps_q;
  assign lane_range_error = err_q;
 
  wire fire     = v_q && out_ready;
  wire can_take = !v_q || out_ready;
  assign in_ready = can_take;
  wire accept = in_valid && can_take && lane_legal;
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      v_q <= 1'b0; lane_q <= '0; isp_q <= 1'b0; pre_q <= '0;
      taps_q <= '0; err_q <= 1'b0;
    end else begin
      // Capture has priority over drain, so a same-cycle accept-and-consume
      // holds the new request rather than dropping it.
      if (accept) begin
        v_q <= 1'b1;
        // THE WHOLE DESCRIPTOR IS CAPTURED TOGETHER. Nothing downstream
        // re-reads the controller's live outputs: the lane a request names
        // must not change while the request waits (P6).
        lane_q <= in_lane;
        isp_q  <= in_is_preset;
        pre_q  <= in_preset;
        taps_q <= in_taps;
      end else if (fire) begin
        v_q <= 1'b0;
      end
 
      if (in_valid && !lane_legal) err_q <= 1'b1;
    end
  end
 
endmodule

// SYNTHESIZABLE. Illustrative adaptation control around a PHY macro.
// The QUALITY METRIC is an abstraction: real margin measurement is done
// by dedicated circuitry (section 1's eye monitor), and this block only
// consumes a normalized scalar. Thresholds and the attempt limit are
// ILLUSTRATIVE POLICY -- no PCIe constant appears here.
module eq_adaptation #(
  parameter int Q_W       = 8,
  parameter int MAX_TRIES = 4,
  parameter int TRY_W     = (MAX_TRIES <= 1) ? 1 : $clog2(MAX_TRIES+1)
) (
  input  logic clk,
  input  logic rst_n,
 
  input  logic             eq_start,
 
  output logic             apply_valid,
  input  logic             apply_ready,
  input  logic             apply_done,     // macro reports setting applied
 
  input  logic             quality_valid,
  input  logic [Q_W-1:0]   quality,
  input  logic [Q_W-1:0]   quality_target,
 
  output logic             eq_success,
  output logic             eq_fail,
  output logic [TRY_W-1:0] attempts
);
 
  typedef enum logic [2:0] {
    S_IDLE, S_APPLY, S_SETTLE, S_MEASURE, S_ACCEPT, S_FAIL
  } st_e;
 
  st_e              st_q;
  logic [TRY_W-1:0] try_q;
  logic [Q_W-1:0]   best_q;
 
  assign apply_valid = (st_q == S_APPLY);
  // SUCCESS AND FAIL ARE STATES, NOT FLAGS -- they cannot both assert.
  assign eq_success  = (st_q == S_ACCEPT);
  assign eq_fail     = (st_q == S_FAIL);
  assign attempts    = try_q;
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      st_q <= S_IDLE; try_q <= '0; best_q <= '0;
    end else begin
      unique case (st_q)
        S_IDLE :
          if (eq_start) begin st_q <= S_APPLY; try_q <= '0; best_q <= '0; end
 
        S_APPLY :
          if (apply_ready) st_q <= S_SETTLE;
 
        // ==============================================================
        // A MEASUREMENT MUST BELONG TO THE SETTING THAT PRODUCED IT.
        //
        // The macro needs time to apply a setting and the channel needs
        // time to settle. Consuming a quality result before apply_done
        // attributes the OLD setting's measurement to the NEW setting --
        // so the loop optimises a SHIFTED function, converges, and
        // reports success on a setting it never measured (section 18).
        // ==============================================================
        S_SETTLE :
          if (apply_done) st_q <= S_MEASURE;
 
        S_MEASURE :
          if (quality_valid) begin
            if (quality >= quality_target) begin
              st_q <= S_ACCEPT; best_q <= quality;
            end else if (try_q == TRY_W'(MAX_TRIES-1)) begin
              // BOUNDED. Retrying forever would hold the Link in
              // adaptation on a channel that cannot meet the target --
              // which must be reported, not hidden in a loop.
              st_q <= S_FAIL;
            end else begin
              try_q <= try_q + TRY_W'(1);
              if (quality > best_q) best_q <= quality;
              st_q  <= S_APPLY;
            end
          end
 
        S_ACCEPT, S_FAIL :
          if (eq_start) begin st_q <= S_APPLY; try_q <= '0; best_q <= '0; end
 
        default : st_q <= S_IDLE;
      endcase
    end
  end
 
endmodule

// VERIFICATION-ONLY. A three-tap channel and a three-tap transmit filter,
// in explicit signed fixed point.
// FORMAT: Q1.7 -- one sign bit, seven fractional bits, so 1.0 is 8'sd128
// and 0.30 is 8'sd38. Coefficients and samples share the format.
package eq_model_pkg;
 
  localparam int FRAC = 7;
  localparam int ONE  = 1 << FRAC;            // 128 == 1.0
 
  // ==================================================================
  // THE FORMAT MUST HOLD THE VALUES. This is not a formality, and it is
  // the first thing to get wrong.
  //
  // A "Q1.7" 8-bit signed value spans -1.0 to +0.992: it CANNOT REPRESENT
  // +1.0. A main tap of 1.0 and bipolar symbols of +/-1.0 both overflow
  // it, and the result saturates silently -- every number comes out
  // slightly small and nothing reports a problem (section 18, mutation 9).
  //
  // So coefficients get integer headroom, and samples get more again,
  // because a four-tap sum of unit symbols can reach +/-1.5 here.
  // ==================================================================
  localparam int COEF_W = 10;                 // Q3.7 : -8.00 .. +7.99
  localparam int SAMP_W = 12;                 // Q5.7 : -16.0 .. +15.99
  localparam int ACC_W  = COEF_W + SAMP_W + 2;
 
  typedef logic signed [SAMP_W-1:0] samp_t;
  typedef logic signed [COEF_W-1:0] coef_t;
  typedef logic signed [ACC_W-1:0]  acc_t;
 
  // ONE rounding point, at the end, with explicit saturation. Note the
  // ARITHMETIC shift: >> would shift zeros into the sign position and
  // turn every negative result into a large positive one.
  function automatic samp_t to_samp(input acc_t a);
    acc_t r;
    r = (a + acc_t'(1 << (FRAC-1))) >>> FRAC;
    if (r >  acc_t'( (1<<(SAMP_W-1)) - 1 )) return samp_t'( (1<<(SAMP_W-1)) - 1 );
    if (r <  acc_t'(-(1<<(SAMP_W-1))     )) return samp_t'(-(1<<(SAMP_W-1)));
    return samp_t'(r);
  endfunction
 
  // rx[n] = h0*x[n+1] + h1*x[n] + h2*x[n-1] + h3*x[n-2]
  //          pre-cursor  main     post 1      post 2
  function automatic samp_t channel(
      input samp_t x_next, x_cur, x_p1, x_p2,
      input coef_t h0, h1, h2, h3);
    acc_t acc;
    // EVERY PRODUCT ACCUMULATED AT FULL WIDTH. No intermediate narrowing
    // anywhere before the single rounding step.
    acc = acc_t'(x_next) * acc_t'(h0)
        + acc_t'(x_cur ) * acc_t'(h1)
        + acc_t'(x_p1  ) * acc_t'(h2)
        + acc_t'(x_p2  ) * acc_t'(h3);
    return to_samp(acc);
  endfunction
 
  // y[n] = c_pre*x[n+1] + c_main*x[n] + c_post*x[n-1]
  // THE TRANSMITTER MAY USE x[n+1] BECAUSE IT ALREADY HAS IT (section 4).
  function automatic samp_t tx_fir(
      input samp_t x_next, x_cur, x_prev,
      input coef_t c_pre, c_main, c_post);
    acc_t acc;
    acc = acc_t'(x_next) * acc_t'(c_pre )
        + acc_t'(x_cur ) * acc_t'(c_main)
        + acc_t'(x_prev) * acc_t'(c_post);
    return to_samp(acc);
  endfunction
 
endpackage

import eq_model_pkg::*;
 
// VERIFICATION-ONLY. Decision-feedback equalization over already-decided
// symbols, with error propagation deliberately representable.
// Five taps matches the vendor implementation quoted in section 1; the
// arithmetic here is this model's, not a claim about that device.
module dfe_model #(
  parameter int TAPS = 5
) (
  input  samp_t sample,                   // post-CTLE sample
  input  coef_t tap      [TAPS],          // signed, Q3.7
  // PREVIOUS decisions, decision[0] most recent. NOT the current one: a
  // DFE using its own current decision would subtract a quantity derived
  // from the value it is computing.
  input  samp_t decision [TAPS],
 
  output samp_t corrected,
  output logic  bit_out
);
 
  acc_t acc;
  always_comb begin
    acc = acc_t'(sample) <<< FRAC;        // bring sample to accumulator scale
    for (int k = 0; k < TAPS; k++)
      acc -= acc_t'(tap[k]) * acc_t'(decision[k]);
    corrected = to_samp(acc);
  end
 
  // The slicer. In real hardware this is an analog comparator with offset
  // and noise; here it is a sign test -- which is exactly why this model
  // says nothing about BER.
  assign bit_out = (corrected >= 0);
 
endmodule

// SVA over tx_eq_config, eq_request_hold and eq_adaptation. These assert
// the CONTROL-PLANE contract. They assert NOTHING about analog
// convergence, eye margin, BER, or that equalization succeeds -- all of
// which depend on a physical channel this design does not control.
 
// ---- ENVIRONMENT ------------------------------------------------------
// A1: a request is stable while offered and not accepted.
assume property (@(posedge clk) disable iff (!rst_n)
  (in_valid && !in_ready) |=> ($stable(in_lane) && $stable(in_taps)));
// A2: quality_valid pulses only for a completed measurement.
assume property (@(posedge clk) disable iff (!rst_n)
  quality_valid |-> !$isunknown(quality));
 
// ---- CONFIGURATION ATOMICITY ------------------------------------------
 
// P1: THE CHAPTER'S CENTRAL RTL PROPERTY. Taps change ONLY on an accepted
// commit -- so the transmitter never sees a partially-updated setting.
property p_taps_change_only_on_commit;
  @(posedge clk) disable iff (!rst_n)
  (!$stable(cfg_taps)) |-> $past(take_coeff);
endproperty
a_commit : assert property (p_taps_change_only_on_commit);
 
// P1b: and when they change, the WHOLE struct came from one request.
property p_taps_match_request;
  @(posedge clk) disable iff (!rst_n)
  $past(take_coeff) |-> (cfg_taps == $past(coeff_req));
endproperty
a_atomic : assert property (p_taps_match_request);
 
// P2: an UNSUPPORTED preset never reaches the macro as valid config.
property p_unsupported_never_applied;
  @(posedge clk) disable iff (!rst_n)
  (preset_valid && !SUPPORTED_PRESETS[preset_id] && !coeff_valid)
    |=> ($stable(cfg_preset) && reject_unsupported);
endproperty
a_preset : assert property (p_unsupported_never_applied);
 
// P3: OUT-OF-RANGE COEFFICIENTS never applied. Checked in SIGNED
// arithmetic -- an unsigned test accepts every negative tap.
property p_range_enforced;
  @(posedge clk) disable iff (!rst_n)
  (coeff_valid && !taps_in_range) |=> ($stable(cfg_taps) && reject_range);
endproperty
a_range : assert property (p_range_enforced);
 
// P4: the APPLIED state is always within the legal signed range -- which
// additionally catches a corrupted register, not only a bad request.
property p_applied_taps_legal;
  @(posedge clk) disable iff (!rst_n)
  cfg_valid |-> (($signed(cfg_taps.pre)  >= COEF_MIN)
              && ($signed(cfg_taps.pre)  <= COEF_MAX)
              && ($signed(cfg_taps.main) >= COEF_MIN)
              && ($signed(cfg_taps.main) <= COEF_MAX)
              && ($signed(cfg_taps.post) >= COEF_MIN)
              && ($signed(cfg_taps.post) <= COEF_MAX));
endproperty
a_legal : assert property (p_applied_taps_legal);
 
// P5: the declared same-cycle priority holds -- coefficients win.
property p_coeff_beats_preset;
  @(posedge clk) disable iff (!rst_n)
  (preset_valid && coeff_valid && taps_in_range) |=> !cfg_is_preset;
endproperty
a_priority : assert property (p_coeff_beats_preset);
 
// ---- REQUEST OWNERSHIP ------------------------------------------------
 
// P6: THE LANE A REQUEST NAMES DOES NOT CHANGE WHILE IT WAITS.
property p_lane_stable;
  @(posedge clk) disable iff (!rst_n)
  (out_valid && !out_ready) |=> (out_valid && $stable(out_lane)
                                           && $stable(out_taps));
endproperty
a_lane : assert property (p_lane_stable);
 
// P7: a held request is not replaced before it is taken.
property p_not_overwritten;
  @(posedge clk) disable iff (!rst_n)
  (out_valid && !out_ready) |=> $stable(out_preset);
endproperty
a_once : assert property (p_not_overwritten);
 
// P8: an out-of-range lane id is refused and reported, never applied.
property p_lane_range;
  @(posedge clk) disable iff (!rst_n)
  (in_valid && !lane_legal) |=> lane_range_error;
endproperty
a_lane_range : assert property (p_lane_range);
 
// ---- ADAPTATION -------------------------------------------------------
 
// P9: A MEASUREMENT BELONGS TO THE SETTING THAT PRODUCED IT. The
// controller reaches MEASURE only through SETTLE, which requires
// apply_done -- section 14's settle state, asserted.
property p_measure_only_after_settle;
  @(posedge clk) disable iff (!rst_n)
  $rose(st_q == S_MEASURE) |-> ($past(st_q) == S_SETTLE) && $past(apply_done);
endproperty
a_settle : assert property (p_measure_only_after_settle);
 
// P10: success and fail are MUTUALLY EXCLUSIVE.
property p_success_xor_fail;
  @(posedge clk) disable iff (!rst_n)
  !(eq_success && eq_fail);
endproperty
a_excl : assert property (p_success_xor_fail);
 
// P11: success is never declared before at least one represented
// measurement met the target. A controller reporting success on entry
// would look perfect and change nothing.
property p_no_success_without_measurement;
  @(posedge clk) disable iff (!rst_n)
  $rose(eq_success) |-> $past(quality_valid && (quality >= quality_target));
endproperty
a_measured : assert property (p_no_success_without_measurement);
 
// P12: BOUNDED. The attempt count never exceeds the configured limit -- a
// deterministic local bound, not a fairness assumption.
property p_attempts_bounded;
  @(posedge clk) disable iff (!rst_n)
  attempts <= TRY_W'(MAX_TRIES-1);
endproperty
a_bounded : assert property (p_attempts_bounded);
 
// P13: reset returns a defined safe state.
property p_reset;
  @(posedge clk)
  !rst_n |=> (!cfg_valid && !out_valid && !eq_success && !eq_fail);
endproperty
a_reset : assert property (p_reset);
 
// ---- SCOPE ------------------------------------------------------------
 
// P14: this controller is not an LTSSM and does not drive link state
// (section 14). An integration property, so a refactor that wires them
// together is caught rather than assumed correct.
property p_not_link_control;
  @(posedge clk) disable iff (!rst_n)
  (eq_success || eq_fail) |-> $stable(dut_ltssm.state);
endproperty
a_scope : assert property (p_not_link_control);