Setup & Hold Fundamentals in Verilog — The Physics of Capture

Chapter 18 · Section 18.1 · Timing Checks

1. The Engineering Problem

A pipeline captures the wrong value at a flop — sometimes. The combinational logic is correct, the connections are right, and at the typical corner it even works. But occasionally the captured value is unpredictable, and on slow silicon it is reliably wrong. The logic never changed. So what is failing?

   // launch flop → combinational logic → capture flop
   //
   //   q_launch changes tcq after the clock edge, the logic takes tlogic,
   //   so new data reaches the capture flop's D at  (edge + tcq + tlogic).
   //
   //   If that arrival is too CLOSE to the NEXT clock edge, the capture
   //   flop's data is not stable in time — a SETUP violation — and the
   //   flop may capture an UNPREDICTABLE value, not a wrong-but-defined one.

Nothing about the function is wrong. What failed is timing: the data arrived too close to the clock edge for the flop to capture it reliably. Every flip-flop demands its data be stable for a window around the edge, and when that demand is broken, the flop does not simply capture old or new — it can go metastable.

A flip-flop requires its data to be stable for a setup time before the clock edge and a hold time after it. A change inside that window can drive the flop metastable — hovering between 0 and 1 before resolving randomly. Setup and hold are the physical capture requirement behind every timing check.

2. Mental Model — A Keepout Window Around the Clock Edge

3. The Hardware View

Setup and hold are properties of a launch–capture pair: one flop launches data, combinational logic transforms it, and a second flop captures it on the next edge.

Visual A — the launch–capture path and its budget

Visual B — the keepout window

4. Setup Time

Setup time (tsu) is how long the data must be stable before the active clock edge. A setup violation happens when the data arrives too late — it is still changing within tsu of the edge.

• Cause: a long data path. The launch-to-capture journey (tcq + tlogic) eats so much of the clock period that the data does not settle with tsu to spare before the next edge.
• Worst at the slow (max) corner (17.3), where delays are longest — which is why setup is checked at the slow corner.
• Fixes: shorten the path (simpler/faster logic), add a pipeline stage to split the logic, or lengthen the clock period (slow the clock). Setup has slack you can buy with a longer period.

Setup answers: did the data make it in time for this edge?

5. Hold Time

Hold time (th) is how long the data must remain stable after the active clock edge. A hold violation happens when the data changes too soon — it moves within th of the edge that was supposed to capture the old value.

• Cause: a short data path (new data races through to the capture flop almost immediately) and/or clock skew (the capture flop's clock arrives late, so the new data beats it).
• Worst at the fast (min) corner (17.3), where delays are shortest — which is why hold is checked at the fast corner.
• Fixes: add delay to the data path (buffers) so the new data arrives after the hold window, or fix the clock skew.
• Cannot be fixed by changing the clock period. This is the crux: hold is a race between data and clock at the same edge — the clock period never enters the equation. Slowing the clock does nothing for a hold violation (§11 DebugLab).

Hold answers: did the old data survive long enough to be captured before the new data arrived?

6. Metastability — What a Violation Actually Causes

A flip-flop captures by driving an internal feedback node to one of two stable states. Given enough time (the setup/hold window), that node resolves cleanly to 0 or 1. If the data changes inside the window, the node can be left balanced between the two states — metastable — like a ball balanced on a knife edge.

• A metastable node eventually "falls" to 0 or 1, but when and which are unpredictable — the resolution time is, in principle, unbounded (it follows an exponential probability).
• Downstream logic sampling a still-metastable output sees a value that is neither cleanly 0 nor 1, and different gates may even interpret it differently.
• Simulation models metastability as X — the honest representation of "unpredictable." A fired setup/hold timing check forces the captured value to X precisely because the real flop's output is, for that capture, unknowable.

This is why a setup/hold violation is not a "wrong but defined" result — it is a nondeterministic one, and X is how the model tells you so.

7. The Timing Equations

Setup and hold each impose an inequality on the launch–capture path. With clock period Tclk, clock-to-Q tcq, logic delay tlogic, setup tsu, hold th, and clock skew tskew:

   SETUP:  Tclk  >=  tcq + tlogic(max) + tsu - tskew
           (the long path must fit in one period, with setup to spare)
 
   HOLD:   tcq + tlogic(min)  >=  th + tskew
           (the short path must outlast the hold window — NO Tclk term!)

Read what each tells you:

• Setup bounds the longest path: it must fit inside the clock period. A longer Tclk relaxes setup — you can always slow the clock to meet setup.
• Hold bounds the shortest path: the new data must not arrive before the hold window closes. Tclk does not appear — hold is a same-edge race, independent of clock frequency. No clock speed makes a hold violation better or worse.
• Skew has opposite signs in the two: positive skew (capture clock late) helps setup but hurts hold.

8. Setup vs Hold — The Contrast

The single most important row is "Depends on Tclk?" — it is the difference that traps engineers who assume every timing problem is solved by slowing the clock.

9. Clock Skew's Role

Clock skew is the difference in clock arrival time between the launch flop and the capture flop. It pushes setup and hold in opposite directions:

• If the capture clock arrives later than the launch clock (positive skew toward capture): the capture edge effectively moves later, giving the data more time to settle — setup is easier — but the old data now has less margin after the launch edge — hold is harder.
• The reverse skew helps hold and hurts setup.

This is why skew is a first-class timing concern: reducing it is not universally good — a clock tree is balanced to trade setup and hold margins deliberately, and skew appears (with opposite signs) in both equations of §7.

10. Common Misconceptions

1. "Any timing violation is fixed by slowing the clock." False. Slowing the clock fixes setup, never hold — hold has no clock-period term (§5, §7, DebugLab).
2. "A violation gives a wrong-but-defined value." False. It can drive the flop metastable, whose outcome is nondeterministic; simulation models it as X (§6).
3. "Setup and hold are checked at the same corner." False. Setup is worst at the slow corner; hold at the fast corner — they are checked at opposite corners (§4, §5).
4. "Less clock skew is always better." Misleading. Skew trades setup against hold; a clock tree balances it deliberately (§9).

11. Debugging Lab

12. Interview Q&A

13. Exercises

Exercise 1 — Which violation?

For each, name setup or hold: (a) data arrives 0.2 ns before the edge but the flop needs 0.5 ns of setup; (b) two flops with no logic between them and the capture clock arrives late; (c) a long arithmetic path that does not settle before the next edge.

Exercise 2 — Apply the equations

A path has tcq = 0.3 ns, tlogic(max) = 4 ns, tsu = 0.4 ns, and tskew = 0. What is the minimum clock period that meets setup? Does a tlogic(min) = 0.1 ns, th = 0.5 ns path meet hold?

Exercise 3 — The wrong lever

A teammate is fixing a hold violation by increasing the clock period and it is not working. Explain why, and give two fixes that would work.

Exercise 4 — Why X?

Explain why a fired setup check forces the captured value to X rather than to the old or new data value.

14. Summary

Setup and hold are the physical capture requirement behind every timing check:

• Setup (tsu) — data stable before the edge; violated by data too late (a long path); worst at the slow corner; relaxed by a longer clock period.
• Hold (th) — data stable after the edge; violated by data too soon (a short path / skew); worst at the fast corner; independent of the clock period — fixed only by adding path delay or reducing skew.
• The window — [edge - tsu, edge + th]; a change inside it risks metastability, an unpredictable resolution that simulation models as X.
• The equations — Tclk >= tcq + tlogic + tsu (setup, has Tclk) and tcq + tlogic >= th (hold, no Tclk); skew has opposite signs in each.

The crux to keep: setup buys margin from the clock period; hold buys it from path delay and skew — opposite problems, opposite cures.

The next sub-topic puts this concept into Verilog: Chapter 18.2 $setup, $hold & $setuphold — the synchronous timing-check tasks that watch this window, how they are written, and the reference edge they measure against.

Related Tutorials

• Timing Checks — Chapter 18 overview; the family of checks this concept anchors.
• Min:Typ:Max & Rise/Fall/Turn-off Delays — Chapter 17.3; why setup is checked at the slow corner and hold at the fast corner.
• Module Path Delays & the specify Block — Chapter 17.4; the specify block where the $setup/$hold checks live.
• Blocking and Non-Blocking Assignments — Chapter 14.3; the non-blocking rule that keeps RTL flops race-free — the logical cousin of the physical hold requirement.