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Verilog · Chapter 17.3 · Delay Modeling

Min:Typ:Max & Rise/Fall/Turn-off Delays in Verilog — Corners & Transition Delay

A single delay number is a convenient fiction that hides two truths about real silicon. First, a cell's delay is not one value. It spans a range across manufacturing corners, voltage, and temperature, so Verilog lets a delay carry three values, written min then typ then max, for fast, typical, and slow, and the simulator runs at one chosen corner. Second, a gate rarely switches at the same speed in both directions, because the pull-up and pull-down networks differ, so Verilog lets a delay give separate rise, fall, and turn-off values. Turn-off covers transitions to high impedance on tri-state outputs. These ideas combine, since each rise, fall, and turn-off value can itself be a triplet. This page shows both forms, how a corner is chosen at run time, and the trap of passing at typical and failing at slow.

Intermediate13 min readVerilogDelay ModelingMin Typ MaxProcess CornersRise Fall Delay

Chapter 17 · Section 17.3 · Delay Modeling

1. The Engineering Problem

A team models a path with a single delay, runs gate-level simulation, and it passes. The same path, on slow silicon a few weeks later, fails — a flop captures late data and the design malfunctions. Nothing in the model changed. So how did one delay number pass in simulation and fail in the lab?

one-number-is-a-lie.v
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Snippet
   // The path was modelled with ONE delay:
   and #2 g (data_q, sel, data);   // "2 ns" — but 2 ns at WHICH corner?
 
   // Real silicon delay is NOT a single number. The same cell is:
   //   ~1 ns on FAST silicon (high voltage, low temperature)
   //   ~2 ns at the TYPICAL corner
   //   ~5 ns on SLOW silicon (low voltage, high temperature)
   //
   // The model captured only "typical". The slow corner — where the
   // setup path actually fails — was never in the model, so it was never
   // simulated.

A single delay is a fiction in two ways at once: it pretends a cell has one delay (it has a range across corners), and it pretends a gate switches at the same speed rising and falling (it usually does not). Verilog gives you both axes.

min:typ:max carries three corner values for one delay, and the simulator runs at one chosen corner; rise:fall:turn-off lets a gate switch at different speeds in each direction. A design that passes at the typical corner can still fail at the slow corner — which is exactly why the three values exist.

2. Mental Model — Three Corners, and Three Directions

3. The Hardware View

The two axes correspond to two physical realities.

Visual A — min:typ:max: one delay, three corners

Min:Typ:Max — three corners of one delay; the simulator picks one

data flow
Min:Typ:Max — three corners of one delay; the simulator picks onemin — fastsiliconhigh V, low T —shortest delaytyp — nominalthe default cornermax — slowsiliconlow V, high T —longest delayone corner perrunchosen by +mindelays / +typdelays / +maxdelayschosen by +mindelays /+typdelays /…
A min:typ:max delay carries three corner values. The simulator applies ONE of them to the entire run — fast (min), typical (typ, the default), or slow (max) — selected by a command-line plusarg. To trust a design you must run more than the default corner.

Visual B — rise/fall/turn-off: direction-dependent delay

Rise / Fall / Turn-off — delay depends on the transition direction

data flow
Rise / Fall / Turn-off — delay depends on the transition directionrisetransition to 1falltransition to 0turn-offtransition to z(tri-state only)
A gate can switch at different speeds in each direction: the rise delay applies to transitions to 1, the fall delay to transitions to 0, and the turn-off delay to transitions to high-impedance z (only meaningful for tri-state outputs). A transition to x uses the smallest applicable delay.

4. Min:Typ:Max Delays

A delay value can be written as three colon-separated numbers — min:typ:max:

minmaxtyp.v
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Snippet
   and #(1:2:5) g (out, a, b);     // min=1, typ=2, max=5  (one transition delay)
   assign #(2:3:4) y = a & b;      // works on continuous assigns too
  • min — the delay on the fastest corner (fast process, high voltage, low temperature).
  • typ — the typical/nominal delay.
  • max — the delay on the slowest corner (slow process, low voltage, high temperature).

The simulator selects one corner for the entire run, via a command-line option:

corner selection (simulator command line)
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Snippet
   +mindelays     →  use the min value of every triplet      (fast corner)
   +typdelays     →  use the typ value  (this is the DEFAULT) (nominal)
   +maxdelays     →  use the max value of every triplet       (slow corner)

If you pass none, every triplet collapses to its typ value. This is the quiet trap: run the simulation with no corner flag, and you have only ever tested the typical corner — not the slow corner where setup paths are tightest, nor the fast corner where hold paths are tightest.

5. Rise/Fall/Turn-off Delays

A delay can also specify different values for different transition directions. There are three forms, by count:

rise-fall-turnoff.v
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Snippet
   and    #5        g1 (o, a, b);       // one value: ALL transitions = 5
   and    #(2, 3)   g2 (o, a, b);       // two values: rise=2, fall=3
   bufif1 #(2, 3, 4) g3 (o, a, en);     // three values: rise=2, fall=3, turnoff=4

Which delay applies to which transition:

TransitionDelay used
to 1 (0→1, x→1, z→1)rise
to 0 (1→0, x→0, z→0)fall
to z (high-impedance)turn-off — tri-state outputs only
to x (unknown)the smallest of the applicable delays (pessimistic)
  • Two-value form (rise, fall) is the common case for ordinary logic — pull-up and pull-down differ, but there is no high-impedance state.
  • Three-value form (rise, fall, turnoff) is only meaningful for gates that can drive z — the tri-state primitives (bufif0/bufif1/notif0/notif1) and nets. The turn-off delay is how long the output takes to release to high-impedance.
  • Transition to x takes the smallest applicable delay, so unknowns appear as early as possible — a deliberately pessimistic choice that makes x hazards easier to catch.

6. Combining Both Forms

The corner axis and the direction axis are orthogonal — each rise/fall/turn-off value can itself be a min:typ:max triplet:

combined.v — direction AND corner together
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Snippet
   // rise = 1:2:3, fall = 4:5:6, turnoff = 7:8:9
   bufif1 #(1:2:3, 4:5:6, 7:8:9) g (out, in, en);
 
   // rise = 2:3:4, fall = 5:6:7  (two-value, each a corner triplet)
   and #(2:3:4, 5:6:7) g2 (o, a, b);

Read it as a small table: the commas separate directions (rise, fall, turn-off); the colons within each group separate corners (min, typ, max). With +maxdelays, gate g above rises in 3, falls in 6, and turns off in 9; with the default (typ), it rises in 2, falls in 5, turns off in 8. This is exactly the shape that back-annotated cell timing (SDF) uses — per-direction, per-corner.

7. Why Corners Matter

In a real flow, min:typ:max is not a curiosity — it is the backbone of timing sign-off.

  • The slow (max) corner is where setup fails. When the clock period is fixed, the longest delays decide whether data arrives in time. Static timing analysis (STA) checks setup at the slow corner; gate-level simulation of the slow corner reproduces the same stress.
  • The fast (min) corner is where hold fails. The shortest delays decide whether data arrives too early and races through a flop. Hold is checked at the fast corner.
  • The typical corner proves neither. A green run at typ — the default — exercises the middle of the range and can completely miss both failure corners. "It passed in simulation" is meaningless unless you say which corner.
  • SDF back-annotation supplies the triplets. After layout, characterized min:typ:max delays per cell and per direction are back-annotated onto the netlist, and gate-level simulation is run at the corners that matter — not just the default.

The discipline: a single delay, or a single (typ) run, is never a sign-off. You exercise the corners deliberately.

8. Common Mistakes

  1. Running only the default (typ) corner and trusting it. The slow and fast corners — where setup and hold fail — were never simulated (§4, §7, DebugLab).
  2. Writing a single delay for a path that must meet timing. One number hides the corner range; the slow corner that fails is simply absent from the model (§1).
  3. Putting a turn-off value on a gate that cannot drive z. Turn-off is only meaningful for tri-state primitives/nets; on ordinary logic it is ignored (§5).
  4. Confusing the commas and colons. Commas separate directions (rise, fall, turn-off); colons separate corners (min:typ:max). #(1:2:3, 4:5:6) is rise-triplet, fall-triplet — not six independent numbers (§6).
  5. Expecting any of this to synthesise. All delay values are simulation-only; synthesis ignores them (Chapter 17 overview).

9. Debugging Lab

The design that passed at typ and failed at the slow corner

Pitfall — only the default (typ) corner was ever simulated
Buggy Code
// A cell on a setup-critical path is modelled with a min:typ:max delay.
// typ = 2 ns, but the SLOW corner is 5 ns.
module capture_path (output reg q, input clk, sel, d_a, d_b);
  wire muxed;
  // Mux cell: min=1, typ=2, max=5  (slow corner is 5 ns)
  assign #(1:2:5) muxed = sel ? d_a : d_b;

  always @(posedge clk)
      q <= muxed;          // flop samples the muxed data
endmodule

// Clock period is 4 ns. The team runs gate-level simulation with the
// DEFAULT corner (no plusarg → typ = 2 ns):
//
//   typ corner: muxed settles 2 ns after sel/data change — comfortably
//   before the next clock edge. q captures correct data. PASS.
//
// The team signs off on this green run. On slow silicon (and in a later
// +maxdelays run), muxed takes 5 ns — LONGER than the 4 ns clock period —
// so it has not settled when the clock edge arrives. q captures stale or
// metastable data. FAIL.
Symptom

Gate-level simulation passes — q always captures the correct muxed value. The design is signed off. But slow-corner silicon (and a later max-corner GLS run) fails: q captures wrong or unknown values on the setup-critical path. The model was never changed between the passing and failing runs.

Root Cause

The mux delay was correctly modelled as min:typ:max = 1:2:5, but the simulation only ever ran at the DEFAULT corner — typ = 2 ns — because no corner plusarg was passed. At 2 ns the muxed data settles well within the 4 ns clock period, so setup is met and the run is green.

The failing corner is MAX = 5 ns. There, the data takes longer to settle than the entire clock period (4 ns), so it arrives after the clock edge needs it — a setup violation — and the flop captures stale/metastable data. That corner was present in the MODEL the whole time, but it was never SELECTED, so it was never simulated.

The min:typ:max triplet exists precisely so you can run the corners that fail. Running only the default proves the design works in the easy middle of the range and says nothing about the slow corner where setup is tightest. "It passed in simulation" is meaningless without naming the corner.

Fix
// FIX 1 — actually run the corners. Don't trust the default (typ) alone:
//
//   simulate +maxdelays   // slow corner → exposes the setup failure
//   simulate +mindelays   // fast corner → exposes hold failures
//   simulate +typdelays   // nominal (the default)
//
// The +maxdelays run now FAILS in simulation, surfacing the bug before
// tape-out instead of after.
//
// FIX 2 — fix the actual timing problem the slow corner revealed: the
// path must meet setup at the SLOW corner, not just at typ. Either the
// clock period must accommodate the 5 ns max delay, or the path must be
// made faster (the muxed logic shortened / re-pipelined) so that even
// max-corner delay settles within the clock period.
//
// Lesson: a green simulation at one corner is not sign-off. min:typ:max
// is the menu of corners; you must deliberately run the ones that fail
// (max for setup, min for hold), not just the default.

10. Interview Q&A

11. Exercises

Exercise 1 — Read the delay

For notif1 #(2:3:4, 5:6:7, 8:9:10) g (o, in, en);, state the rise, fall, and turn-off delays at each of the three corners.

Exercise 2 — Pick the corner

For each goal, name the corner (min/typ/max) and the plusarg: (a) stress the tightest setup paths; (b) stress the tightest hold paths; (c) a quick nominal sanity run.

Exercise 3 — Commas vs colons

Explain in one sentence the difference between #(1:2:3) and #(1, 2, 3).

Exercise 4 — Explain the trap

A teammate says "gate-level sim is green, we're good to tape out." Their run used no corner flag. Explain in two sentences why the green run is not sufficient.

12. Summary

A single delay number hides two truths; min:typ:max and rise/fall/turn-off restore them:

  • min:typ:max — three corner values (fast / typical / slow). The simulator runs the whole simulation at one corner, chosen by +mindelays / +typdelays / +maxdelays, defaulting to typ.
  • rise / fall / turn-off — direction-dependent delay: rise to 1, fall to 0, turn-off to z (tri-state only); a transition to x uses the smallest applicable delay.
  • They combine — each direction value can be a min:typ:max triplet; commas separate directions, colons separate corners.
  • The trap — setup fails at the slow (max) corner, hold at the fast (min) corner; a default (typ) run tests neither. Name the corner, or the result is meaningless.

All of this is simulation-only and mirrors the per-direction, per-corner shape of back-annotated SDF timing.

The final sub-topic of this chapter makes delay precise per input-to-output pin: Chapter 17.4 Module Path Delays & the specify Block — how real standard cells are timed, and the construct that will host Chapter 18's timing checks.