“Chiplets Are Always Cheaper”

The argument that persuades everyone is the yield curve, and it deserves to. Defect density against die area is one of the most compelling relationships in semiconductor economics, and every part of it is true. The mistake is not believing the curve — it is believing the curve is the equation.

1. The Belief

"Splitting a big die into chiplets improves yield, and better yield means lower cost. So chiplets are cheaper."

Both premises are correct. The conclusion does not follow, because the first premise is about silicon cost and the conclusion is about total cost — and the terms in between move in the opposite direction.

The replacement model (§6):

Total cost per working product = Σ(die cost ÷ die yield) + package + assembly cost ÷ assembly yield + known-good-die test + NRE ÷ volume.

Chiplets trade silicon cost for packaging, test and integration cost. The trade wins above a crossover — and below it, it loses.

That model tells you what to compute. "Chiplets aren't always cheaper" tells you nothing.

2. Why a Competent Engineer Believes It

The yield mathematics is genuinely dramatic, and it is the first thing anyone learns about chiplets.

The curve is steep in the region that matters. Under a simple Poisson model, yield falls exponentially with area — so at large die sizes, halving the area does far more than halve the loss. An engineer who works that arithmetic once is permanently and correctly impressed.

Every introduction leads with it. Yield is the most-repeated justification for chiplets in papers, talks and internal decks. Repetition establishes it as the reason rather than a reason.

Large companies visibly do it, and their products work. 26.1 §4 documents AMD shipping compute dies with 2 of 40 compute units disabled "for yield management" — an architecture that plans for defective silicon. That is real, Class-A evidence that yield economics drives partitioning.

And the omitted terms are invisible from a design desk. Substrate cost, assembly yield, known-good-die test time, and integration NRE do not appear in any tool an RTL or architecture engineer uses. The terms that survive the split are the ones you can see; the ones that grow are on someone else's spreadsheet.

One structural reason, worth naming. The engineer proposing the split is rarely the person who owns the packaging and test budget. The belief is not just a misunderstanding — it is what an organisational boundary looks like from one side.

3. The Hidden Assumption

That die cost is the whole cost — that packaging, assembly yield, test and integration effort are constants unaffected by how many dies the product contains.

Three sub-assumptions.

A — that packaging cost is fixed. It is not: more dies means more substrate area, more interconnect, and frequently a more advanced (more expensive) packaging technology.

B — that assembly always succeeds. It does not, and assembly yield compounds with die count (§8) — a term with no analogue in a monolithic design.

C — that a die is either good or scrap. This is the assumption with an RTL consequence (§10): whether a partially defective die can be sold is a design decision, not a manufacturing outcome.

4. The Root-Cause Tree

Note the two branches. The economic error (partition the wrong die) and the design error (no harvest path) come from different sub-assumptions, and the second one silently removes the benefit the first one was chasing — a die with no harvest path captures only part of the yield advantage that justified splitting it.

5. Sourcing and Scope

6. The Cost Equation

Three readings.

The yield argument is correct about exactly one row and silent about five. That is the whole misconception, expressed as a table.

Row 5 is the one that punishes low volume hardest. NRE divides by volume, so a split that is clearly correct at high volume can be clearly wrong at low volume with identical silicon — the die areas, the defect density and the yields are all the same, and the answer flips. Volume is an input to a partitioning decision, which is not how partitioning is usually discussed.

And row 4 hides a second-order effect. Known-good-die testing must be more thorough than final test for a monolithic part, because a bad die discovered after assembly destroys the whole package, including the good dies in it. Escape cost rises with die count, so test cost is not merely multiplied — it is multiplied and then increased.

7. The Minimal Counterexample

The smallest system where the belief predicts a saving and reality produces a loss: a die that was never yield-limited.

Case A — the large die, where the belief is right.

Case B — the small die, same process, same defect density.

Same process, same defect density, same yield curve, opposite conclusion.

Four readings.

The yield saving in Case B is real and it is 2.5 %. The belief is not wrong about the direction — it is wrong about the magnitude relative to what the split costs, and the added packaging term is roughly a hundred times larger than the saving it bought.

The curve's steepness is the whole story. At 6 cm² the exponential is in its punishing region and halving area recovers a great deal. At 0.5 cm² the die was already at 95 % yield, so there was almost nothing to recover — and you cannot save what you were not losing.

The crossover is a real number you can compute, and computing it is the actionable replacement for the belief. Set silicon-yield saving equal to added packaging and assembly cost and solve for area — the answer depends on D₀, on the packaging technology, and on volume through the NRE term (§6 row 5).

And the honest framing for a review: the question is never "are chiplets cheaper?" It is "at this die size, this defect density, this packaging technology and this volume, which side of the crossover are we on?" — five inputs, and the belief supplies one.

8. Assembly Yield Compounds

The term with no monolithic analogue, and the one that punishes many-die partitions specifically.

If each die-attach step succeeds with probability y, a package with n dies assembles successfully with probability y^n (assuming independence — a simplification, and the real dependence structure makes clustering worse rather than better).

Three readings.

At y = 0.97, a twelve-die package loses roughly 31 % of assemblies — and each loss discards every die in it, including good ones. The scrap cost is the sum of the dies, not the cost of one.

Which makes known-good-die testing economically load-bearing rather than a quality nicety (§6 row 4). Every defective die that reaches assembly destroys its packagemates, so KGD confidence must rise as die count rises — and that is a test-cost increase driven purely by the partition decision.

And this is why "more chiplets is more better" is a distinct and worse version of the belief. The silicon term keeps improving with finer splits, slowly, while the assembly term degrades geometrically. 26.1 §7's hub-and-spoke costs and 26.3 §6's reticle argument both sit inside this constraint: there is an optimum die count, and it is not "as many as possible."

9. Architectural Consequence

Three readings.

Row 3 is the decision that quietly forfeits the benefit. A die with no harvest path captures only part of the yield advantage that justified splitting it — every die with a single defective unit is scrapped rather than sold as a lower-tier part. 26.1 §4's 38-of-40 is the counter-practice, in a shipping product.

Row 6 is the input most often missing from a partitioning discussion entirely. NRE ÷ volume can flip the answer with identical silicon, so "should we go chiplet?" is not answerable without a volume forecast — which makes it a business decision wearing an architecture costume.

And row 7 is what row 3 produces downstream. If harvested parts are real SKUs, they are real verification and performance targets — and §12 is what happens when only the full configuration was ever modelled.

10. RTL Consequence — a Design That Cannot Be Harvested

The code that follows naturally from assuming a die is either good or scrap: everything is fixed, because every instance is identical.

// WRONG. ILLUSTRATIVE. A link datapath with a hardcoded lane map and a fixed
// resource count. There is nothing wrong with this code in a world where every
// die is perfect — and that world is the hidden assumption (§3, assumption C).
localparam int N_LANE = 16;
localparam int N_UNIT = 40;
 
// BUG 1: lane n is wired to physical lane n, forever. One defective physical
//        lane makes the entire die unusable — there is no way to route around it.
always_comb
  for (int l = 0; l < N_LANE; l++)
    tx_phys[l] = tx_logical[l];
 
// BUG 2: the active unit count is a compile-time constant. A die with one
//        defective unit cannot be configured as a 39-unit part; it is scrap.
assign active_unit_mask = {N_UNIT{1'b1}};
 
// BUG 3: capability reported to software is the constant, not what this
//        instance actually has. A harvested die would lie about itself.
assign reported_units = N_UNIT[7:0];

Architecture. A datapath in which every instance is assumed identical to every other. There is no per-die state, so there is nothing a partially defective die could be configured into.

State. None — and that absence is the defect. A harvestable design needs per-instance state establishing what this die actually has.

Event. Fixed at elaboration. Nothing at manufacture or boot can change it.

Contract. It assumes the manufactured die matches the design exactly. That assumption is false for a measurable fraction of every wafer, and the fraction rises with area — which is the same curve the chapter opened with.

Failure — the economics, not a timeline. With D₀ = 0.1/cm² and a 3.0 cm² die (§7 Case A), about 26 % of dies have at least one defect. With this RTL, all of them are scrap.

A 21 % improvement in sellable dies, from a design decision, on identical silicon. That improvement is a substantial share of the benefit the split was undertaken to obtain (§7 Case A recovered ≈13 % in total cost) — so a chiplet program with no harvest path forfeits much of its own justification.

DV/debug. The symptom is not a bug report; it is a yield review in which the sellable fraction is far below the die yield, and nobody in the room owns the gap. The discriminator is the ratio of scrapped to defective — if they are equal, the design has no harvest path, and that is an RTL finding surfacing as a manufacturing number.

11. Corrected — Configurability as a Yield Feature

// CORRECT. ILLUSTRATIVE. Per-instance configuration established at manufacture
// and read at boot. The design intent is explicit: a die with a small number of
// defects is a LOWER-TIER PRODUCT, not scrap.
localparam int N_LANE       = 16;
localparam int N_LANE_SPARE = 2;                 // physical lanes beyond logical
localparam int N_PHYS       = N_LANE + N_LANE_SPARE;
localparam int N_UNIT       = 40;
 
// Per-die configuration, loaded from fuses/OTP at reset. This is the state the
// wrong version has none of.
logic [$clog2(N_PHYS)-1:0] lane_map_q [N_LANE];   // logical -> physical
logic [N_UNIT-1:0]         unit_enable_q;
logic [7:0]                sku_unit_count_q;
logic                      cfg_loaded_q;
 
always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    cfg_loaded_q <= 1'b0;
    for (int l = 0; l < N_LANE; l++) lane_map_q[l] <= l[$clog2(N_PHYS)-1:0];
    unit_enable_q <= {N_UNIT{1'b1}};
  end else if (fuse_valid && !cfg_loaded_q) begin
    for (int l = 0; l < N_LANE; l++) lane_map_q[l] <= fuse_lane_map[l];
    unit_enable_q    <= fuse_unit_enable;
    sku_unit_count_q <= 8'($countones(fuse_unit_enable));
    cfg_loaded_q     <= 1'b1;
  end
end
 
// Routing through the map. A defective physical lane is simply never selected.
always_comb
  for (int l = 0; l < N_LANE; l++)
    tx_phys[lane_map_q[l]] = tx_logical[l];
 
// The die reports what IT has, not what the design nominally has (BUG 3 fix).
assign reported_units = sku_unit_count_q;
 
// MANDATORY. English: the lane map is a permutation — no two logical lanes are
// routed to the same physical lane. A duplicate mapping silently drops one
// lane's data while everything appears to train correctly.
a_lane_map_is_injective: assert property (
  @(posedge clk) disable iff (!rst_n || !cfg_loaded_q)
    (lane_map_q[chk_a] != lane_map_q[chk_b]) || (chk_a == chk_b)
);
 
// MANDATORY. English: the lane map never changes while the link is carrying
// traffic. A remap mid-traffic reorders bytes on the wire with no error
// anywhere — the data is delivered intact, to the wrong lane.
a_lane_map_stable_in_active: assert property (
  @(posedge clk) disable iff (!rst_n)
    link_active |-> $stable(lane_map_q[chk_a])
);
 
// MANDATORY. English: reported capability matches the enabled resources.
// Catches a harvested die advertising the full configuration — which produces
// a software-visible failure at first use of a disabled resource.
a_reported_matches_enabled: assert property (
  @(posedge clk) disable iff (!rst_n || !cfg_loaded_q)
    reported_units == 8'($countones(unit_enable_q))
);

Architecture. Three mechanisms: spare physical lanes with an indirection map, a resource enable mask, and honest capability reporting. Together they turn a class of defective dies into a sellable SKU.

State. lane_map_q, unit_enable_q, sku_unit_count_q — per-instance state, loaded once from fuses. This is precisely the state §10 lacks.

Event. Loaded at reset when fuse_valid, and cfg_loaded_q makes it write-once — a second load while traffic flows is the hazard a_lane_map_stable_in_active exists for.

Contract. Software and the peer die must be told the actual capability, not the nominal one. A harvested die that advertises the full configuration fails at first use of a disabled resource — and that failure surfaces as a driver bug on a subset of parts, which is a miserable thing to debug (27.5 §18 I1).

Failure. The subtle defect here is a non-injective lane map — two logical lanes mapped to one physical lane. The link trains, no error is reported, and one lane's data is silently lost. That is why the permutation property is an assertion rather than a code review comment.

DV/debug. The verification consequence is a configuration matrix, not a single configuration (27.3 §17 H2): full, minus-one-unit, minus-two, and with each spare lane substituted. A harvested SKU that was never verified is a product shipped untested — and it is a real product, because that was the point of building the harvest path.

12. DV and Performance Consequence

Three readings.

Row 4 is the performance failure with a real precedent in this curriculum. 26.3 §13 showed a round-robin scheduler turning one slower participant into a package-wide collapse. Harvesting guarantees unequal participants — that is what harvesting is — so a design that harvests and also distributes work evenly has built its own worst case.

Row 3 makes the performance model plural. There is no single performance number for a harvested product line, and a review that validates the full configuration has validated one SKU (27.4 §7 B5).

And row 1 is where the economics and the verification budget collide. Harvesting adds SKUs, and each SKU is a verification target. That cost belongs in §6's equation too — the harvest path is not free, it is merely much cheaper than the scrap it prevents.

13. Which Review Gate This Corrupts

And the architecture gate's own irreversibility test flags it (27.1 §3): the harvest path changes interfaces — fuses, capability reporting, a lane indirection in the datapath. It cannot be added after RTL without touching everything it touches, which places it firmly at the first gate.

14. Whiteboard Question

"A 50 mm² die at 95 % yield. Your colleague proposes splitting it into two 25 mm² chiplets to improve yield. Talk me through it."

A weak answer accepts the premise and discusses partitioning.

A strong answer computes first. "At 0.5 cm² and a defect density around 0.1/cm², yield is about 95 %. Splitting gives two dies at about 97.5 % each — so the silicon-cost saving is roughly 2.5 %. Against that I'm adding substrate, an assembly step with its own yield, and a second test insertion. The added cost is far larger than the saving — this die is on the wrong side of the crossover."

Then it generalises rather than just answering. "The yield argument is about one term. The question is always: at this area, this defect density, this packaging technology and this volume, which side of the crossover are we on? Five inputs, and yield supplies one."

And it names the legitimate reasons that survive the arithmetic, which is what separates a good answer from a contrarian one: "there are other reasons to split a small die — process affinity, reuse across products, power domains, or the reticle limit if it applied. None of them is the yield argument, and if one of those is the real driver we should say so, because it changes where the boundary goes." (25.7 §6.)

15. Interview Ladder

Weak candidate answer. "Chiplets improve yield because smaller dies have fewer defects, so they're cheaper."

Why the interviewer probes. The statement is correct and incomplete, and the follow-up separates someone who has read about chiplets from someone who has costed one.

Follow-up. "When are they more expensive?"

Strong revised answer. "When the die was never yield-limited. Yield falls exponentially with area, so the saving is large at 600 mm² and negligible at 50 mm² — around 2.5 % for a small die — while the added packaging, assembly and test cost is roughly fixed. Below a crossover in area, splitting costs more. Volume matters too, because NRE divides by it: the same silicon can be right at high volume and wrong at low volume."

The senior addition, unprompted: "and assembly yield compounds — at 97 % per attach, a twelve-die package loses about 31 % of assemblies, and each loss scraps every die in it. That's why known-good-die testing gets economically load-bearing as die count rises, and why 'more chiplets' isn't monotonically better."

The addition that marks someone who has shipped: "the other half is the harvest path. If the design has no way to sell a die with one defective unit, you scrap 26 % of a 300 mm² wafer's dies and forfeit much of the benefit you split for. AMD documents 38 of 40 compute units active per die for yield management — that's the practice, and it's a design decision made long before the fab."

16. How to Remember the Correct Model

The yield curve is one term. Cost is a sum.

And the operational form: name the five inputs before answering. Die area, defect density, packaging technology, volume, and whether a harvest path exists. A yield argument that does not mention the other four is answering a different question.

The memory hook for §8: assembly yield compounds and every failed assembly scraps the good dies with the bad. That single sentence is why "more chiplets is better" is a distinct misconception rather than an extension of this one.

17. Understanding Check

18. Summary

Six things.

The yield curve is correct and it is one term (§6). Packaging rises, NRE rises, and assembly yield and known-good-die test are new terms with no monolithic analogue.

The counterexample is arithmetic (§7). A 0.5 cm² die at 95 % yield saves 2.5 % by splitting and pays roughly a hundred times that in packaging — ≈3.3× more expensive, on the same curve that makes a 6 cm² die 13 % cheaper.

Assembly yield compounds (§8). At 97 % per attach, twelve dies lose 31 % of assemblies, and each loss scraps the good dies with the bad — which is why "more chiplets" is a separate, worse belief.

Five inputs, not one (§16): area, defect density, packaging technology, volume, harvest path. NRE ÷ volume alone can flip the answer with identical silicon.

The RTL consequence is harvestability (§10–§11). A hardcoded lane map and a constant resource count make every defective die scrap — forfeiting much of the benefit the split was for. Spare lanes, an enable mask and honest capability reporting recover it, and the lane map must be a permutation.

And harvesting guarantees unequal participants (§12), which is 26.3 §13's scheduler collapse waiting to happen — a design that harvests and distributes work evenly has built its own worst case.