Throughput — What You Actually Got, and Where the Rest Went

[GT/s] × [bits/transfer, after encoding] = [Gb/s]
[Gb/s] ÷ 8 [bits/byte]                   = [GB/s]
[GB/s per lane] × [lanes]                = [GB/s per direction]

    [bytes accepted]        [bytes]            [bytes]
  ────────────────────  =  ─────────  ×  ────────────────  = [bytes/second]
    [cycles] × [s/cycle]    [cycle]          [second]

// SYNTHESIZABLE. Measurement types and a reusable saturating counter.
// Diagnostic counters SATURATE rather than wrap: a wrapped counter turns a
// saturated link into an apparently idle one (§11 Model 5: 255 -> 232).
package perf_pkg;
 
  parameter int CNT_W    = 32;
  parameter int BYTES_W  = 12;              // bytes accepted per beat
  parameter int WINDOW_W = 24;
 
  typedef enum logic [2:0] {
    CAT_TRANSFER  = 3'd0,
    CAT_STALLED   = 3'd1,
    CAT_NO_CREDIT = 3'd2,
    CAT_NO_WORK   = 3'd3,
    CAT_LINK_DOWN = 3'd4
  } cycle_cat_e;
 
  function automatic logic [CNT_W-1:0] sat_add(input logic [CNT_W-1:0] v,
                                               input logic [CNT_W-1:0] inc);
    logic [CNT_W:0] wide;
    wide = {1'b0, v} + {1'b0, inc};
    return wide[CNT_W] ? {CNT_W{1'b1}} : wide[CNT_W-1:0];
  endfunction
 
  function automatic bit is_saturated(input logic [CNT_W-1:0] v);
    return (v == {CNT_W{1'b1}});
  endfunction
 
endpackage

import perf_pkg::*;
 
// SYNTHESIZABLE. Payload byte counter at the DECLARED measurement point (§3).
// Increments ONLY on the handshake -- counting on valid alone inflated the
// total by 17.7% in §11 Model 3.
module payload_byte_counter (
  input  logic               clk,
  input  logic               rst_n,
  input  logic               measuring,
  input  logic               tx_valid,
  input  logic               tx_ready,
  input  logic [BYTES_W-1:0] tx_byte_count,   // VALID bytes this beat, not bus width
 
  output logic [CNT_W-1:0]   payload_bytes,
  output logic               saturated,
  output logic               zero_byte_seen   // sticky: a beat claiming 0 bytes
);
  logic [CNT_W-1:0] acc_q;
  logic             zb_q;
  logic             xfer;
 
  assign xfer          = tx_valid && tx_ready;     // THE transfer, §7
  assign payload_bytes = acc_q;
  assign saturated     = is_saturated(acc_q);
  assign zero_byte_seen = zb_q;
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin acc_q <= '0; zb_q <= 1'b0; end
    else if (measuring && xfer) begin
      acc_q <= sat_add(acc_q, CNT_W'(tx_byte_count));
      if (tx_byte_count == '0) zb_q <= 1'b1;       // report, do not silently count
    end
  end
endmodule

import perf_pkg::*;
 
// SYNTHESIZABLE. THE CORE BLOCK (§6). Classifies every measured cycle into
// exactly one category by declared priority, so the categories SUM to the
// window. §11 Model 2: residual 0 over 600,000 cycles, versus a 6.2%
// overcount for independent per-cause counters.
module cycle_attribution (
  input  logic clk,
  input  logic rst_n,
  input  logic measuring,
 
  input  logic link_operational,
  input  logic work_pending,        // something is queued to send
  input  logic credit_ok,           // credits suffice for the pending packet
  input  logic tx_valid,
  input  logic tx_ready,
 
  output logic [CNT_W-1:0] c_transfer,
  output logic [CNT_W-1:0] c_stalled,
  output logic [CNT_W-1:0] c_no_credit,
  output logic [CNT_W-1:0] c_no_work,
  output logic [CNT_W-1:0] c_link_down,
  output logic [CNT_W-1:0] c_cycles,        // the DENOMINATOR
  output cycle_cat_e       cat_this_cycle,
  output logic             any_saturated
);
  logic [CNT_W-1:0] t_q, s_q, nc_q, nw_q, ld_q, cy_q;
 
  // ================================================================
  // ONE cycle, ONE category. The priority order encodes what you would
  // fix first: a down Link moots everything; nothing pending indicts the
  // source, not PCIe; only then is credit the story (§6).
  // ================================================================
  always_comb begin
    if      (!link_operational)   cat_this_cycle = CAT_LINK_DOWN;
    else if (!work_pending)       cat_this_cycle = CAT_NO_WORK;
    else if (!credit_ok)          cat_this_cycle = CAT_NO_CREDIT;
    else if (tx_valid && tx_ready) cat_this_cycle = CAT_TRANSFER;
    else                          cat_this_cycle = CAT_STALLED;
  end
 
  assign c_transfer  = t_q;  assign c_stalled   = s_q;
  assign c_no_credit = nc_q; assign c_no_work   = nw_q;
  assign c_link_down = ld_q; assign c_cycles    = cy_q;
  assign any_saturated = is_saturated(t_q)  || is_saturated(s_q)
                      || is_saturated(nc_q) || is_saturated(nw_q)
                      || is_saturated(ld_q) || is_saturated(cy_q);
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      t_q<='0; s_q<='0; nc_q<='0; nw_q<='0; ld_q<='0; cy_q<='0;
    end else if (measuring) begin
      cy_q <= sat_add(cy_q, CNT_W'(1));
      unique case (cat_this_cycle)
        CAT_TRANSFER:  t_q  <= sat_add(t_q,  CNT_W'(1));
        CAT_STALLED:   s_q  <= sat_add(s_q,  CNT_W'(1));
        CAT_NO_CREDIT: nc_q <= sat_add(nc_q, CNT_W'(1));
        CAT_NO_WORK:   nw_q <= sat_add(nw_q, CNT_W'(1));
        CAT_LINK_DOWN: ld_q <= sat_add(ld_q, CNT_W'(1));
      endcase
    end
  end
endmodule

import perf_pkg::*;
 
// SYNTHESIZABLE. Sliding-window rate measurement WITHOUT a divider (§4).
// Publishes bytes-per-window; software divides by WINDOW_CYCLES and the
// clock period. Verified at WINDOW_CYCLES = 1 (§11 Model 4, §12).
module throughput_window #(parameter int WINDOW_CYCLES = 1024) (
  input  logic               clk,
  input  logic               rst_n,
  input  logic               measuring,
  input  logic               tx_valid,
  input  logic               tx_ready,
  input  logic [BYTES_W-1:0] tx_byte_count,
 
  output logic [CNT_W-1:0]   window_bytes,       // live accumulator
  output logic [CNT_W-1:0]   last_window_bytes,  // published snapshot
  output logic               snap_valid,
  output logic [WINDOW_W-1:0] window_cycle
);
  // Guarded so WINDOW_CYCLES = 1 is legal: the boundary is then EVERY cycle.
  localparam int unsigned WC = (WINDOW_CYCLES < 1) ? 1 : WINDOW_CYCLES;
 
  logic [CNT_W-1:0]    acc_q, snap_q;
  logic [WINDOW_W-1:0] cyc_q;
  logic                snap_q_v;
  logic                at_boundary, xfer;
 
  assign xfer              = tx_valid && tx_ready;
  assign at_boundary       = measuring && (cyc_q == WINDOW_W'(WC - 1));
  assign window_bytes      = acc_q;
  assign last_window_bytes = snap_q;
  assign snap_valid        = snap_q_v;
  assign window_cycle      = cyc_q;
 
  always_ff @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
      acc_q <= '0; snap_q <= '0; cyc_q <= '0; snap_q_v <= 1'b0;
    end else begin
      snap_q_v <= 1'b0;
      if (measuring) begin
        // SAME-CYCLE RULE (§10): a transfer ON the boundary cycle belongs to
        // the window that is closing, not to the next one.
        automatic logic [CNT_W-1:0] nxt = xfer ? sat_add(acc_q, CNT_W'(tx_byte_count))
                                               : acc_q;
        if (at_boundary) begin
          snap_q   <= nxt;          // publish INCLUDING this cycle
          snap_q_v <= 1'b1;
          acc_q    <= '0;
          cyc_q    <= '0;
        end else begin
          acc_q <= nxt;
          cyc_q <= cyc_q + WINDOW_W'(1);
        end
      end
    end
  end
endmodule

import perf_pkg::*;
 
// VERIFICATION-ONLY. Completeness monitor: the categories must sum to the
// window (§6). This is the property that makes the taxonomy a measurement
// rather than a set of opinions.
module attribution_completeness_monitor (
  input logic [CNT_W-1:0] c_transfer, c_stalled, c_no_credit,
                          c_no_work,  c_link_down, c_cycles,
  input logic             any_saturated,
  output logic            err_residual
);
  logic [CNT_W+2:0] sum;
  always_comb begin
    sum = c_transfer + c_stalled + c_no_credit + c_no_work + c_link_down;
    // Only meaningful while nothing has saturated -- saturation is lossy
    // BY DESIGN, and the monitor must not report it as a taxonomy error.
    err_residual = !any_saturated && (sum != {3'b0, c_cycles});
  end
endmodule

// ==================================================================
// BYTE ACCOUNTING (§7) -- the transfer, not the offer.
// ==================================================================
 
// P1: payload bytes advance ONLY on a handshake. §11 Model 3: counting on
// valid alone inflated the total by 17.7%.
property p_bytes_on_transfer_only;
  @(posedge clk) disable iff (!rst_n)
    (payload_bytes != $past(payload_bytes)) |->
      $past(measuring && tx_valid && tx_ready);
endproperty
 
// P2: nothing is counted while measurement is off.
property p_no_count_when_idle;
  @(posedge clk) disable iff (!rst_n)
    (!measuring) |=> $stable(payload_bytes);
endproperty
 
// P3: the increment equals the ACCEPTED byte count, not the bus width.
property p_increment_exact;
  @(posedge clk) disable iff (!rst_n)
    (measuring && tx_valid && tx_ready && !saturated) |=>
      (payload_bytes == $past(payload_bytes) + CNT_W'($past(tx_byte_count)));
endproperty
 
// P4: a zero-byte beat is REPORTED, never silently counted as progress.
property p_zero_byte_flagged;
  @(posedge clk) disable iff (!rst_n)
    (measuring && tx_valid && tx_ready && (tx_byte_count == '0)) |=> zero_byte_seen;
endproperty
 
// ==================================================================
// CYCLE ATTRIBUTION (§6) -- the completeness contract.
// ==================================================================
 
// P5: exactly one category per measured cycle. The enum makes this
// structural; the property makes it checkable.
property p_one_category_per_cycle;
  @(posedge clk) disable iff (!rst_n)
    measuring |-> (cat_this_cycle inside {CAT_TRANSFER, CAT_STALLED,
                    CAT_NO_CREDIT, CAT_NO_WORK, CAT_LINK_DOWN});
endproperty
 
// P6: exactly one counter advances per measured cycle.
property p_one_counter_advances;
  @(posedge clk) disable iff (!rst_n)
    (measuring && !any_saturated) |=>
      ($countones({c_transfer  != $past(c_transfer),
                   c_stalled   != $past(c_stalled),
                   c_no_credit != $past(c_no_credit),
                   c_no_work   != $past(c_no_work),
                   c_link_down != $past(c_link_down)}) == 1);
endproperty
 
// P7: THE COMPLETENESS PROPERTY. The parts sum to the whole -- §11 Model 2
// measured residual 0 over 600,000 cycles.
property p_categories_sum_to_window;
  @(posedge clk) disable iff (!rst_n)
    (!any_saturated) |->
      ((c_transfer + c_stalled + c_no_credit + c_no_work + c_link_down)
        == c_cycles);
endproperty
 
// P8: the priority order is respected -- a down Link is never attributed
// to credit, however credit-starved it also is.
property p_link_down_wins;
  @(posedge clk) disable iff (!rst_n)
    (measuring && !link_operational) |-> (cat_this_cycle == CAT_LINK_DOWN);
endproperty
 
// P9: no-work outranks no-credit. Nothing pending is a SOURCE problem and
// must not be reported as a PCIe credit problem (§13).
property p_no_work_outranks_credit;
  @(posedge clk) disable iff (!rst_n)
    (measuring && link_operational && !work_pending) |->
      (cat_this_cycle == CAT_NO_WORK);
endproperty
 
// P10: a stall requires an unaccepted offer. valid && !ready, nothing else.
property p_stall_requires_offer;
  @(posedge clk) disable iff (!rst_n)
    (cat_this_cycle == CAT_STALLED) |-> (tx_valid && !tx_ready);
endproperty
 
// P11: a transfer category implies the handshake.
property p_transfer_implies_handshake;
  @(posedge clk) disable iff (!rst_n)
    (cat_this_cycle == CAT_TRANSFER) |-> (tx_valid && tx_ready);
endproperty
 
// ==================================================================
// SATURATION (§9) -- diagnostics must degrade honestly.
// ==================================================================
 
// P12: counters SATURATE, never wrap. §11 Model 5: a wrapping 8-bit
// counter read 232 after 1000 increments -- an idle-looking saturated link.
property p_never_wraps;
  @(posedge clk) disable iff (!rst_n)
    (c_cycles == {CNT_W{1'b1}}) |=> (c_cycles == {CNT_W{1'b1}});
endproperty
 
// P13: monotonic while measuring -- a diagnostic counter never decreases.
property p_counters_monotonic;
  @(posedge clk) disable iff (!rst_n)
    (c_transfer >= $past(c_transfer)) && (c_cycles >= $past(c_cycles));
endproperty
 
// P14: saturation is sticky and visible, so software can discard the window.
property p_saturation_sticky;
  @(posedge clk) disable iff (!rst_n)
    any_saturated |=> any_saturated;
endproperty
 
// ==================================================================
// WINDOW (§9) -- boundary behaviour, incl. WINDOW_CYCLES = 1.
// ==================================================================
 
// P15: the snapshot is published exactly once per window.
property p_snapshot_once_per_window;
  @(posedge clk) disable iff (!rst_n)
    snap_valid |=> !snap_valid until_with (window_cycle == WINDOW_W'(0));
endproperty
 
// P16: the accumulator restarts at zero after a boundary.
property p_accumulator_restarts;
  @(posedge clk) disable iff (!rst_n)
    snap_valid |-> (window_cycle == WINDOW_W'(0));
endproperty
 
// P17: the boundary-cycle transfer is INCLUDED in the closing window (§10).
property p_boundary_transfer_included;
  @(posedge clk) disable iff (!rst_n)
    (snap_valid && $past(tx_valid && tx_ready && measuring)) |->
      (last_window_bytes >= CNT_W'($past(tx_byte_count)));
endproperty
 
// P18: the window counter never exceeds its modulus -- safe at WC = 1.
property p_window_counter_bounded;
  @(posedge clk) disable iff (!rst_n)
    (window_cycle <= WINDOW_W'(WC - 1));
endproperty
 
// ==================================================================
// NON-INTERFERENCE -- the measurement must not become the experiment.
// ==================================================================
 
// P19: no diagnostic output drives the transmit interface. Formally: tx
// behaviour is independent of every counter value.
property p_monitor_does_not_drive_tx;
  @(posedge clk) disable iff (!rst_n)
    $stable({tx_valid, tx_ready, tx_byte_count}) or
      !$stable({c_transfer, c_cycles, payload_bytes});
endproperty
 
// P20: measured payload can never exceed the interface's own capacity --
// bytes/cycle is bounded by the maximum beat size.
property p_payload_bounded_by_capacity;
  @(posedge clk) disable iff (!rst_n)
    (!any_saturated) |-> (payload_bytes <= c_cycles * CNT_W'(2**BYTES_W - 1));
endproperty