AMBA CHI · Module 20 · Real Industry Case Studies

Mobile SoCs

This module shows CHI in silicon, starting with the flagship mobile SoC. It is a power- and area-constrained part with heterogeneous big.LITTLE cores sharing a coherent L3, a GPU, an NPU, and memory. CHI ties it together: the CPU cores and coherent GPU/NPU are request nodes sharing data without copies; the memory controllers are subordinate nodes; a compact interconnect connects them. What makes mobile distinctive is constraint, not scale: power dominates, so the design leans on aggressive gating, retention, and DVFS, and a compact interconnect over a server mesh. The trap is over-provisioning — a server-class mesh in a power-constrained part — when the right choice is compact and aggressively gated. Representative case study, not a product specification.

Intermediate14 min readAMBA CHIMobile SoCbig.LITTLEPower GatingCoherent GPU

Module 20 · Chapter 20.1 · Real Industry Case Studies

Project thread — Module 19 was interview prep. 20.1 is CHI in mobile silicon; 20.2 is AI accelerators.

1. The Domain

A mobile flagship SoC is the application processor at the heart of a phone or tablet — and the highest-volume coherent design there is. It integrates a moderate, heterogeneous set of CPU cores (a few big performance cores and a few little efficiency cores), a GPU, a neural accelerator (NPU), a display and camera pipeline, and one or two memory channels — all on a single die that must fit a phone's power and area budget. It is coherent, but it is small by server standards and ruthlessly power-constrained.

2. Why CHI Here

Mobile SoCs use CHI because even a phone now has many coherent agents that must share data efficiently. The CPU cores share an L3 and must stay coherent; the GPU and NPU increasingly share data with the CPUs (a photo the CPU produced, a tensor the NPU consumes) — and doing that coherently eliminates the copy-and-flush overhead a non-coherent design pays on every hand-off. CHI provides that coherence with targeted snoops (so the small fabric isn't flooded) and credit-based flow control (so it never overflows) — and its modularity lets the design stay compact and aggressively gated for power.

3. Key Terms

4. Previous Chapter Connection

This chapter applies the node roles (Chapter 19.2), the directory-based coherence (Chapter 11), and the flow control (Chapter 14) to a real product. The CPU cores are RN-F (fully-coherent request nodes, Chapter 5); the L3 and coherence point involve home functionality (Chapter 5); the memory controllers are SN (Chapter 13.5). The targeted-snoop scalability lever (Chapter 15.6) matters even at small scale, because it keeps the compact fabric quiet.

The new dimension mobile adds is power, which none of the technical modules foregrounded. Where the performance module (Chapter 15) optimized for throughput, mobile optimizes for energy — the same CHI mechanisms, evaluated against a battery budget rather than a bandwidth target. This case study is where CHI's modularity and compactness — properties you've seen but not weighted — become the dominant design considerations. It sets up the other case studies by establishing the pattern: same protocol, different constraint.

5. The CHI Configuration

The typical mobile CHI setup — a compact, heterogeneous, coherent system:

CPU cluster (RN-F + shared L3). A DynamIQ Shared Unit-style cluster groups the big and little cores with a shared L3 as one coherent unit — each core a fully-coherent request node.
Coherent GPU / NPU (RNs). The GPU and neural accelerator join the coherence domain as request nodes, so they share data with the CPUs without copies.
Memory controllers (SN). One or two memory channels are the subordinate nodes supplying and storing data.
Compact CHI interconnect. A small CHI interconnect (a modest mesh or a coherent crossbar) with home-node functionality and a system-level cache ties the agents together — sized for area and power, not server scale.

The synthesis:

A mobile SoC uses CHI to connect a heterogeneous CPU cluster (big + little RN-F cores sharing an L3), a coherent GPU and NPU (RNs that share data without copies), and one or two memory controllers (SNs), over a compact CHI interconnect. The configuration is small and power-optimized, not scale-optimized — the same protocol as a server, tuned for a battery.

6. The Domain Constraints

What shapes every mobile design decision — and it is not performance alone.

Power is the currency. Battery life dominates. Every idle block is clock- or power-gated; whole clusters go into retention; the fabric itself is gated when quiet. Coherence traffic costs energy, so targeted snoops matter.
Area is cost. Mobile dies are cost-sensitive, so the interconnect is compact — a small mesh or crossbar, a modestly-sized system-level cache — not a sprawling server mesh.
Heterogeneity is the norm. big.LITTLE means cores of very different performance share one coherence domain, and work migrates between them (a thread moves from a little to a big core) — coherently, so no data is lost in the move.
Bursty, latency-sensitive workloads. UI responsiveness and camera/graphics bursts favor low latency and fast wake, not sustained throughput — so fast power-state transitions matter more than peak bandwidth.

The point to carry:

Mobile inverts the server priority: energy per operation, not operations per second, is the figure of merit. The CHI mechanisms are the same, but they are evaluated against a power budget — which is why mobile favors a compact, aggressively-gated fabric and targeted coherence over raw scale. A design that is fast but power-hungry is a failure in mobile, even if every CHI flow is textbook-correct.

7. Engineering Diagram — the mobile CHI system

Figure 1 — a representative mobile SoC on CHI. A heterogeneous CPU cluster (big and little cores sharing a coherent L3) is a set of fully-coherent request nodes; the GPU and neural accelerator join as coherent request nodes so they share data with the CPUs without copies; the memory controllers are subordinate nodes. A compact CHI interconnect with a system-level cache connects them, and power gating idles blocks and fabric regions when quiet.

A heterogeneous cluster, a coherent GPU/NPU, and memory, tied by a compact CHI interconnect with a system-level cache. The whole fabric — and each block — is gated when idle. The picture is deliberately small: mobile is CHI at modest scale with power as the overriding constraint.

8. The Distinctive Design Decisions

What mobile does differently — and why.

Decision	Mobile choice	Why
Interconnect size	compact (small mesh / crossbar)	area and power, not scale
Core mix	heterogeneous big.LITTLE	performance and efficiency in one domain
GPU/NPU coherence	coherent (RNs)	eliminate copy/flush overhead
Power management	aggressive gating + retention + DVFS	battery life dominates
System-level cache	modest, power-aware	reduce memory (energy) without large area
Wake latency	fast power-state transitions	UI responsiveness

The rule to carry: every mobile decision trades toward energy. A compact fabric, aggressive gating, coherent accelerators (to avoid energy-costly copies), and a modest SLC (to avoid energy-costly memory accesses) all serve the same master: battery. The heterogeneous cores exist for the same reason — run light work on the little cores at a fraction of the energy, and only wake the big cores when needed. CHI's job is to keep all of this coherent while the power management churns underneath it.

9. The Trade-offs

The tensions a mobile CHI design balances.

Power vs performance. DVFS and gating save energy but add wake latency and cap peak throughput. Mobile accepts lower peak for much lower average power.
Compact fabric vs headroom. A small interconnect saves area/power but has less headroom for bursts — sized for the common case, not the peak.
Coherent accelerators vs coherence overhead. Coherent GPU/NPU eliminate copies but add snoop/coherence traffic — a net win when data sharing is frequent, which on mobile it increasingly is.
Heterogeneity vs complexity. big.LITTLE saves energy but complicates migration (moving a thread's coherent state between cores) and scheduling — worth it for the battery gain.

The point to carry:

The defining mobile trade-off is average power for peak performance. The design is tuned for the common, low-intensity case (browsing, standby, light UI) where little cores and a gated fabric sip power, and it bursts to the big cores and full fabric only when needed. CHI supports both regimes with the same coherence — but the sizing and gating choices all lean toward the low-power common case. Getting this balance right is the essence of a mobile design.

10. A Concrete Walkthrough

A coherent CPU-to-NPU hand-off — the scenario that shows why coherence matters on mobile.

The CPU produces data. A big core computes an image buffer and writes it to memory — the data is in its cache (dirty) and the coherent memory space.
The NPU consumes it, coherently. The NPU (a coherent RN) reads that buffer. Because it's coherent, the fabric snoops the CPU and delivers the latest data — even the parts still dirty in the CPU's cache.
No copy, no flush. In a non-coherent design, software would have to flush the CPU's cache and the NPU would read a separate copy — extra memory traffic and energy, plus software cache-maintenance overhead. Coherence eliminates all of it.
The fabric idles. After the hand-off, if the CPU and NPU go quiet, the fabric and blocks gate — power drops to near zero until the next burst.

The coherent hand-off saved energy (no copy, no flush) and the gating saved more (idle blocks off). That combination — coherence to avoid copies, gating to avoid idle power — is the mobile CHI value in one scenario. The pitfall is a design that provisions for the burst but pays its area/power cost during the idle common case.

11. Representative Configuration

A compact, power-oriented mobile CHI configuration, expressed as parameters. Representative.

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

// Representative mobile SoC CHI configuration (educational, not a product spec).
// Small, heterogeneous, aggressively power-managed -- the opposite of a server mesh.
localparam int  N_BIG_CORES   = 4;      // big performance cores (RN-F)
localparam int  N_LITTLE_CORES= 4;      // little efficiency cores (RN-F)
localparam int  N_GPU_NPU_RN  = 2;      // coherent GPU + NPU request nodes
localparam int  N_MEM_CTRL    = 2;      // memory channels (SN) -- modest
localparam int  N_HOME_NODES  = 2;      // few homes -- compact fabric, not a large mesh
localparam int  SLC_KB        = 4096;   // modest system-level cache (area/power aware)
localparam bit  COHERENT_GPU  = 1'b1;   // GPU/NPU share memory coherently (no copies)
 
// Power management -- the defining mobile feature.
localparam bit  CLUSTER_GATING   = 1'b1;  // gate/retain idle CPU clusters
localparam bit  FABRIC_GATING    = 1'b1;  // gate idle interconnect regions
localparam bit  DVFS_ENABLED     = 1'b1;  // dynamic voltage/frequency scaling
localparam int  RETENTION_STATES = 3;     // off / retention / on per block
 
// Sizing leans to the COMMON (low-power) case, not the peak:
//   compact interconnect, few homes, modest SLC, aggressive gating.
// Contrast a server (Chapter 20.6): huge mesh, many homes, large SLC, no gating.

The configuration is small numbers and lots of gating: a handful of cores, a couple of homes and memory channels, a modest SLC, and every power-saving feature enabled. The contrast with the server configuration (Chapter 20.6) is stark — same protocol, opposite sizing — because the constraints (battery vs bandwidth) are opposite.

12. Analysis View — energy, not throughput

The figure of merit that governs a mobile design.

Energy per operation. Mobile optimizes joules per task, not tasks per second. A coherence action's energy (snoop messages, memory accesses) matters more than its latency.
Idle power dominates the average. A phone spends most time idle or lightly loaded, so leakage and idle power — minimized by gating and retention — dominate the average battery drain, not peak activity.
Copies are energy. Every avoided copy (via coherent accelerators) is saved memory bandwidth and therefore saved energy — one of coherence's biggest mobile wins.
Targeted snoops save energy. The directory's targeted snoops (Chapter 15.6) send fewer messages than broadcast — and each message is energy, so targeting is an energy win even at small scale.

The point to carry:

In mobile, energy is the currency and idle is the common case, so the design is dominated by leakage/idle power (minimized by gating) and avoided work (copies eliminated by coherence, memory accesses eliminated by the SLC, snoop messages eliminated by targeting). Every CHI feature is re-valued in energy terms: coherence is not just correctness, it's copy avoidance; the directory is not just scalability, it's fewer energy-costly messages. This re-framing — CHI as an energy optimization — is what makes mobile a distinct case study.

13. Design Considerations

The deeper checklist for a mobile CHI design.

Size for the common case. Provision the fabric and SLC for the low-intensity common case, with just enough burst headroom — not the peak.
Gate everything gateable. Clock/power gating, cluster retention, fabric gating — the more that's off when idle, the lower the average power.
Make coherent accelerators worthwhile. Coherent GPU/NPU pay off when data sharing is frequent; ensure the coherence overhead is less than the copies avoided.
Fast wake. Optimize power-state transitions so bursts (UI, camera) aren't sluggish — wake latency is a UX issue.
Manage heterogeneous migration. Ensure a thread's coherent state migrates cleanly between big and little cores.
Keep the SLC power-aware. A modest, gateable SLC that cuts memory accesses (energy) without large leakage.

14. The Pitfall

Pitfall: over-provisioning a server-class fabric into a mobile part

The classic mobile mistake is to over-provision the interconnect — building a large, server-style mesh with many home nodes, a big system-level cache, and generous buffering into a part where area and power are the currency. It looks impressive on a throughput chart, but it is wrong for mobile: the large fabric leaks power even when idle (which is most of the time), consumes area (cost), and delivers peak bandwidth the phone almost never needs. Mobile workloads are bursty and mostly idle, so the design should be sized for the common low-intensity case with aggressive gating, not the rare peak. The sibling mistake is skimping on power management — a compact fabric that can't gate is still an idle-power drain. The right mobile fabric is compact and aggressively gated: small enough to save area, gated enough to save idle power, with just enough headroom for bursts.

The fix: size the fabric for the common case, enable every gating and retention feature, and use coherent accelerators and a modest SLC to cut energy-costly copies and memory accesses. Compact and gated beats large and fast in mobile.

15. Common Mistakes

Over-provisioned fabric. Assumption: bigger is better. Bug: idle-power and area waste (the Pitfall). Fix: compact, sized for the common case.
Weak power management. Assumption: gating is optional. Bug: idle-power drain. Fix: aggressive gating + retention + DVFS.
Non-coherent accelerators. Assumption: DMA is simpler. Bug: copy/flush energy. Fix: coherent GPU/NPU where sharing is frequent.
Oversized SLC. Assumption: more cache is better. Bug: leakage. Fix: a modest, gateable SLC.
Ignoring migration. Assumption: cores are interchangeable. Bug: state lost on migration. Fix: coherent big.LITTLE migration.
Optimizing peak, not average. Assumption: peak throughput is the goal. Bug: poor battery life. Fix: energy per operation, idle power.

16. Engineering Checklist

Size the CHI fabric for the common low-intensity case, with burst headroom.
Enable clock/power gating, retention, and DVFS on cores, blocks, and fabric.
Join the GPU/NPU as coherent RNs to eliminate copies where sharing is frequent.
Keep the system-level cache modest and power-aware.
Ensure a thread's coherent state migrates cleanly across big.LITTLE cores.
Optimize wake latency for bursty, UI-driven workloads.

17. Key Takeaways

Mobile SoCs use CHI for a compact, heterogeneous, coherent system — not scale.
Power is the currency — aggressive gating, retention, and DVFS dominate.
big.LITTLE cores share one coherence domain; work migrates coherently.
Coherent GPU/NPU eliminate copy-and-flush overhead — an energy win.
Size for the common low-intensity case, not the peak.
The pitfall is a server-class fabric in a power-constrained part; the model here is representative.

18. Quick Revision

Mobile SoCs. A flagship mobile SoC uses CHI to connect a heterogeneous CPU cluster (a few big performance + little efficiency cores in a DynamIQ-style shared unit, each an RN-F sharing a coherent L3), a coherent GPU and NPU (request nodes that share data with the CPUs without copies), and one or two memory controllers (SN), over a compact CHI interconnect with a modest system-level cache. What makes mobile distinctive is constraint, not scale: power is the currency, so the design leans on aggressive clock/power gating, cluster retention, and DVFS, and favors a compact interconnect over a server mesh. The figure of merit is energy per operation and idle power (a phone is mostly idle), so every CHI feature is re-valued in energy terms — coherence eliminates energy-costly copies, the SLC eliminates energy-costly memory accesses, and targeted snoops eliminate energy-costly messages. The design is sized for the common low-intensity case with just enough burst headroom, and gated hard when idle. The pitfall: over-provisioning a server-class mesh into a power- and area-constrained part — large fabrics leak idle power (which is most of the time) and cost area for peak bandwidth a phone rarely needs. Compact and aggressively gated beats large and fast in mobile. Representative case study; 20.2 covers AI accelerators.

Coming Next

Chapter 20.2 — AI Accelerators. Mobile balanced power against a modest workload; AI accelerators push CHI in the opposite direction — toward bandwidth. Chapter 20.2 covers CHI in AI-accelerator coherent subsystems — how a neural accelerator joins the coherence domain to share data with CPUs without copies, why bandwidth provisioning and directory coverage dominate the design, and the trade-off between coherence overhead and the copy elimination it buys.