HN-I (IO Home Node)

Module 5 · Chapter 5.4 · CHI System Components

Project thread — 5.3 detailed HN-F, the coherent home. This chapter takes the home's I/O counterpart: ordering and routing without coherency. 5.5 turns to the coherent subordinate, SN-F.

1. Learning Outcomes

By the end of this chapter you should be able to:

• Define HN-I as the Home Node for non-coherent I/O and peripheral address ranges.
• Explain why it holds no directory and issues no snoops — its space is non-coherent.
• Distinguish what it keeps from HN-F (ordering, routing) and drops (directory, snoops, coherence FSM).
• State the key point: non-coherent does not mean unordered — HN-I still enforces I/O ordering.
• Recognize that a coherent, snoop-requiring request to I/O space is illegal.
• Implement a representative HN-I access handler in SystemVerilog, Verilog-2001, and VHDL.

2. Why Should I Learn This?

Every SoC has non-coherent address space — MMIO, peripheral registers, non-cacheable device memory — and HN-I is its home. Getting it right is what makes device drivers work: register writes that must land in order, accesses routed to the correct peripheral, completions returned reliably. Miss its ordering role and devices misbehave in ways that look like hardware faults.

It also completes a symmetry. Chapter 5.2 subtracted the cache from a request node; this chapter subtracts the directory from a home node. Seeing that the same "coherent vs I/O" split applies to both request and home nodes makes the whole taxonomy click — and clarifies exactly what "coherency" adds, by showing a node that does the home's other jobs without it.

3. Key Terms

4. Previous Chapter Connection

Chapter 5.3 gave HN-F its two engines: a directory and a per-line coherence state machine. Together they make HN-F the point of coherence — it tracks holders and snoops them.

HN-I removes both. Its address space is non-coherent, so there is nothing cached to track and no one to snoop. What survives is the other half of a home node's job, the half 4.3 described before the directory appeared: serialize and route. HN-I is a home that orders accesses to its range and forwards them to the backing subordinate — with the coherency machinery of 5.3 simply absent. It is the home-node parallel to Chapter 5.2's cacheless requester.

5. Core Concept — a home without coherency

HN-I keeps the home's ordering and routing; it drops coherency entirely.

• It is a home for its range. HN-I owns a slice of non-coherent address space (I/O, peripherals) and is the point every access to that range routes through. It serializes and orders those accesses and routes each to the subordinate (SN-I / peripheral) that backs the address.
• It manages no coherency. No directory, no snoop filter, no snoop generation, no I/S/U state machine. There are no cached copies of I/O space to track, so all of that machinery is simply not present.
• It handles non-coherent transactions. Accesses to its space are ReadNoSnp / WriteNoSnp — they carry no snoop and touch no directory. A coherent (snoop-requiring) request to I/O space is illegal — there is nothing to snoop.
• It still enforces ordering. This is the subtle part: non-coherent is not unordered. Device registers often require strict ordering (write config, then write "go"), and HN-I enforces the ordering the requests ask for, even though it never snoops.

The synthesis:

HN-I is HN-F minus coherency: the home's ordering and routing role without the directory, snoops, or coherence state machine. Its space is non-coherent, so it tracks nothing and snoops no one — but it still orders accesses, because I/O correctness depends on order. Coherency is gone; the home's job of putting accesses in a well-defined sequence and routing them remains.

6. Engineering Mental Model — a dispatch desk without a ledger

Return to the registrar model. HN-F was the registrar with a ledger (directory) and a rulebook (coherence FSM), tracking who holds each record.

HN-I is a dispatch desk for a different kind of request — errands to outside offices (peripherals) that keep no shared records.

• The desk takes requests in order and forwards each to the right office (routing). If a client says "do these two in order — set the address, then press send," the desk makes sure the first completes before the second goes out (I/O ordering).
• But there is no ledger: these offices hold nothing the co-op shares, so the desk never tracks holders and never calls anyone to reclaim a copy (no directory, no snoops).
• If a client mistakenly asks the desk to "check who else has this record" (a coherent snoop), the desk refuses — these offices keep no shared records (coherent request to I/O is illegal).

A dispatch desk that orders and forwards but keeps no ledger — that is HN-I.

7. Engineering Diagram — inside HN-I

Compare HN-F (Chapter 5.3): the serializer and routing survive, but the directory and snoop generator are gone. That missing pair is the whole difference between a coherent home and an I/O home.

8. What It Keeps and Drops

HN-I is HN-F with the coherency engines removed. The consequences:

Two facts to carry: everything tied to tracking cached copies is gone (directory, snoops, FSM), and everything tied to being a home — ordering and routing — remains. HN-I is a home node's structure without its coherency.

9. Non-Coherent but Ordered

The one place HN-I is easy to get wrong: assuming non-coherent means it can reorder freely. It cannot.

• Coherency and ordering are different guarantees. Coherency keeps cached copies consistent; ordering keeps accesses in a defined sequence. HN-I drops the first but not the second.
• I/O demands ordering. A driver writing a device does things like: set a DMA address register, set a length register, then write a "start" register. If the "start" write overtakes the address write, the device launches with a stale address. The order is part of the program's meaning.
• HN-I enforces the requested ordering. CHI requests can be marked ordered; HN-I holds a new ordered access until the prior one has reached its ordering point, preserving the sequence to the device — without any snoop or directory involved.

The point to carry:

Non-coherent is not unordered. HN-I sheds coherency but keeps ordering, because I/O correctness depends on accesses reaching devices in the right sequence. Confusing "no coherency" with "no ordering" is the classic HN-I bug — and the DebugLab.

10. Transaction Walkthrough — a device-register write sequence

A driver configures a DMA device through MMIO: address, length, then start.

1. Ordered writes. The RN issues three WriteNoSnp accesses to the device's registers, marked ordered: ADDR, then LEN, then START.
2. HN-I serializes. HN-I owns this I/O range. It admits the ADDR write, forwards it to the device (SN-I), and holds LEN until ADDR reaches its ordering point.
3. In order to the device. LEN follows, then START — each held until the prior is ordered. No snoops, no directory: just non-coherent writes kept in sequence.
4. Device launches correctly. The device sees ADDR, LEN, START in that order and begins the DMA with the correct configuration.
5. No coherency involved. No cache holds these registers; HN-I never snooped anyone. Ordering alone made the sequence correct.

Everything HN-I did was ordering and routing — and that was exactly enough. Reorder step 3 and the device launches misconfigured, which is the DebugLab.

11. RTL / Hardware View — an HN-I access handler

HN-I's logic: accept a non-coherent access when it is legal and the ordering allows, stall it when an earlier ordered access is still in flight, and flag a coherent request as illegal. Representative and combinational.

// Representative HN-I access handler (educational, non-coherent home).
// HN-I orders and forwards I/O accesses; it keeps NO directory and issues NO
// snoops. It accepts NoSnp accesses (stalling to preserve ordering), and rejects
// coherent snoop-requiring requests as illegal for non-coherent I/O space.
module hni_handler (
  input  logic req_valid,
  input  logic req_coherent,     // 1 = a coherent (snoop-requiring) request
  input  logic req_ordered,      // 1 = must be kept in order
  input  logic prev_pending,     // an earlier ordered access is still in flight
  output logic accept,           // forward to the subordinate this cycle
  output logic order_stall,      // hold: ordering not yet satisfied
  output logic illegal           // coherent request to non-coherent space
);
  assign illegal     = req_valid && req_coherent;                       // I/O is non-coherent
  // Ordered access must wait for a prior ordered access to reach its order point.
  assign order_stall = req_valid && !req_coherent && req_ordered && prev_pending;
  assign accept      = req_valid && !req_coherent && !order_stall;      // legal + ordering ok
endmodule

The same behavior in Verilog-2001:

// Representative HN-I access handler (Verilog-2001).
module hni_handler (
  input  req_valid, req_coherent, req_ordered, prev_pending,
  output accept, order_stall, illegal
);
  assign illegal     = req_valid & req_coherent;
  assign order_stall = req_valid & ~req_coherent & req_ordered & prev_pending;
  assign accept      = req_valid & ~req_coherent & ~order_stall;
endmodule

And in VHDL:

-- Representative HN-I access handler (VHDL).
library ieee;
use ieee.std_logic_1164.all;
 
entity hni_handler is
  port (
    req_valid, req_coherent, req_ordered, prev_pending : in  std_logic;
    accept, order_stall, illegal                       : out std_logic
  );
end entity;
 
architecture rtl of hni_handler is
  signal stall_i : std_logic;
begin
  illegal     <= req_valid and req_coherent;
  stall_i     <= req_valid and (not req_coherent) and req_ordered and prev_pending;
  order_stall <= stall_i;
  accept      <= req_valid and (not req_coherent) and (not stall_i);
end architecture;

All three keep the home's job — order and forward — with no coherency: a legal non-coherent access is accepted only once ordering allows, and a coherent request is flagged illegal. There is no directory or snoop anywhere in the logic.

12. Verification View — coherent illegal, ordering preserved

Two properties: a coherent request is never accepted (it is illegal), and an ordered access with a prior pending is never accepted (ordering held).

// Bind to hni_handler.
// 1. A coherent request to I/O space is illegal and never accepted.
property p_coherent_illegal;
  @(*) req_coherent |-> (illegal && !accept);
endproperty
 
// 2. An ordered access with an earlier ordered access still in flight must not
//    be accepted — ordering to the device is preserved.
property p_ordering_held;
  @(*) (req_ordered && prev_pending && !req_coherent) |-> !accept;
endproperty

The system point, beyond the two checks:

HN-I's two guarantees are legality and ordering — not coherency. Legality: I/O space is non-coherent, so a snoop-requiring request has no meaning here and must be rejected, never quietly forwarded. Ordering: even without coherency, accesses to a device must reach it in the program's order, so an ordered access waits for its predecessor. Dropping coherency does not license reordering — conflating the two is exactly the failure the DebugLab shows.

• What it proves: coherent requests are rejected; ordered accesses wait their turn.
• What it does not prove: the full I/O ordering model (streams, barriers) — this is the core case.
• Bug signature: ordered device writes reaching the peripheral out of sequence (the DebugLab).

13. Testbench — legal, ordered, and illegal cases

Exercises a legal ordered access (accepted then stalled by a pending prior) and an illegal coherent request.

module tb_hni_handler;
  logic req_valid, req_coherent, req_ordered, prev_pending;
  logic accept, order_stall, illegal;
  int errors = 0;
 
  hni_handler dut (.*);
 
  task automatic check(input logic v, input logic co, input logic ord, input logic pend,
                       input logic exp_acc, input logic exp_stall, input logic exp_ill, input string tag);
    req_valid = v; req_coherent = co; req_ordered = ord; prev_pending = pend; #1;
    if (accept !== exp_acc || order_stall !== exp_stall || illegal !== exp_ill) begin
      errors++; $display("FAIL [%s] acc=%b stall=%b ill=%b", tag, accept, order_stall, illegal);
    end else $display("PASS [%s] acc=%b stall=%b ill=%b", tag, accept, order_stall, illegal);
  endtask
 
  initial begin
    check(1, 0, 1, 0, 1'b1, 1'b0, 1'b0, "ordered, no prior -> accept");
    check(1, 0, 1, 1, 1'b0, 1'b1, 1'b0, "ordered, prior pending -> stall");
    check(1, 0, 0, 1, 1'b1, 1'b0, 1'b0, "unordered -> accept regardless");
    check(1, 1, 0, 0, 1'b0, 1'b0, 1'b1, "coherent -> illegal, not accepted");
 
    if (errors == 0) $display("ALL TESTS PASSED");
    else             $display("%0d FAILURE(S)", errors);
    $finish;
  end
endmodule

Expected output:

PASS [ordered, no prior -> accept] acc=1 stall=0 ill=0
PASS [ordered, prior pending -> stall] acc=0 stall=1 ill=0
PASS [unordered -> accept regardless] acc=1 stall=0 ill=0
PASS [coherent -> illegal, not accepted] acc=0 stall=0 ill=1

14. DebugLab — HN-I reorders an ordered device sequence

issue order   register   arrives at device   note
    1          ADDR            2nd             ordered write, delayed
    2          START           1st             overtook ADDR -> device launches early

15. Common Mistakes

• Assuming non-coherent means unordered. Assumption: no coherency, reorder freely. Bug: device misconfiguration (the DebugLab). Prevention: HN-I still enforces I/O ordering.
• Expecting a directory in HN-I. Assumption: every home tracks holders. Bug: looking for snoop state that does not exist. Prevention: HN-I has no directory — its space is non-coherent.
• Sending coherent requests to I/O space. Assumption: any request works anywhere. Bug: illegal snoop-requiring request. Prevention: use NoSnp for I/O; coherent requests are illegal there.
• Confusing HN-I with an SN. Assumption: the home stores the device data. Bug: mislocating the endpoint. Prevention: HN-I orders and routes; the SN-I / peripheral holds the data.
• Skipping HN-I's completion role. Assumption: it just forwards. Bug: missing ordering/completion guarantees. Prevention: it is the ordering and completion point for its range.
• Treating HN-I as unimportant. Assumption: I/O is a side concern. Bug: driver-visible ordering bugs. Prevention: HN-I correctness is device correctness.

16. Engineering Checklist

• Use HN-I for non-coherent I/O / peripheral address ranges.
• Expect no directory and no snoops — nothing cached to track.
• Route accesses to the backing SN-I / peripheral.
• Enforce I/O ordering — hold an ordered access until its predecessor is ordered.
• Reject coherent (snoop-requiring) requests to I/O space as illegal.
• Remember: non-coherent is not unordered.

17. Key Takeaways

• HN-I is the Home Node for non-coherent I/O / peripheral ranges — HN-F minus coherency.
• It keeps the home's ordering and routing; it drops the directory, snoops, and coherence state machine.
• Its accesses are NoSnp (ReadNoSnp / WriteNoSnp); a coherent snoop-requiring request to I/O space is illegal.
• Non-coherent is not unordered — HN-I still enforces the ordering device registers depend on.
• It is the home-node parallel to Chapter 5.2's cacheless requester: the same coherent-vs-I/O split, applied to a home.
• Getting its ordering right is getting device drivers right; the model here is representative.

18. Quick Revision

HN-I (I/O Home Node). The home for non-coherent I/O / peripheral address ranges — HN-F minus coherency. It keeps the home's ordering and routing (serialize accesses to its range, forward to the backing SN-I / peripheral) and drops all coherency: no directory, no snoop filter, no snoops, no I/S/U state machine. Accesses are ReadNoSnp / WriteNoSnp; a coherent snoop-requiring request to I/O space is illegal. Crucial point: non-coherent is not unordered — HN-I still enforces the ordering device registers require (write ADDR, then LEN, then START, in order), holding an ordered access until its predecessor is ordered. It is the home-node parallel to the cacheless requester of 5.2. Representative model; 5.5 covers SN-F.

Coming Next

Chapter 5.5 — SN-F (Fully Coherent Slave Node). The taxonomy turns from the homes to the endpoints. Chapter 5.5 details SN-F, the subordinate that backs coherent memory: the memory controller behind an HN-F that completes the coherent reads and writes the Home Node forwards. We saw in Chapter 4.4 that the subordinate does no coherency itself; 5.5 gives SN-F its depth — how it serves a coherent Home Node, handles writebacks, and stays the plain storage endpoint at the back of every coherent transaction.