Named & Positional Port Connections

// The module being instantiated:
// module adder_4bit (input logic a, b, cin, output logic sum, cout);
//                              ①  ②   ③                ④     ⑤
 
// Positional instantiation — signal order must match port order
adder_4bit  u_add (
    operand_a,    // ① connects to: a
    operand_b,    // ② connects to: b
    carry_in,     // ③ connects to: cin
    result,       // ④ connects to: sum
    carry_out     // ⑤ connects to: cout
);

// ── Standard named connections ─────────────────────────────────
adder_4bit  u_add (
    .a   (operand_a),    // port 'a'   ← signal 'operand_a'
    .b   (operand_b),    // port 'b'   ← signal 'operand_b'
    .cin (carry_in),     // port 'cin' ← signal 'carry_in'
    .sum (result),       // port 'sum' ← signal 'result'
    .cout(carry_out)     // port 'cout'← signal 'carry_out'
);
 
// ── Order doesn't matter — this is identical ───────────────────
adder_4bit  u_add2 (
    .cout(carry_out),    // outputs listed first — totally fine
    .sum (result),
    .cin (carry_in),
    .b   (operand_b),
    .a   (operand_a)
);
 
// ── Port name = signal name? You can write .port(port) ─────────
// Or even shorter — named connection where names match:
adder_4bit  u_add3 (
    .a   (a),            // port 'a' connected to signal 'a' in parent
    .b   (b),
    .cin (cin),
    .sum (sum),
    .cout(cout)
);
 
// ── Connecting a constant or expression directly ────────────────
adder_4bit  u_add4 (
    .a   (operand_a),
    .b   (operand_b),
    .cin (1'b0),         // ← constant tied to a port
    .sum (result),
    .cout()              // ← intentionally unconnected (empty parens)
);

module top;
 
    // Signals named IDENTICALLY to the module's ports
    logic [3:0] a, b, sum;
    logic       cin, cout;
 
    // .* connects every port to a same-named signal automatically
    // adder_4bit has ports: a, b, cin, sum, cout
    adder_4bit  u_add (.*);     // one token — zero manual wiring!
 
    // ── Mixing .* with explicit overrides ──────────────────────
    // You can override specific ports while .* handles the rest
    logic [3:0] alt_b;
 
    adder_4bit  u_add2 (
        .*,                    // connect a, cin, sum, cout by name
        .b(alt_b)              // override: connect b to alt_b instead
    );
 
endmodule

module tb_counter;
 
    // Declare signals with the EXACT same names as the DUT's ports
    logic        clk  = 0;
    logic        rst_n;
    logic        en;
    logic [7:0]  count;       // output port 'count'
    logic        is_zero;     // output port 'is_zero'
 
    // DUT: counter_8bit has ports: clk, rst_n, en, count, is_zero
    counter_8bit  u_dut (.*);   // all five connected in one token
 
    always #5 clk = ~clk;
 
    initial begin
        rst_n = 0; en = 0;
        @(posedge clk); rst_n = 1; en = 1;
        repeat(20) @(posedge clk);
        $finish;
    end
 
endmodule

// ── Empty parentheses = intentionally unconnected output ───────
adder_4bit  u_add (
    .a   (operand_a),
    .b   (operand_b),
    .cin (1'b0),          // tie carry-in LOW with a constant
    .sum (result),
    .cout()               // empty () = "I know it's unconnected, intentional"
);
 
// ── Tying inputs to constants ───────────────────────────────────
uart_tx  u_uart (
    .clk    (sys_clk),
    .rst_n  (rst_n),
    .en     (1'b1),        // always enabled — tied HIGH
    .data   (tx_data),
    .baud   (2'b00),       // fixed baud rate — tied to constant
    .tx_out (serial_out),
    .busy   ()             // don't care about busy flag — unconnected
);
 
// ── What NOT to do ─────────────────────────────────────────────
// Simply omitting a port in named style also leaves it unconnected,
// but gives no documentation of intent — harder to review:
adder_4bit  u_add_bad (
    .a   (operand_a),
    .b   (operand_b),
    .cin (1'b0),
    .sum (result)
    // cout omitted — compiler warns, reader wonders if it was a mistake
);

// ── The DUT: simple half-adder ──────────────────────────────────
module half_adder (
    input  logic a, b,
    output logic sum, cout
);
    assign sum  = a ^ b;
    assign cout = a & b;
endmodule
 
 
// ── Testbench comparing all three styles ────────────────────────
module tb_connection_styles;
 
    // Signals for named & positional instances
    logic p, q, s_pos, c_pos;      // for positional
    logic x, y, s_nam, c_nam;      // for named
 
    // Signals named to MATCH half_adder ports (for .* instance)
    logic a, b, sum, cout;         // for implicit .*
 
    // ── ❶ Positional ──────────────────────────────────────────────
    half_adder  u_pos   (p, q, s_pos, c_pos);
 
    // ── ❷ Named .port(signal) ─────────────────────────────────────
    half_adder  u_named (.a(x), .b(y), .sum(s_nam), .cout(c_nam));
 
    // ── ❸ Implicit .* ─────────────────────────────────────────────
    half_adder  u_impl  (.*);   // a,b,sum,cout connected by name
 
    // ── Apply the same stimulus to all three ──────────────────────
    initial begin
        $monitor("p=%b q=%b | pos: s=%b c=%b | named: s=%b c=%b | impl: s=%b c=%b",
                 p, q, s_pos, c_pos, s_nam, c_nam, sum, cout);
 
        {p,x,a} = 3'b000; {q,y,b} = 3'b000; #10;
        {p,x,a} = 3'b111; {q,y,b} = 3'b000; #10;
        {p,x,a} = 3'b000; {q,y,b} = 3'b111; #10;
        {p,x,a} = 3'b111; {q,y,b} = 3'b111; #10;
        $finish;
    end
 
endmodule

// ── ❶ Positional — signal order must match port order ──────────
mod_name  inst_name (sig1, sig2, sig3);
 
// ── ❷ Named — .port(signal) — RECOMMENDED for all RTL ──────────
mod_name  inst_name (
    .port1(signal_a),
    .port2(signal_b),
    .port3(1'b0),       // tie input to constant
    .port4()            // intentionally unconnected output
);
 
// ── ❸ Implicit .* — connect every port by name match ───────────
mod_name  inst_name (.*);
 
// ── ❸b Mix .* with explicit overrides ──────────────────────────
mod_name  inst_name (.*, .port2(different_signal));
 
// ── Cannot mix: positional + named ─────────────────────────────
// mod_name inst_name (sig1, .port2(sig2));  ← ILLEGAL
 
// ── Tie to constants ────────────────────────────────────────────
// .en   (1'b1)      tie HIGH
// .sel  (1'b0)      tie LOW
// .data ('0)        tie whole bus to zero
// .data ('1)        tie whole bus to ones
// .out  ()          output — intentionally unconnected

// ── DUT: an 8-bit register file write port ─────────────────────
module reg_file (
    input  logic       clk,
    input  logic       we,
    input  logic [2:0] waddr,
    input  logic [7:0] wdata      // ← 8 bits
);
    logic [7:0] mem [8];
    always_ff @(posedge clk) if (we) mem[waddr] <= wdata;
endmodule
 
 
// ── Parent: somebody widens the data bus to 16 bits ────────────
module cpu_core;
    logic        clk, we;
    logic [2:0]  waddr;
    logic [15:0] alu_result;  // ← now 16 bits!
 
    // LRM-legal but DANGEROUS — upper 8 bits silently truncated
    reg_file u_rf (
        .clk(clk),
        .we (we),
        .waddr(waddr),
        .wdata(alu_result)   // ❌ alu_result[15:8] thrown away silently
    );
endmodule
 
// ── The fix: be explicit. The truncation is now a CHOICE ──────
reg_file u_rf_safe (
    .clk(clk), .we(we), .waddr(waddr),
    .wdata(alu_result[7:0])  // ✅ truncation is documented & intentional
);

// ── A tri-state I/O pad model ──────────────────────────────────
module tristate_pad (
    inout  wire  pad,         // ← MUST be a net, not logic
    input  logic drive_en,
    input  logic drive_val,
    output logic rx_val
);
    assign pad    = drive_en ? drive_val : 1'bz;  // tri-state
    assign rx_val = pad;
endmodule
 
 
// ── ❌ WRONG: parent uses 'logic' for the inout net ────────────
module top_bad;
    logic bus_net;          // ← variable! cannot drive an inout
    logic en, dval, rval;
 
    tristate_pad u_pad (
        .pad(bus_net),      // ❌ elaboration error in most tools
        .drive_en(en), .drive_val(dval), .rx_val(rval)
    );
endmodule
 
 
// ── ✅ CORRECT: declare the shared bus as a wire/tri ───────────
module top_good;
    wire        bus_net;     // ✅ net — can be driven by multiple sources
    logic       en, dval, rval;
 
    // Optional weak pull-up so bus is not X when nobody drives
    pullup      (bus_net);    // strength 'pull' on bus_net
 
    tristate_pad u_pad (
        .pad(bus_net),
        .drive_en(en), .drive_val(dval), .rx_val(rval)
    );
endmodule

// ── ❶ The interface bundles the DUT-facing signals ────────────
interface axi_if (input logic aclk, aresetn);
    logic [31:0] awaddr;
    logic        awvalid, awready;
    logic [31:0] wdata;
    logic        wvalid, wready;
    // ... plus modports for master/slave/monitor
endinterface
 
 
// ── ❷ Top-level TB instantiates DUT with NAMED connections ────
module tb_top;
    logic aclk = 0, aresetn;
    always #5 aclk = ~aclk;
 
    // One interface instance per AXI port
    axi_if m_if (aclk, aresetn);
 
    // DUT instantiation — NAMED, with interface signals on the right
    dma_engine u_dut (
        .aclk     (aclk),
        .aresetn  (aresetn),
        .m_awaddr (m_if.awaddr),
        .m_awvalid(m_if.awvalid),
        .m_awready(m_if.awready),
        .m_wdata  (m_if.wdata),
        .m_wvalid (m_if.wvalid),
        .m_wready (m_if.wready)
    );
 
    // ❸ Publish the virtual interface so UVM driver/monitor can grab it
    initial begin
        uvm_config_db#(virtual axi_if)::set(null, "uvm_test_top.env.agent*",
                                              "vif", m_if);
        run_test("axi_smoke_test");
    end
endmodule

module dut_with_probes (
    // SAME port list as the DUT — wrapper is transparent
    input  logic clk, rst_n, en,
    input  logic [31:0] data_in,
    output logic [31:0] data_out, status
);
    // ← .* connects every signal whose name matches — fast & safe
    dut u_dut (.*);
 
    // Add SVA / coverage / debug probes here — independent of port list
    assert property (@(posedge clk) disable iff (!rst_n)
        en |-> ##[1:5] status[0])
        else $error("DUT did not ack within 5 cycles");
 
endmodule

# Find positional instantiations: open-paren followed by
# an identifier (NOT a dot) — heuristic but catches 95% of cases.
rg -t verilog -nP '\b\w+\s+\w+\s*\(\s*[a-zA-Z_]' rtl/ \
  | grep -v '\.\w' \
  | awk -F: '{print $1}' \
  | sort | uniq -c | sort -rn \
  | head -20
 
# Output (most-frequent files first — refactor these first):
#    34  rtl/cpu/decode_stage.sv
#    27  rtl/mem/cache_ctrl.sv
#    19  rtl/io/uart_top.sv
#    ...