SystemVerilog — Tutorials & Labs

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Expert-Crafted Content

Written by industry veterans with real VLSI verification experience at leading semiconductor companies.

Interview-Ready Depth

Topics mirror exactly what Intel, Cadence, Synopsys, and NVIDIA ask in SystemVerilog verification interviews.

Zero Knowledge Gaps

17 progressive modules so each topic naturally prepares you for the next — nothing assumed, nothing skipped.

SystemVerilog Complete Curriculum

Your Learning Roadmap

17 chapters · 129 pages — from language basics to expert verification.

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Chapter 1

Foundations

1.1What is SystemVerilog?1.2SystemVerilog vs Verilog 1.3Tool Setup 1.4Your First SystemVerilog Program

Chapter 2

Data Types

2.14-State vs 2-State Types 2.2Integer Types 2.3Real & Shortreal Types 2.4String Type & Methods 2.5User-Defined Types with typedef 2.6Enumeration Types 2.7Structures — Packed & Unpacked 2.8Unions & Tagged Unions 2.9Type Casting & Conversion

Chapter 3

Arrays

3.1Fixed-Size Arrays 3.2Dynamic Arrays 3.3Associative Arrays 3.4Queues 3.5Array Methods

Chapter 4

Operators & Expressions

4.1Arithmetic Operators 4.2Relational & Equality Operators 4.3Logical Operators 4.4Bitwise Operators 4.5Reduction Operators 4.6Shift Operators 4.7Concatenation, Replication & Conditional 4.8Inside Operator 4.9Wildcard Equality — ==? and !=?4.10Operator Precedence

Chapter 5

Procedural Statements

5.1Procedural Blocks 5.2if-else & Unique/Priority Modifiers 5.3case, casex, casez, unique, priority 5.4Loops 5.5break, continue, return, disable 5.6Blocking vs Non-Blocking Assignments

Chapter 6

Tasks & Functions

6.1Tasks vs. Functions — When to Use Which 6.2Function Declarations & Return Values 6.3Task Declarations & Time-Consuming Calls 6.4Automatic vs. Static Lifetime 6.5Pass by Value vs. Pass by Reference 6.6Default Argument Values 6.7void Functions & System Tasks Overview

Chapter 7

Modules & Hierarchy

7.1Module Definition & Instantiation 7.2Port Types — input, output, inout, ref 7.3Named & Positional Port Connections 7.4Parameters & Localparams 7.5Parameter Overrides — defparam & # Notation 7.6Generate Constructs — for, if, case 7.7Hierarchical References & $root

Chapter 8

Interfaces

8.1Introduction to Interfaces 8.2Modport — Restricting Port Directions 8.3Clocking Blocks 8.4Virtual Interfaces 8.5Interface Arrays & Parameterised Interfaces

Chapter 9

Object-Oriented Programming

9.1Introduction to OOP in SystemVerilog 9.2Classes & Objects — Basics 9.3Properties & Methods 9.4Constructors & new()9.5Encapsulation — public, protected, local 9.6The this Keyword 9.7Static Properties & Methods 9.8Inheritance & extends 9.9The super Keyword 9.10Polymorphism & Virtual Methods 9.11Abstract Classes & Pure Virtual Methods 9.12Parameterised Classes 9.13Nested Classes 9.14Handles — Shallow Copy, Deep Copy, Comparison 9.15typedef class — Forward Declarations 9.16Class Scope Resolution (::)

Chapter 10

Constrained Random Verification

10.1Introduction to Constrained Random Verification 10.2rand & randc Keywords 10.3The randomize() Method & Return Value 10.4Constraint Blocks 10.5Inline Constraints — the with Clause 10.6Constraint Modes — constraint_mode()10.7Soft Constraints 10.8Weighted Distributions — dist 10.9Implication & Conditional Constraints 10.10Iterative Constraints — foreach in Constraints 10.11Randomising Arrays 10.12pre_randomize & post_randomize Callbacks 10.13randcase Statement 10.14randsequence Statement 10.15Solve Before Constraints

Chapter 11

Functional Coverage

11.1Introduction to Functional Coverage 11.2Covergroups & Coverpoints 11.3Automatic Bins 11.4Named Bins — Explicit Coverage Partitions 11.5Wildcard, Illegal & Ignore Bins 11.6Transition Coverage 11.7Cross Coverage 11.8Coverage Options 11.9Sampling Events 11.10Instance vs Type Coverage

Chapter 12

SystemVerilog Assertions

12.1Introduction to SystemVerilog Assertions (SVA)12.2Immediate Assertions 12.3Deferred Immediate Assertions 12.4Concurrent Assertions 12.5SVA Sequences 12.6SVA Properties 12.7Clocking & disable iff 12.8Implication Operators 12.9Repetition Operators 12.10assert, assume, cover, restrict 12.11Assertion Severity & Action Blocks 12.12Assertion Control System Tasks

Chapter 13

Inter-Process Communication

13.1Introduction to Inter-Process Communication 13.2Events 13.3Semaphores 13.4Mailboxes

Chapter 14

Process Control

14.1fork-join 14.2fork-join_any 14.3fork-join_none 14.4disable fork & wait fork 14.5The process Class

Chapter 15

Program Blocks

15.1Program Block vs Module — Race-Free Simulation 15.2Clocking Blocks — Deep Dive, SVA, Coverage, Multi-Clock SoC, CDC 15.3Input & Output Skews 15.4Program Block Limitations & Best Practices

Chapter 16

Packages

16.1Package Declaration & Usage 16.2import — Explicit & Wildcard 16.3Package-Level Parameters & Types 16.4Package Dependencies & Compilation Order

Chapter 17

Advanced Topics

17.1Direct Programming Interface (DPI-C)17.2The bind Construct 17.3Checkers 17.4Specify Blocks & Path Delays 17.5config & Library Mapping 17.6Scheduling Semantics & Timing Regions