The i2c_if Interface — Bidirectional Signals in a Testbench

   interface i2c_if(input logic clk);
      // DO NOT DO THIS
      wire sda;
      logic sda_out, sda_oe;
      assign sda = sda_oe ? sda_out : 1'bz;    // drives HIGH when sda_out is 1
   endinterface

      logic [N_DRV-1:0] scl_drive_low;
      logic [N_DRV-1:0] sda_drive_low;

      wire scl = ~(|scl_drive_low | dut_scl_drive_low);
      wire sda = ~(|sda_drive_low | dut_sda_drive_low);

      clocking drv_cb @(posedge clk);
         output scl_drive_low, sda_drive_low;
         input  scl, sda, scl_holders, sda_holders;
      endclocking

      clocking mon_cb @(posedge clk);
         input scl, sda, scl_holders, sda_holders;
      endclocking

      modport drv_mp (clocking drv_cb);
      modport mon_mp (clocking mon_cb);

      wire [31:0] sda_holders = $countones(sda_drive_low) + (dut_sda_drive_low ? 1 : 0);

   // -----------------------------------------------------------------------------
   // i2c_if.sv
   // An open-drain bus as a SystemVerilog interface.
   //
   // NOT EXECUTED. No UVM library and no UVM-capable simulator exists in this
   // environment -- `probe/capability.sh` measures it, and a virtual interface inside a
   // class is itself a compile error on the only Verilog simulator available here. This
   // file is published as reviewed, statically checked source, not as a simulated result.
   //
   // THE ONE DECISION THAT MATTERS. There is no `sda` output. A participant owns a
   // `*_drive_low` bit and nothing else, exactly as in Module 16's bus model and Module
   // 19's pad: the only action available on this bus is PULLING LOW, and `1` is the
   // absence of an action rather than an action. An interface that exposed a drivable
   // `sda` would let a testbench component drive the line high, which no open-drain
   // device can do -- and Chapter 20.4's argument is that this has to be impossible
   // rather than merely discouraged.
   //
   // Consequently the resolved value is computed here, in one place, as a wired-AND of
   // every participant's pull. A component reads `scl`/`sda` and writes only its own
   // `*_drive_low` bit, and the two are genuinely different signals: a component that
   // releases a line and then assumes it is high is the defect Chapter 20.5's driver
   // exists to avoid.
   // -----------------------------------------------------------------------------
   `timescale 1ns/1ps

   interface i2c_if #(
      // Participants that can pull the lines. The DUT is not one of them -- it connects
      // to the resolved nets through its own pins.
      parameter int N_DRV = 4
   ) (
      input logic clk
   );

      // ---- what each testbench participant requests ----------------------------
      // Index 0 is by convention the master driver, 1 the responder, 2 the error
      // injector, 3 spare. Nothing enforces that; the resolution below does not care.
      logic [N_DRV-1:0] scl_drive_low;
      logic [N_DRV-1:0] sda_drive_low;

      // ---- what the DUT requests ----------------------------------------------
      logic dut_scl_drive_low;
      logic dut_sda_drive_low;

      // ---- what the bus therefore IS ------------------------------------------
      // Wired-AND: low if ANY participant pulls, high only if every one released. This
      // is the only place in the VIP that decides what the bus is, which is why a
      // component cannot accidentally disagree with it.
      wire scl = ~(|scl_drive_low | dut_scl_drive_low);
      wire sda = ~(|sda_drive_low | dut_sda_drive_low);

      // ---- evidence a monitor cannot get from the line -------------------------
      // How MANY participants are pulling. The resolved line cannot answer this -- low
      // is low, and the wired-AND of one puller and two is bit-identical -- so a second
      // unintended driver in an acknowledge slot is undetectable without a count.
      // Chapter 20.9 argues this is the one protocol rule that has no bus-level check.
      wire [31:0] scl_holders = $countones(scl_drive_low) + (dut_scl_drive_low ? 1 : 0);
      wire [31:0] sda_holders = $countones(sda_drive_low) + (dut_sda_drive_low ? 1 : 0);

      // ---- clocking blocks -----------------------------------------------------
      // An ACTIVE participant drives its own pull bits and samples the resolved lines.
      // A PASSIVE one samples and has no outputs at all: the modport is where passivity
      // stops being a promise. A monitor connected through `mon_mp` cannot drive,
      // because there is nothing in its view to drive.
      clocking drv_cb @(posedge clk);
         output scl_drive_low, sda_drive_low;
         input  scl, sda, scl_holders, sda_holders;
      endclocking

      clocking mon_cb @(posedge clk);
         input scl, sda, scl_holders, sda_holders;
      endclocking

      modport drv_mp (clocking drv_cb);
      modport mon_mp (clocking mon_cb);

      // ---- reset the interface's own drivers -----------------------------------
      // Release everything. A participant that has not been started must not be holding
      // a line, or every test after it inherits a wedged bus.
      task automatic release_all();
         scl_drive_low = '0;
         sda_drive_low = '0;
      endtask

      initial begin
         scl_drive_low     = '0;
         sda_drive_low     = '0;
         dut_scl_drive_low = 1'b0;
         dut_sda_drive_low = 1'b0;
      end

   endinterface