Replication Operator in Verilog — Repeat a Value to Build Wide Vectors

Chapter 10 · Section 10.9 · Operators & Operands

1. The Engineering Problem

A parameterized module needs an all-ones mask the width of its data. The engineer hardcodes it:

module masker #(parameter integer WIDTH = 8)(
    input  [WIDTH-1:0] data,
    output [WIDTH-1:0] result
);
    assign result = data & 8'hFF;        // all-ones mask... but hardcoded 8 bits
endmodule

For the default WIDTH = 8 it works. Instantiate it with WIDTH = 16 and it breaks: 8'hFF zero-extends to 16'h00FF, so the mask clears the upper 8 bits instead of passing them — the §6 bug from the bitwise page, now caused by a width-locked constant. The "all-ones" mask is only all-ones at one specific width.

The replication operator builds the mask width-independently:

assign result = data & {WIDTH{1'b1}};   // WIDTH copies of 1 → all-ones, any WIDTH

`{WIDTH{1'b1}}` is 1'b1 repeated WIDTH times — a WIDTH-bit all-ones value that scales automatically with the parameter. Change WIDTH and the mask follows; there is no constant to forget.

The replication operator repeats a value a constant number of times to build a wider one — the width-independent way to construct fills, sign extensions, and masks. Hardcoded-width constants silently break when the width changes; replication scales with it.

Replication is a construction operator, not a computation one — it assembles vectors rather than transforming values. This page teaches its syntax, the three jobs it does constantly, and why the repeat count must be a constant.

2. Mental Model — Repeat a Value N Times to Build a Wider One

Visual A — replication duplicates and joins

3. The Syntax

   {count{value}}            // value repeated 'count' times
 
   {4{1'b1}}                 // = 4'b1111
   {8{1'b0}}                 // = 8'b0000_0000
   {2{4'hC}}                 // = 8'hCC
   {WIDTH{1'b1}}             // = WIDTH-bit all-ones (count is a parameter)
   {{3{1'b1}}, 2'b00}        // replication nested inside concatenation → 5'b11100

The form is nested braces: an outer brace pair, a count, then an inner brace pair around the value — `{count{value}}`. Notes:

• The inner braces are required. `{4{1'b1}}` is correct; `{4 1'b1}` (missing inner braces) is a syntax error. The double-brace shape is the signature of replication.
• count is a constant expression — a literal or parameter, resolved at elaboration (§7).
• value is any expression — a literal, a signal, even another replication or concatenation (nesting is allowed).

4. The Three Key Uses

Almost all replication is one of these three patterns:

   // 1. FILL — width-independent all-zeros / all-ones
   {WIDTH{1'b0}}            // all zeros, scales with WIDTH
   {WIDTH{1'b1}}            // all ones,  scales with WIDTH
 
   // 2. SIGN EXTENSION — replicate the sign bit (with concatenation, 10.10)
   {{8{val[7]}}, val}       // extend 8-bit signed 'val' to 16 bits, sign-preserved
 
   // 3. CONDITIONAL MASK — replicate a control bit across a bus
   data ^ {WIDTH{invert}}   // invert every bit of data when 'invert' is 1
   data & {WIDTH{enable}}   // pass data when 'enable' is 1, else all zeros (gate)

• Fills — `{N{1'b0}}` and `{N{1'b1}}` are the width-independent all-zeros and all-ones, replacing hardcoded constants that break on resize (§1).
• Sign extension — replicating the sign bit N times and concatenating it ahead of the value widens a signed number correctly. Zero-extending instead (prepending 0s) corrupts negative values — the §5 trap.
• Conditional masks — `{N{ctrl}}` turns a single control bit into a full-width mask: XOR with it for a controllable inverter, AND with it to gate a bus on/off. (The conditional-invert idiom previewed in 10.4 is exactly this.)

Visual B — the three replication jobs

5. Sign Extension — Replicate the Sign, Don't Zero-Fill

Sign extension is the most important replication use to get right, because doing it wrong silently corrupts negative values — the signedness theme from 10.2/10.6/10.7, now in vector construction.

To widen a signed value, you must fill the new high bits with copies of the sign bit, not zeros:

   wire signed [7:0]  val;          // 8-bit signed, e.g. -1 = 8'hFF
   wire signed [15:0] wide;
 
   // CORRECT — replicate the sign bit (val[7]) 8 times, then the value:
   assign wide = {{8{val[7]}}, val};      // -1 → 16'hFFFF = -1   ✓
 
   // WRONG — zero-extend: prepend 8 zeros:
   assign wide = {8'b0, val};             // -1 → 16'h00FF = +255 ⚠ sign lost

The correct form `{{8{val[7]}}, val}` replicates val[7] (the sign bit) eight times and concatenates the value after it, so a negative value stays negative when widened. Zero-extending with `{8'b0, val}` makes −1 into +255. (This combines replication with concatenation, the comma-brace operator drilled in 10.10 — sign extension is the canonical place the two brace operators work together.)

Note: if the operand is declared signed and assigned to a wider signed target, Verilog sign-extends automatically — but explicit replication is the portable, unambiguous way, and is required whenever you assemble a vector by hand.

Visual C — sign extension by replication

6. Replication Lives Inside Concatenation

Replication and concatenation are the two brace operators, and they compose. Replication often appears inside a concatenation to build a structured vector:

   {{4{1'b0}}, data}          // zero-extend data by 4 bits  (replication + concat)
   {{8{val[7]}}, val}         // sign-extend (§5)
   {byte, {3{2'b10}}, flag}   // assemble a structured word from parts

`{n{x}}` is itself shorthand for the concatenation `{x, x, …, x}` (n copies). The full concatenation operator — joining different values with commas — is the next page (10.10); here the point is that replication is one ingredient you drop into a concatenation, most often to fill or extend. Sign extension (§5) is the canonical example of the two working together.

7. The Constant-Count Requirement

The replication count must be a constant known at elaboration — a literal or a parameter, never a runtime signal:

   {4{1'b1}}                 // OK — literal count
   {WIDTH{1'b1}}             // OK — parameter count (constant at elaboration)
   {n{1'b1}}                 // ERROR if 'n' is a runtime signal (reg/wire)

The reason is fundamental: the count sets the result width, and a hardware vector's width must be fixed at build time — you cannot have a wire bundle whose number of bits changes during operation. A variable shift is fine (the width is fixed, only the data moves), but a variable replication would imply a variable-width result, which has no hardware meaning. If you need a runtime-selectable width effect, use a fixed-width vector and mask or mux it — never a variable replication count.

8. Worked Examples

8.1 Example 1 — a width-independent all-ones mask

module masker #(parameter integer WIDTH = 8)(
    input  [WIDTH-1:0] data,
    output [WIDTH-1:0] result
);
    assign result = data & {WIDTH{1'b1}};    // all-ones mask, any WIDTH
endmodule

`{WIDTH{1'b1}}` builds a WIDTH-bit all-ones value that scales with the parameter — the §1 fix. Instantiate with any WIDTH and the mask is always full-width, unlike a hardcoded 8'hFF. (Here the mask is trivially data, but the pattern generalizes to any partial mask built from replication and concatenation.)

8.2 Example 2 — sign-extend a signed value

module sign_extend (
    input  signed [7:0]  narrow,
    output signed [15:0] wide
);
    assign wide = {{8{narrow[7]}}, narrow};   // replicate sign bit, then the value
endmodule

The canonical sign extension: replicate the sign bit narrow[7] eight times and concatenate the value, widening −1 to 16'hFFFF (still −1). Zero-extending would corrupt negatives (§5). This is replication and concatenation working together.

8.3 Example 3 — a conditional inverter

   // invert every bit of 'data' when 'invert_en' is 1, pass through when 0
   assign out = data ^ {WIDTH{invert_en}};

`{WIDTH{invert_en}}` replicates the single control bit across the full data width, turning it into a mask of all-invert_en. XOR-ing with it flips every bit when invert_en is 1 and passes data through when 0 — a one-line controllable inverter (the idiom previewed in 10.4). The same pattern with & (`data & {WIDTH{enable}}`) gates a bus on/off.

9. Industry Perspective

• Parameterized fills use replication. Reusable IP builds all-ones/all-zeros and partial masks with `{WIDTH{...}}` so they scale with the module's width parameters — never a hardcoded constant that breaks on configuration.
• Sign extension is everywhere in datapaths. Widening signed operands for arithmetic, ALUs, and DSP relies on sign-bit replication; getting it wrong (zero-extension) is a classic signedness bug, caught in review and lint.
• Conditional masks gate and invert buses. `{N{ctrl}}` to build a full-width mask from a control bit is a standard idiom for enables, controllable inverters, and conditional clears.
• Replication keeps RTL width-agnostic. Like reductions (10.5), replication lets logic scale with width parameters automatically, a key reason it is favored over fixed-width constants in reusable modules.

10. Common Mistakes

1. Hardcoding a width-locked fill instead of `{WIDTH{...}}` — breaks when the width changes (§1, DebugLab 1).
2. Zero-extending a signed value instead of replicating the sign bit — corrupts negatives (§5, DebugLab 2).
3. A variable (runtime) replication count — illegal; the count must be constant (§7, DebugLab 3).
4. Forgetting the inner braces — `{4 1'b1}` is a syntax error; it must be `{4{1'b1}}`.
5. Miscomputing the result width — it is count × value-width, not count alone.

11. Debugging Lab

12. Interview Q&A

13. Exercises

Exercise 1 — Evaluate the replications

Give the value and width of each: (a) {4{1'b0}}; (b) {2{4'hF}}; (c) {3{2'b10}}; (d) {8{1'b1}}; (e) {2{ {2{1'b1}} }}.

Exercise 2 — Build the construct

Write the replication (or replication-plus-concatenation) for each: (a) a WIDTH-bit all-ones; (b) sign-extend a signed 12-bit x to 16 bits; (c) zero-extend an unsigned 4-bit y to 8 bits; (d) a mask that is all-ones when en is 1 and all-zeros when en is 0, for an 8-bit bus.

Exercise 3 — Fix the construction

Each line states intent. Identify the bug and fix it.

mask  = data & 16'hFF;          // intent: all-ones mask for 16-bit data
wide  = {4'b0, sval};           // intent: sign-extend signed 12-bit sval to 16 bits
fill  = {n{1'b1}};              // intent: n leading ones, n is a runtime signal

Exercise 4 — Reason about width and signedness

(a) What is the width of {5{3'b101}}? (b) Why does {8'b0, val} corrupt a negative signed val but {{8{val[7]}}, val} does not? (c) Why is a variable shift allowed but a variable replication count not?

14. Summary

The replication operator repeats a value a constant number of times to build a wider one — the construction operator for fills, sign extension, and masks.

The core ideas:

• {count{value}} repeats value count times, result width = count × value-width, free wiring (no gates).
• The count must be a constant (literal or parameter) — a vector's width is fixed at elaboration; runtime counts are illegal.
• Three key uses: width-independent fills ({N{1'b1}}/{N{1'b0}}), sign extension (replicate the sign bit, {{N{val[MSB]}}, val}), and conditional masks ({N{ctrl}} → full-width mask).
• Sign-extend by replicating the sign bit, not by zero-filling — zero-extension corrupts negative values.
• Replication composes with concatenation (10.10) — it is the fill/extend ingredient dropped into a {} assembly.

The discipline this page instils:

• Build fills with {WIDTH{...}}, not hardcoded constants — width-independent and resize-safe.
• Sign-extend by replicating the sign bit — never zero-extend a signed value.
• Keep the replication count constant — drive runtime width effects with a shift or mask, not a variable count.

You can now repeat values to construct vectors. The next page covers the other brace operator — joining different values: Chapter 10.10 Concatenation Operator drills {a, b, c} — combining signals into a wider bus, splitting and reassembling fields, and the partner of replication in sign extension and vector assembly.

Related Tutorials

• Bitwise Operators — Chapter 10.4; the masks ({N{ctrl}}) replication builds for conditional invert/gate.
• Reduction Operators — Chapter 10.5; the other width-independent, parameter-scaling operator.
• parameter — Chapter 6.1; the constant counts that make replication width-independent.
• Arithmetic Operators — Chapter 10.2; the signedness theme that sign extension serves.