Operator Usage in Verilog

wire [7:0]  a = 8'd100;
wire [7:0]  b = 8'd200;
 
wire [7:0]  sum    = a + b;     // 100 + 200 = 300 → truncated to 8 bits → 44
wire [8:0]  sum_w  = a + b;     // 9-bit dest → 300 fits → result = 9'd300
wire [7:0]  diff   = a - b;     // 100 - 200 = -100 → as 2's complement 8-bit → 156
wire [15:0] prod   = a * b;     // 100 * 200 = 20 000 → fits in 16 bits
 
wire [7:0]  quot   = a / b;     // integer division — truncates toward zero
wire [7:0]  rem    = a % b;     // modulo — sign of result follows the dividend
wire [15:0] power  = a ** 2;    // exponentiation — `a` squared

wire [3:0] a = 4'b1100;
wire [3:0] b = 4'b1010;
 
wire [3:0] band  = a & b;        // 4'b1000
wire [3:0] bor   = a | b;        // 4'b1110
wire [3:0] bxor  = a ^ b;        // 4'b0110
wire [3:0] bnot  = ~a;           // 4'b0011
wire [3:0] bxnor = a ~^ b;       // 4'b1001 (equivalent: a ^~ b)

wire [3:0] a = 4'b1100;
wire [3:0] b = 4'b0000;
 
wire       land = a && b;        // (a != 0) AND (b != 0) → 1 && 0 → 0
wire       lor  = a || b;        // (a != 0) OR  (b != 0) → 1 || 0 → 1
wire       lnot = !a;            // NOT (a != 0)          → !1     → 0

wire [3:0] a = 4'b1100;
wire [3:0] b = 4'b0011;
 
wire [3:0] bw = a & b;           // BITWISE: bit-by-bit AND → 4'b0000
wire       lg = a && b;          // LOGICAL: (a!=0) && (b!=0) → 1 && 1 → 1
 
// Wait — `lg` is 1 even though `a & b` is 0? Yes. They mean different things.
// `&` answers "what's the bit-by-bit AND of these vectors?"
// `&&` answers "are both operands non-zero?"

// ✅ datapath — bitwise
assign masked_data = data & mask;          // & — bitwise
 
// ✅ conditional — logical
always @(posedge clk) begin
    if (en && !rst_n)                       // && — logical
        count_q <= count_q + 1'b1;
end

wire [7:0] data = 8'b1010_1100;
 
wire all_set    = &data;          // 1 if EVERY bit is 1 → 0 (data has 0s)
wire any_set    = |data;          // 1 if ANY bit is 1  → 1
wire parity     = ^data;          // XOR of every bit  → 0 (4 ones — even parity)
wire none_set   = ~|data;         // NOR — 1 if every bit is 0 → 0
wire all_zero_partner = ~&data;   // NAND — 1 if any bit is 0 → 1
wire even_parity_xnor = ~^data;   // XNOR — 1 if even parity  → 1

// FIFO full when every bit of the count register is 1
assign full = &count_q;
 
// Generate parity bit for outgoing data
assign parity_bit = ^data_out;
 
// Interrupt asserted when any source is pending
assign irq = |source_pending;

wire signed [7:0] s = -8'sd16;     // 8'b1111_0000 (two's complement -16)
wire        [7:0] u = 8'b1111_0000;
 
wire [7:0] sl  = u << 2;            // logical left  → 8'b1100_0000 (shifts in zeros)
wire [7:0] sr  = u >> 2;            // logical right → 8'b0011_1100 (shifts in zeros)
wire [7:0] al  = s <<< 2;           // arithmetic left  → 8'b1100_0000 (same as <<)
wire [7:0] ar  = s >>> 2;           // arithmetic right → 8'b1111_1100 (shifts in SIGN BIT)

wire        [7:0] u_data = 8'b1111_0000;
wire signed [7:0] s_data = 8'sb1111_0000;   // -16 as signed
 
wire [7:0] u_arith_right = u_data >>> 2;     // 8'b0011_1100 — zero-fill (unsigned)
wire [7:0] s_arith_right = s_data >>> 2;     // 8'b1111_1100 — sign-fill (signed)

wire [7:0] a = 8'd100;
wire [7:0] b = 8'd200;
 
wire lt  = a <  b;           // 1
wire le  = a <= b;           // 1
wire gt  = a >  b;           // 0
wire ge  = a >= b;           // 0

wire signed [7:0] s_neg  = -8'sd1;       // 8'b1111_1111 as signed = -1
wire        [7:0] u_zero = 8'd0;
 
wire lt = s_neg < u_zero;     // ❌ Expected: 1 (-1 < 0). Got: 0.
                              //   Why: `u_zero` is unsigned; the compare is
                              //   unsigned; s_neg is reinterpreted as 8'd255.
                              //   255 < 0 → 0. Silent bug.

wire lt_fixed = $signed(s_neg) < $signed(u_zero);   // ✅ 1

wire [3:0] q = 4'bxxxx;          // unknown
wire [3:0] z = 4'b0000;
 
wire eq2  = (q == z);            // ❌ Returns `x`, not `0` or `1`.
                                  //   In an `if (q == z)` this is treated as FALSE.
                                  //   So the branch is taken when q is X.
 
wire eq4  = (q === z);           // ✅ Returns `0` (every bit differs because q has X).
wire isx  = (q === 4'bxxxx);     // ✅ Returns `1` — q's bits ARE all X.
 
// Testbench rule: when checking for X, use ===
// RTL rule: never use === — it's testbench-only.

wire [7:0] mux2 = sel ? a : b;                       // 2:1 mux
wire [7:0] mux4 = sel[1] ? (sel[0] ? d : c)
                         : (sel[0] ? b : a);         // 4:1 mux as nested ternaries
wire [7:0] absolute = (data[7]) ? -data : data;      // absolute value
wire [7:0] saturate = (sum > MAX) ? MAX : sum;       // saturating clamp

wire [3:0] a = 4'h5;
wire [3:0] b = 4'hA;
 
// Concatenation — `{}` joins values left-to-right, MSB first
wire [7:0]  ab     = {a, b};              // 8'h5A  (a is upper, b is lower)
wire [11:0] abc    = {4'h0, a, b};        // 12'h05A (zero-pad)
wire [11:0] sign_ext = {{4{a[3]}}, a, b}; // 12'hF5A (sign-extend a to 12 bits)
 
// Replication — `{N{value}}` repeats value N times
wire [15:0] all_ones  = {16{1'b1}};       // 16'hFFFF
wire [15:0] all_zeros = {16{1'b0}};       // 16'h0000
wire [15:0] pattern   = {4{4'hA}};        // 16'hAAAA
wire [3:0]  mask      = {WIDTH{1'b1}};    // parameter-driven all-ones

module masked_bus #(parameter WIDTH = 8) (
    input  wire [WIDTH-1:0] data_in,
    input  wire             en,
    output wire [WIDTH-1:0] data_out
);
    // Mask data when not enabled — `en` is replicated WIDTH times
    assign data_out = data_in & {WIDTH{en}};
endmodule

// ❌ Expected: y = a AND b OR c → reader expects `(a & b) | c`
// Actual: Verilog evaluates as `a & (b | c)` because `|` is LOWER than `&` — wait no.
// Actually `|` is LOWER precedence than `&`, so `a & b | c` parses as `(a & b) | c`. ✅
// The actual trap is with relational operators:
 
wire bad = a + b > c;     // Parses as: (a + b) > c  ✅ (relational lower than arithmetic)
 
// But:
wire really_bad = a == b & c;    // Parses as: a == (b & c)
                                  // — because `&` is HIGHER than `==`.
                                  // Reader probably expected: (a == b) & c.
 
// Always parenthesise mixed-family expressions:
wire fixed = (a == b) & c;        // ✅ explicit

module sat_add_8b (
    input  wire signed [7:0] a,
    input  wire signed [7:0] b,
    output wire signed [7:0] sum_sat       // saturates to ±127 on overflow
);
 
    // 9-bit add preserves the sign bit through the operation
    wire signed [8:0] sum_ext = {a[7], a} + {b[7], b};
 
    // Overflow detected when bits [8] and [7] differ
    wire overflow_pos = (sum_ext[8] == 1'b0) && (sum_ext[7] == 1'b1);
    wire overflow_neg = (sum_ext[8] == 1'b1) && (sum_ext[7] == 1'b0);
 
    // Saturating mux — ternary cascade
    assign sum_sat = overflow_pos ? 8'sd127
                   : overflow_neg ? -8'sd128
                   : sum_ext[7:0];
 
endmodule