GLS · Topic
Timing Basics for Gate-Level Simulation
Setup, hold, propagation delay, clock skew and timing arcs — the timing concepts a gate-level simulation makes visible.
Gate-level simulation is where timing stops being an abstraction in a report and becomes behaviour you can watch. Understanding what setup and hold actually constrain — and that they constrain different edges of different clocks — is what makes a violation message readable. The concepts here are the same ones STA uses; the difference is that simulation shows the consequence rather than the margin.