Setup, Hold & Timing-Check Fundamentals

Chapter 3 · Section 3.2 · Timing Basics for GLS

Project thread — 3.1 classified the counter's cell delays (pin-to-pin arcs). This lesson adds the timing checks on the counter's flops that guard capture; 3.3 adds interconnect delay to the picture.

1. Why Should I Learn This?

Setup and hold are the two rules every synchronous design lives by. Understanding them lets you:

• Read a flop X as a timing-check firing, not noise.
• Know when GLS can flag a timing problem (and when it can't).
• Keep GLS and STA in their correct lanes — dynamic vs signoff.

This is the timing vocabulary the rest of the chapter (interconnect, corners, glitches) and Chapter 4 (SDF) build on.

2. Real Silicon Story — the "passing" timing that STA never blessed

A gate-level run with SDF passed with no timing-check violations, and the team read it as timing closed.

STA — run separately — flagged a setup violation on a path the testbench never exercised. The GLS "pass" only meant no stimulus had violated a check; it said nothing about the unexercised path. STA, which checks all paths regardless of stimulus, caught it.

Lesson: absence of a GLS timing-check violation is not timing closure. GLS checks are dynamic and stimulus-limited; STA is the exhaustive signoff.

3. Concept — the windows and the checks

The windows (around a rising clock edge):

• Setup time — data must be stable for t_su before the edge.
• Hold time — data must be stable for t_h after the edge.
• Violate either → the captured value is unreliable (metastable in silicon; X in sim).

The checks (system tasks in the cell's specify block):

• $setup (data, posedge clk, limit, notifier) — data steady before the edge.
• $hold (posedge clk, data, limit, notifier) — data steady after the edge.
• $width / $period — minimum pulse width / clock period.
• $recovery / $removal — async set/reset released a safe distance from the edge.

How a violation shows up: the check fires → toggles the notifier → the cell's UDP emits X on the output (2.5). A dynamic effect.

Scope: a check fires only if the stimulus violates it on that edge. STA checks every path statically — GLS does not prove all timing (0.3).

4. Mental Model — a quiet zone around the clock edge

Picture a quiet zone bracketing the clock edge: setup before, hold after. Data may change outside the zone freely; inside it must stay still.

• Change inside the zone → the flop can't tell old from new → unreliable capture.
• The timing check is a guard watching the quiet zone; if data moves inside it, the guard raises the alarm (notifier → X).
• But the guard only watches when data actually moves on a real edge — it does not survey every possible path. That surveying is STA's job.

5. Working Example — a flop with checks, and a hold violation waveform

A representative flop model with checks and a notifier:

// Rising-edge DFF with timing checks + notifier — REPRESENTATIVE, tool-neutral
module DFFX1 (Q, D, CK);
  output Q; input D, CK; reg notify;
  DFF_udp_n u0 (Q, D, CK, notify);     // sequential UDP (2.3), notifier wired in
  specify
    (CK => Q) = 0;                     // clk-to-Q arc (placeholder -> SDF, 3.1/Ch4)
    $setup (D, posedge CK, 0, notify); // D steady BEFORE CK
    $hold  (posedge CK, D, 0, notify); // D steady AFTER CK
    $width (posedge CK, 0, 0, notify); // min pulse width
  endspecify
endmodule

A representative STA timing report — the static view of the same path:

# STA setup report — REPRESENTATIVE, tool-neutral (this is STATIC, path-based)
Startpoint: u_cnt/q_reg[1]  (rising, CK)
Endpoint:   u_cnt/q_reg[2]  (rising, CK)
  data arrival time      1.84
  data required time     1.90   (clock period - setup - uncertainty)
  ----------------------------------
  slack (MET)            0.06
# STA checks EVERY such path. GLS only sees paths the stimulus exercises.

Practical context (representative, tool-neutral):

# STA and GLS are SEPARATE steps on the same netlist:
netlist/counter4.vg + lib(corner).lib + constraints.sdc  --STA-->  timing_report.rpt (+ SDF)
netlist/counter4.vg + lib/cells.v + sdf/counter4.sdf      --GLS-->  sim.log (+ waveform)
# STA = exhaustive static proof. GLS = dynamic functional confirmation with real delays.

Here is a hold violation as a real waveform:

6. Debugging Session — a clean GLS read as timing closure

7. Common Mistakes

• Reading "no GLS violation" as timing closure. Absence proves nothing — STA is signoff (0.3).
• Confusing setup and hold. Setup = before the edge; hold = after.
• Leaving checks active during reset / async crossings. Common false-fire sources (deep triage Ch8).
• Treating a notifier-X as a random glitch. It is a timing-check firing — diagnosable (2.5).
• Using the wrong corner for the check limits / SDF (3.4).

8. Industry Best Practices

• STA closes timing; GLS confirms function with real delays — keep the lanes distinct.
• Recognise notifier-X by its $setup/$hold message and triage real-vs-artifact.
• Match check limits / SDF to the signoff corner (3.4).
• Setup vs hold intuition: setup fails when logic is too slow; hold fails when a path is too fast/short.
• Do not gate reset-window / async-crossing checks without justification (Ch8).

Senior Engineer Thinking

• Beginner: "GLS had no timing violations, so timing is done."
• Senior: "GLS only tested the paths my stimulus drove. Timing closure is STA, across all corners. GLS confirms the design works with real delays and flags violations I happened to exercise."

The senior treats STA as signoff and GLS timing checks as a dynamic, stimulus-bounded complement.

Silicon Impact

Read "no GLS violation" as closure and you may skip or under-weight STA — letting a real setup/hold violation on an unexercised path reach silicon as an intermittent, corner-sensitive failure. Conversely, chasing every notifier-X as a real bug wastes effort on artifacts (reset-window checks, async crossings). The discipline: STA proves timing across all paths and corners; GLS timing checks dynamically confirm function and surface exercised violations. That split keeps timing bugs off the tape-out.

Engineering Checklist

• Used STA (all corners) for timing closure — not GLS.
• Treated GLS timing checks as a dynamic complement.
• Recognised notifier-X and triaged real-vs-artifact (Ch8).
• Matched check limits / SDF to the signoff corner (3.4).
• Did not read "no GLS violation" as timing proven.

Try Yourself

1. Instantiate the representative DFFX1 and clock it with D changing well clear of the edge — Q is clean.
2. Observe: now move a D transition into the hold window after posedge CK; the $hold check fires and Q goes X.
3. Change: move D earlier so it is stable through the window; re-run.
4. Expect: no violation, clean Q. Then note: you only tested the edges you drove — STA would check every path. Prove the scope to yourself.

Any free Verilog simulator supports specify timing checks and notifiers. Real check limits come from the .lib/SDF (vendor/PDK). No paid tool required.

Interview Perspective

• Weak: "Setup and hold are just timing numbers."
• Good: "Setup is the stability window before the clock edge, hold is after; a violation drives the flop output to X via the notifier."
• Senior: "Setup guards logic being too slow, hold guards a path being too fast. GLS timing checks fire dynamically only on stimulated violations, so they don't prove timing — STA does, statically, across all paths and corners. GLS is the functional complement."

9. Interview / Review Questions

10. Key Takeaways

• Setup = data stable before the clock edge; hold = data stable after it. Violate either and capture is unreliable (X in sim, metastable in silicon).
• Cell models watch the windows with timing checks — $setup, $hold, $width, $recovery, $removal — and a violation drives the flop output to X via the notifier (2.5).
• Gate-level timing checks are dynamic and stimulus-limited — they fire only on violations the stimulus exercises.
• STA checks every path statically and exhaustively — it is the timing signoff; GLS is the dynamic complement (0.3).
• "No GLS violation" ≠ timing closed. Absence proves nothing; met STA slack (all corners, 3.4) does. Next: 3.3 — interconnect delay & the post-layout picture.

Quick Revision

Setup = before the edge; hold = after. Cell models watch them with $setup/$hold/$width/$recovery/$removal; a violation → notifier → Q = X (dynamic). GLS checks are stimulus-limited; STA (static, exhaustive, all corners) is timing signoff. "No GLS violation" proves nothing. Next: 3.3 — interconnect delay.