Interconnect Delay & the Post-Layout Picture

Chapter 3 · Section 3.3 · Timing Basics for GLS

Project thread — 3.2 guarded the counter's flops with setup/hold. This lesson adds the wire delay between them once the counter is placed and routed; 3.4 then asks which process corner to simulate.

1. Why Should I Learn This?

"Works in sim" often means pre-layout sim — where wires are ideal. Silicon has wires.

• Post-layout, net RC delay changes arrival times and can expose races/glitches a pre-layout run never saw.
• The SPEF is where those net parasitics come from — a core ASIC artifact.
• Knowing the extraction → SPEF → SDF → GLS chain tells you when your gate run actually reflects silicon.

This bridges 3.2 (checks) to 3.4 (corners) and Chapter 4 (SDF).

2. Real Silicon Story — the race that only appeared after routing

A gate-level counter passed clean pre-layout. Post-layout — with extracted net delays — a control signal arrived late relative to its capture clock, and a downstream flop captured a stale value on one path.

The pre-layout run had ideal wires: zero net delay, so the arrival was "perfect." The real routed net had RC delay (from its length and fanout), captured in the SPEF, turned into an SDF interconnect delay, and only then visible in GLS.

Lesson: pre-layout GLS omits wire delay. Post-layout behaviour needs extracted parasitics (SPEF → SDF). A clean pre-layout run is not a post-layout guarantee.

3. Concept — pre-layout vs post-layout, and where net delay comes from

Two pictures:

• Pre-layout: delay = cell delays only; nets are ideal (zero or wire-load-model estimate).
• Post-layout: delay = cell delays + real net RC delay from the actual routing.

The post-layout flow (tool-neutral):

1. Place & route → physical layout.
2. Parasitic extraction → SPEF (each net's R and C).
3. Delay calculation → combines SPEF + .lib timing → SDF (cell arcs and interconnect delays).
4. Back-annotation → GLS applies the SDF (Chapter 4).

Key points:

• SPEF holds parasitics, not delays. Delay calc turns R/C into a delay number.
• The SDF now carries INTERCONNECT entries, not just cell IOPATH.
• Scope: representative; even post-layout GLS is dynamic — STA (all corners) is signoff (0.3).

4. Mental Model — wires are components too

Pre-layout, you treat wires as free zero-delay connectors. Post-layout, a wire is a component with its own delay.

• A long, high-fanout net is a slow wire — it delays the signal like an extra buffer would.
• The SPEF is the wire's datasheet (its R and C); delay calc reads it to compute the wire's delay.
• Add wire delay to cell delay and you get the real path delay — the post-layout picture.

Ideal-wire sim is a sketch; post-layout sim is the photograph.

5. Working Example — SPEF, the resulting SDF, and a pre/post waveform

A representative SPEF fragment — parasitics for one net:

# SPEF — REPRESENTATIVE, tool-neutral (parasitics, NOT delays)
*D_NET u_cnt/n1 4.21              # total capacitance of net n1 (fF)
*CONN
  *P u_cnt/n1 O                   # driver pin
  *I u_cnt/u_q1/D I               # load pin
*RES
  1 u_cnt/n1:1 u_cnt/n1:2 12.4    # a resistance segment (ohms)
*END
# SPEF carries R and C. Delay calc turns these into a delay number -> SDF.

The delay-calc output — an SDF now with interconnect delay:

# SDF (Chapter 4) — REPRESENTATIVE — note the INTERCONNECT entry (new, post-layout)
(INSTANCE u_cnt)
  (DELAY (ABSOLUTE
    (IOPATH A Y (0.062))                 # cell arc (as before, 3.1)
    (INTERCONNECT u_cnt/u_x1/Y u_cnt/u_q1/D (0.045)))))  # NET delay from SPEF

Practical context (representative, tool-neutral):

pnr/counter4.def          # routed layout
extract/counter4.spef     # parasitics  <- THIS lesson
sdf/counter4.post.sdf     # cell arcs + INTERCONNECT (from delay calc)
# Flow position: ... synthesis -> P&R -> EXTRACTION(SPEF) -> delaycalc(SDF) -> post-layout GLS / STA signoff

Pre-layout vs post-layout arrival, as a real waveform:

6. Debugging Session — clean pre-layout, broken post-layout

7. Common Mistakes

• Treating pre-layout GLS as post-layout truth. Ideal wires omit net delay entirely.
• Thinking SPEF contains delays. It holds R/C; delay calc produces the delay.
• Forgetting INTERCONNECT entries exist in a post-layout SDF (not just cell IOPATH).
• Using the wrong corner for extraction/SDF (3.4).
• Claiming any GLS run proves timing. STA on extracted parasitics is signoff (0.3).

8. Industry Best Practices

• Run post-layout GLS with the extracted (SPEF-derived) SDF for arrival-sensitive behaviour.
• Keep pre-layout GLS for function, post-layout for the real-delay picture.
• Know the chain: layout → extraction (SPEF) → delay calc → SDF → GLS/STA.
• Match the corner across extraction, SDF, and STA (3.4).
• STA (all corners) closes timing; GLS confirms function with real delays.

Senior Engineer Thinking

• Beginner: "It passed in gate sim, so the wires are fine."
• Senior: "Was that pre-layout? Then wires were ideal. Real net RC comes from the SPEF into the SDF — I need the post-layout run for arrival, and STA on the extracted parasitics for signoff."

The senior distinguishes ideal-wire from extracted-wire sims and knows net delay originates in the SPEF.

Silicon Impact

Net delay is not a rounding error — long, high-fanout nets can dominate a path. Trust a pre-layout "pass" and you can miss a post-layout race or late-arrival capture that becomes an intermittent silicon failure. The SPEF (via delay calc → SDF) is what puts real wire delay into GLS, and STA on those same parasitics is what proves timing across corners. Running only ideal-wire sims is verifying a design that does not physically exist yet.

Engineering Checklist

• Ran arrival-sensitive checks with the post-layout (SPEF-derived) SDF.
• Understood SPEF = parasitics; delay calc = the delay.
• Confirmed the SDF has INTERCONNECT (net) delays post-layout.
• Matched the corner across extraction / SDF / STA (3.4).
• Relied on STA (all corners) for timing closure, GLS for function.

Try Yourself

1. Simulate the representative netlist with no interconnect delay (ideal wires) — note the load D tracks the driver instantly.
2. Observe: the capture edge sees the new value immediately (pre-layout picture).
3. Change: add a small explicit net delay (or annotate a tiny SDF with an INTERCONNECT entry) between driver and load.
4. Expect: D now arrives later; if it crosses the capture edge, the flop grabs the old value — the post-layout race, reproduced.

Any free Verilog simulator can model a net delay (buffer or SDF INTERCONNECT). Real SPEF/extraction are EDA/PDK artifacts, but the concept is identical. No paid tool required.

Interview Perspective

• Weak: "Wires don't add delay in simulation."
• Good: "Post-layout, nets have RC delay; extraction produces a SPEF, delay calc turns it into SDF interconnect delay for GLS."
• Senior: "Pre-layout GLS uses ideal wires; post-layout arrival comes from the SPEF via the SDF's INTERCONNECT entries. A clean pre-layout run doesn't prove post-layout timing — and STA on the extracted parasitics, across corners, is the actual signoff."

9. Interview / Review Questions

10. Key Takeaways

• Pre-layout delay = cell delays only (ideal wires); post-layout delay = cell delays + real net RC delay.
• Net delay reaches GLS via a chain: layout → parasitic extraction (SPEF) → delay calc → SDF (INTERCONNECT) → back-annotation (Chapter 4).
• SPEF holds parasitics (R, C), not delays — delay calculation converts them into the delay numbers.
• A clean pre-layout run does not prove post-layout timing — net delay can expose new races, late captures, and shifted glitches.
• Even post-layout GLS is dynamic — STA on the extracted parasitics (all corners, 3.4) is the timing signoff (0.3). Next: 3.4 — timing corners: which corner to simulate & why.

Quick Revision

Pre-layout = cells only (ideal wires); post-layout = cells + net RC. Chain: layout → extraction (SPEF) → delay calc → SDF INTERCONNECT → GLS (Ch4). SPEF = parasitics, not delays. A clean pre-layout run ≠ post-layout timing (new races/late captures). STA on the parasitics (all corners) is signoff. Next: 3.4 — timing corners.