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GLS · Chapter 3 · Timing Basics for GLS

Timing Corners: Which Corner to Simulate & Why

A design is not fast or slow at a single speed. Its delays shift with process, voltage, and temperature, together called the PVT corners. The library is characterised per corner and the SDF is generated per corner, so which corner you annotate decides the delays your gate-level simulation sees. Two corners frame the extremes: the slow corner has maximum delay and stresses setup, asking whether the logic is fast enough, while the fast corner has minimum delay and stresses hold, asking whether data holds long enough past the edge. This lesson explains the corners, which one to reach for and why, and the boundary that matters most: a gate run at one corner is only a sample, while static timing analysis across all corners is the actual timing signoff.

Foundation12 min readGLSCornersPVTSetupHold

Chapter 3 · Section 3.4 · Timing Basics for GLS

Project thread — 3.3 put real net delay on the counter's paths. This lesson asks at which corner those delays are measured; 3.5 then looks at glitches, which corners also affect.

1. Why Should I Learn This?

The same netlist has different delays at different corners. If you annotate the wrong SDF, your gate run can look healthy while a real problem hides at another corner.

  • Setup problems surface at the slow corner (max delay).
  • Hold problems surface at the fast corner (min delay).
  • Models and SDF must be from the same corner or the picture is inconsistent.

This completes the "which delays" question (3.1 types, 3.3 interconnect) and feeds Chapter 4 (SDF is per-corner).

2. Real Silicon Story — the setup bug that hid at the fast corner

A team ran GLS with a fast-corner (FF) SDF — the delays were short, everything captured comfortably, no violations.

STA at the slow corner (SS) flagged a setup violation: at max delay the logic did not finish before the capture edge. The fast-corner GLS could not have shown it — its delays were the shortest, precisely the case where setup is easiest to meet.

Lesson: setup is a slow-corner concern. A gate run at the wrong corner hides corner-specific problems. Only STA across all corners covers them.

3. Concept — PVT corners and which one stresses what

PVT = the three axes of delay variation:

  • Process — fabrication spread: SS (slow), TT (typical), FF (fast).
  • Voltage — lower voltage → slower; higher → faster.
  • Temperature — affects mobility (can slow or speed depending on node).

Per-corner artifacts:

  • The .lib is characterised per corner (slow-corner lib, fast-corner lib, …).
  • The SDF is generated per corner from the matching .lib.
  • Annotating a corner's SDF makes GLS see that corner's delays.

Which corner for which check:

  • Setup → slow corner (max delay): worst case for "is logic fast enough?"
  • Hold → fast corner (min delay): worst case for "does data hold past the edge?"

Scope: a GLS run uses one SDF = one corner = a sample. STA runs all corners — it is the signoff (0.3). Do not claim single-corner GLS proves timing.

PVT corners: slow SS stresses setup, fast FF stresses hold, typical TT in between; .lib and SDF are per corner, STA covers allper cornersetup runhold runcovers allSlow corner (SS)MAX delay -> stresses SETUPTypical (TT)nominal delayFast corner (FF)MIN delay -> stresses HOLD.lib per cornercharacterised at each PVTpointSDF per cornerGLS annotates ONE cornerSTA: ALL cornersexhaustive timing signoff12
Figure 1 — PVT corners and what each stresses (representative). Process spreads from SS (slow, max delay) through TT (typical) to FF (fast, min delay); voltage and temperature shift delay further. The .lib is characterised per corner and the SDF is generated per corner. The SLOW corner (SS) stresses SETUP (is logic fast enough?); the FAST corner (FF) stresses HOLD (does data hold long enough?). A GLS run annotates ONE corner's SDF; STA runs ALL corners for signoff.

4. Mental Model — the same runner on a hot day and a cold day

A cell is like a runner whose speed depends on conditions.

  • Slow corner = tired runner (hot, low voltage, slow silicon) → arrives late → setup is the risk.
  • Fast corner = fresh runner (cold, high voltage, fast silicon) → arrives early → hold is the risk.
  • The .lib/SDF is the stopwatch reading for that condition.

One GLS run times one condition. STA times all of them — that is why STA, not a single gate run, closes timing.

5. Working Example — per-corner SDF, and a slow-vs-fast waveform

The same arc, two corner SDFs — different numbers:

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
# SDF, SLOW corner (SS) — REPRESENTATIVE — MAX delays (stresses setup)
(INSTANCE u_x1) (DELAY (ABSOLUTE (IOPATH A Y (0.121)))))
Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
# SDF, FAST corner (FF) — REPRESENTATIVE — MIN delays (stresses hold)
(INSTANCE u_x1) (DELAY (ABSOLUTE (IOPATH A Y (0.041)))))

Practical context (representative, tool-neutral):

Azvya Education Pvt. Ltd.VLSI Mentor
Snippet
lib/
  cells_ss.lib   cells_tt.lib   cells_ff.lib     # per-corner libraries
sdf/
  counter4_ss.sdf   counter4_ff.sdf              # per-corner SDFs
# GLS:  annotate ONE (e.g. _ss for a setup-flavoured run, _ff for hold)
# STA:  runs ALL corners -> the signoff. Keep cell models + SDF on the SAME corner.

Same path, slow vs fast corner, as a real waveform:

Same path, two corners: slow-corner (late) vs fast-corner (early) arrival at the capture edge

8 cycles
A data path result arrives late at the slow corner and early at the fast corner relative to the same clock edgeSS arrives late → setup riskSS arrives late → setu…FF arrives early → hold riskFF arrives early → hol…CKD slow (SS)D fast (FF)t0t1t2t3t4t5t6t7
Representative. At the slow corner the path result arrives late (setup pressure). At the fast corner the same path arrives early (hold pressure). One GLS run sees only one of these; STA evaluates both extremes and everything between.

6. Debugging Session — a healthy gate run that hid a setup bug

1

A GLS run at the fast corner shows no violations, but STA at the slow corner flags a setup violation — the fast-corner SDF has the shortest delays, exactly where setup is easiest, so it could never expose a slow-corner setup problem

SETUP HIDES AT FAST; HOLD HIDES AT SLOW
Symptom

GLS with a fast-corner (FF) SDF runs clean. STA at the slow corner (SS) reports a setup violation on a path.

Root Cause

Setup asks "is the logic fast enough to arrive before the capture edge?" — worst at max delay, the slow corner. A fast-corner SDF has the shortest delays, so logic arrives earliest and setup is easiest to meet: the fast-corner GLS cannot reveal a slow-corner setup problem. The run was healthy for the corner it used — but that corner was the wrong one for a setup question. (Symmetrically, a hold problem hides at the slow corner and shows at the fast corner.)

Fix

Match the corner to the check: slow for setup-flavoured runs, fast for hold-flavoured runs — and keep the cell models and SDF on the same corner (a mixed-corner annotation is meaningless). But the real fix is scope: STA across all corners is the timing signoff, not any single GLS run. Use GLS to functionally confirm behaviour with real delays at a chosen corner; rely on STA for the exhaustive, all-corner proof (0.3). Never conclude "timing OK" from one corner's clean gate run.

7. Common Mistakes

  • Running one corner and calling timing done. Setup hides at fast, hold hides at slow — one corner can't see both.
  • Mixing corners between cell models and SDF — an inconsistent, meaningless run.
  • Assuming "fast corner = best case, safe." Fast corner is the worst case for hold.
  • Forgetting voltage/temperature, not just process — all three shift delay.
  • Treating single-corner GLS as signoff. STA (all corners) is signoff (0.3).

8. Industry Best Practices

  • Match corner to check: slow → setup, fast → hold.
  • Keep models and SDF on one corner per run.
  • Rely on STA across all corners for closure; GLS confirms function per corner.
  • Track the full PVT point, not just process letters.
  • Document which corner a given GLS run used (reproducibility).

Senior Engineer Thinking

  • Beginner: "Gate sim was clean, timing's fine."
  • Senior: "Which corner? Setup hides at fast, hold at slow. One GLS corner is a sample; STA across all corners is the signoff. And were the models and SDF the same corner?"

The senior always asks which corner and defers closure to all-corner STA.

Silicon Impact

Silicon ships across the whole PVT space — every corner is a real chip somewhere. Verify one corner and treat it as closure, and a setup bug (slow corner) or hold bug (fast corner) can reach production as a part that fails only hot, or only cold, or only on slow/fast silicon — the hardest field failures to reproduce. STA across all corners exists precisely because one condition never represents the population. GLS at a chosen corner confirms function with real delays; it does not replace all-corner STA.

Engineering Checklist

  • Matched corner to check (slow → setup, fast → hold).
  • Kept cell models and SDF on the same corner.
  • Relied on STA across all corners for timing closure.
  • Considered voltage and temperature, not just process.
  • Recorded which corner each GLS run used.

Try Yourself

  1. Annotate the representative netlist with the slow-corner SDF ((IOPATH A Y (0.121))) and check a tight path against the clock — setup pressure appears.
  2. Observe: at max delay the result arrives late relative to the capture edge.
  3. Change: re-annotate with the fast-corner SDF (0.041) and re-run.
  4. Expect: the setup pressure vanishes (early arrival) — but now a hold-sensitive path is the one at risk. Prove that no single corner shows both.

Any free Verilog simulator with $sdf_annotate can swap SDFs. Real per-corner .lib/SDF are foundry/PDK artifacts, but the corner concept is identical. No paid tool required.

Interview Perspective

  • Weak: "A cell has one delay."
  • Good: "Delays shift with process, voltage, temperature; the .lib and SDF are per corner."
  • Senior: "Setup is a slow-corner concern, hold a fast-corner concern, because they stress max and min delay respectively. A GLS run annotates one corner — a sample. STA across all corners is signoff, and I keep the cell models and SDF on the same corner."

9. Interview / Review Questions

10. Key Takeaways

  • Delay varies across PVT corners — process (SS/TT/FF), voltage, temperature — so the .lib and SDF are generated per corner.
  • The corner you annotate decides what GLS sees: setup problems surface at the slow corner (max delay), hold problems at the fast corner (min delay).
  • Keep cell models and SDF on the same corner — a mixed-corner run is meaningless.
  • A single-corner GLS run is a sample, not closure — setup hides at fast, hold hides at slow.
  • STA across all corners is the timing signoff (0.3); GLS confirms function with real delays at a chosen corner. Next: 3.5 — pulse rejection & glitch behaviour.

Quick Revision

PVT corners shift delay: SS (slow, max) stresses setup; FF (fast, min) stresses hold. The .lib and SDF are per corner; GLS annotates one (keep models + SDF same corner). One corner = a sample — STA across all corners is signoff. Next: 3.5 — pulse rejection & glitches.