Delay Types: Distributed, Lumped & Pin-to-Pin

Chapter 3 · Section 3.1 · Timing Basics for GLS

Project thread — the counter you read in 2.6 has AND/XOR/DFF cells, each carrying specify pin-to-pin arcs (2.4). This lesson classifies those arcs among the delay types; 3.2 adds setup/hold; Chapter 4 fills them with real SDF numbers.

1. Why Should I Learn This?

Every gate-level delay you ever annotate lands in one of three models. If you do not know which, you cannot reason about where a number goes or why a run has no timing.

• Standard cells are pin-to-pin — the model SDF targets.
• Distributed/lumped are older, coarser styles you will still meet in behavioural models.
• A cell has delay structure (the arc) but no value until SDF — this is why the counter updated instantly in 2.6.

This sets up the whole timing chapter (3.2 checks, 3.3 interconnect, 3.4 corners, 3.5 glitches) and Chapter 4 (SDF).

2. Real Silicon Story — the delay that was written but never applied

A team adds delays to a behavioural block using a single output delay (lumped), then reuses the same mental model on a synthesized netlist — assuming one delay per cell "covers it."

Post-layout, paths behaved differently. The netlist's cells used pin-to-pin arcs (A=>Y, B=>Y — different per input pin), and the real values came from an SDF that had never been annotated. The lumped assumption hid that each input-to-output path has its own delay, and that all of them were still zero without SDF.

Lesson: delay lives in a specific model. Standard cells are pin-to-pin, one arc per input→output path, and those arcs are placeholder until an SDF fills them (Chapter 4).

3. Concept — three delay models, and which cells use which

• Distributed delay — a delay on each primitive inside a module. Delay accumulates as signals ripple through internal gates.
• Lumped delay — one delay, placed at the module output (on the last gate). Simple, but loses per-path detail.
• Pin-to-pin (path) delay — declared in specify: (A => Y) = d;. Models each input-pin → output-pin path directly, independent of internal structure.

Key facts:

• Standard cells use pin-to-pin (specify) delays. One arc per input→output path (A=>Y, B=>Y, CK=>Q).
• SDF annotates pin-to-pin arcs. The SDF IOPATH entries map straight onto specify arcs (Chapter 4).
• Arc structure ≠ delay value. The arc exists in the model; its number is 0/nominal until SDF (2.4).
• Scope: representative; without SDF a gate run is zero-delay — not a timing proof (0.3/0.4).

4. Mental Model — the arc is a labelled pipe; SDF is the water

Think pin-to-pin: each specify arc is a labelled pipe from an input pin to an output pin.

• The pipe defines where delay can flow (which pin affects which output).
• The pipe ships empty — its value is a placeholder.
• SDF is the water poured into the pipe (Chapter 4).

So a cell having arcs tells you the structure is there — not that any delay is present. A bare run: pipes installed, no water → zero-delay.

5. Working Example — pin-to-pin arcs on the counter's cells

A representative combinational cell shows two distinct pin-to-pin arcs:

// Standard cell with PIN-TO-PIN (specify) delays — REPRESENTATIVE, tool-neutral
module XOR2X1 (Y, A, B);
  output Y; input A, B;
  xor (Y, A, B);                 // function (2.3)
  specify
    (A => Y) = 0;                // arc A->Y  (placeholder -> SDF)
    (B => Y) = 0;                // arc B->Y  (a DIFFERENT path, its own value)
  endspecify
endmodule

The SDF later gives each arc its own per-instance number:

# SDF (Chapter 4) — REPRESENTATIVE — one IOPATH per pin-to-pin arc, per instance
(INSTANCE u_x1)
  (DELAY (ABSOLUTE
    (IOPATH A Y (0.062))     # fills (A => Y) for THIS instance
    (IOPATH B Y (0.058)))))  # fills (B => Y) — note: not the same as A=>Y

Practical context (representative, tool-neutral):

gls/
  rtl/counter4.v          # design (Ch1/2 thread)
  netlist/counter4.vg     # synthesized netlist (2.6)
  lib/cells.v             # cell Verilog models (specify arcs) <- THIS lesson
  sdf/counter4.sdf        # per-instance arc values (Ch4)
  tb/tb_counter4.v
 
# Representative compile/run (tool-neutral):
#   compile:  <sim> lib/cells.v netlist/counter4.vg tb/tb_counter4.v
#   run:      (no SDF) -> arcs are zero -> zero-delay functional run
#   run+sdf:  $sdf_annotate("sdf/counter4.sdf", u_dut) -> arcs carry real delays (Ch4)

Here is the same A=>Y arc with and without a value — a real waveform:

6. Debugging Session — a "timed" gate run that is actually zero-delay

7. Common Mistakes

• Assuming one delay per cell (lumped) on a pin-to-pin netlist. Each input→output path has its own arc/value.
• Reading specify arcs as real delays. They are placeholders until SDF (2.4).
• Calling a no-SDF run "timed." No SDF → zero-delay, regardless of arc richness.
• Confusing arc structure with delay value. Structure is in the model; value is in the SDF.
• Treating SDF-annotated GLS as a full timing proof. It is stimulus-limited; STA is exhaustive (0.3).

8. Industry Best Practices

• Know the model: standard cells are pin-to-pin; SDF targets those arcs.
• Back-annotate an SDF for any timing GLS — arcs are empty otherwise.
• Label runs by mode (zero-delay functional vs SDF-annotated).
• Match the corner across models and SDF (3.4).
• Keep GLS and STA roles distinct — dynamic vs static/exhaustive (0.3).

Senior Engineer Thinking

• Beginner: "Every cell has a specify block, so my gate sim is timed."
• Senior: "Those are pin-to-pin arcs — structure. Did I annotate an SDF for the right corner? If not, every arc is zero and this is a functional run."

The senior separates arc structure from delay value, and knows real numbers arrive via SDF.

Silicon Impact

Mistaking arc structure for real timing leads teams to skip the SDF-annotated run and let timing-dependent bugs escape to silicon (the post-layout escape, 0.3). Pin-to-pin arcs are the scaffolding every real delay hangs on — but scaffolding is not the building. The values come from SDF for the signoff corner (Chapter 4 / 3.4), and even then GLS is a dynamic complement to STA, not a replacement.

Engineering Checklist

• Identified the delay model (standard cells → pin-to-pin arcs).
• Confirmed each input→output path has its own arc.
• Back-annotated an SDF for any timing run (Chapter 4).
• Labelled the run (zero-delay functional vs SDF-annotated).
• Kept GLS distinct from STA (dynamic vs exhaustive).

Try Yourself

1. Compile the representative XOR2X1 model with (A => Y) = 0; and toggle A.
2. Observe: Y follows instantly — the arc exists but its value is 0.
3. Change: add a temporary explicit delay ((A => Y) = 2;) or annotate a tiny SDF, and re-run.
4. Expect: Y now changes a delay after A. Same arc, different value — proving structure vs value.

Any free Verilog simulator supports specify and $sdf_annotate. Real cell arcs and SDF are vendor/PDK artifacts, but the mechanics are identical. No paid tool required.

Interview Perspective

• Weak: "Delay is just a number on the gate."
• Good: "Verilog models delay three ways — distributed, lumped, pin-to-pin; standard cells use pin-to-pin specify arcs."
• Senior: "Standard cells are pin-to-pin: one arc per input→output path. The arc is structure; the value comes from an SDF, per instance, per corner. No SDF means zero-delay — and even SDF-GLS is dynamic, not a timing signoff."

9. Interview / Review Questions

10. Key Takeaways

• Verilog models delay three ways: distributed (per-primitive), lumped (one at the output), pin-to-pin (specify arcs per input→output path).
• Standard cells use pin-to-pin arcs — one per path (A=>Y, B=>Y, CK=>Q) — and an SDF back-annotates exactly these.
• Arc = structure, SDF = value. Arcs exist in the model but hold placeholder (zero) delay until SDF (Chapter 4).
• A cell model having specify arcs does not mean a run is timed — no SDF means zero-delay (0.4).
• SDF-annotated GLS is dynamic/stimulus-limited — not a replacement for STA (0.3). Next: 3.2 — setup, hold & timing-check fundamentals.

Quick Revision

Three delay models: distributed, lumped, pin-to-pin. Standard cells = pin-to-pin specify arcs (one per input→output path), the target of an SDF. Arc = structure; SDF = value — no SDF means zero-delay. SDF-GLS is dynamic, not a timing signoff. Next: 3.2 — setup, hold & timing checks.