Case Study — Flip-Flop: Making One Bit Testable

Chapter 14 · Section 14.1 · Industry Case Studies — chapter opener

Project thread — THE single flip-flop that started the thread, now made testable: the seed. 14.2 stitches several into a counter; 14.6 scales it to millions.

1. Why Should I Learn This?

The single-bit case is the atom of all DFT — master how one bit becomes controllable and observable, and every later structure is just more of it, organized.

• A plain D-FF is not controllable/observable in isolation — test needs to set a value in and read it out (defects, not bugs).
• The scan (mux-D) cell adds both: a mux on D (SE selects functional-D vs SI) + Q → next SI.
• Test intent for one bit: shift-0/capture/observe and shift-1/capture/observe → detect Q stuck-at-0/1.
• Cost: a scan-mux setup penalty (12.1/12.2). Debug it structure-first (flush/fork, 13.1/13.2).

2. Real Silicon Story — the one bit that no test could reach

A block had a single control flip-flop deep in its logic that no test pattern could reach — its D was driven by a long combinational cone, and its Q fanned into logic that masked its value at every observable point. A defect on that flop escaped to the field.

The fix was to make that one bit testable — the atom of scan. The flop was converted to a mux-D scan cell: a mux on D (select functional-D in normal mode, scan-in in test) and Q threaded into the scan path. Now the bit was controllable (shift a known value straight into it, bypassing the deep cone) and observable (shift its captured value straight out, bypassing the masking logic). With two patterns — shift-0/capture/observe and shift-1/capture/observe — its stuck-at-0 and stuck-at-1 faults became detectable, and the escape class was closed. Lesson: manufacturing test needs control + observe of the physical node, and a plain flip-flop provides neither in isolation. The scan (mux-D) cell provides both — one bit is the foundation; every scan chain, counter, FSM, and IP in the rest of the track is this cell, replicated.

3. Factory Perspective — one testable bit through each lens

• What the test engineer sees: the two patterns (shift-0/1, capture, observe) that detect the bit's stuck-at faults — the smallest unit of a pattern set.
• What the RTL/DV engineer sees: a plain FF that must become scan-friendly — don't block its D or bury its Q so DFT can insert the mux-D cleanly (4.x).
• What the STA engineer sees: the scan-mux setup penalty on the functional-D path and the new shift path (hold) — the timing cost of one bit (12.1/12.2).
• What management cares about: that every state bit is testable — one unreachable bit is a coverage hole and a potential escape (2.x/1.5).

4. Concept — control + observe, the mux-D cell, one-bit test

The problem (control + observe):

• A plain D flip-flop in isolation is not controllable (you can't force its D from the pins through deep logic) and not observable (you can't read its Q through masking logic).
• Manufacturing test (defects) needs both: set a known value IN, read the value OUT. (This is distinct from verification, which finds bugs — test needs physical control + observe.)

The fix (the scan/mux-D cell, 3.2):

• Add a mux on D: scan_enable = 0 → D = functional-D (normal); scan_enable = 1 → D = scan-in (SI) (shift).
• Thread Q to the next cell's SI (or the scan-out for a 1-cell chain).
• Now the bit is CONTROLLABLE (shift a value in) and OBSERVABLE (shift its captured value out). One bit = the atom of scan.

Test intent for one bit (stuck-at, 2.2):

• Shift in 0 → capture → shift out (expect 0): detects Q stuck-at-1 (a stuck-at-1 makes it read 1).
• Shift in 1 → capture → shift out (expect 1): detects Q stuck-at-0.
• Also exercises the mux/SI path (a broken SI/mux shows up as a flush failure).

The cost (timing, 12.1/12.2):

• The scan mux adds a setup penalty on the functional-D path (an extra mux delay before the flop).
• The shift path (SI → cell → next SI) has its own hold requirement (12.2 shift=hold). One bit shows the whole tradeoff in miniature.

The atom:

• A chain (3.3) is many of these cells; a counter (14.2) is a few; an IP (14.6) is millions. Every later case is this bit, replicated and organized.

5. Mental Model — a light switch you can reach vs one behind a wall

A plain flip-flop deep in logic is a light switch sealed behind a wall; a scan cell is that switch with a pull-cord and an indicator lamp you can reach from the hallway.

• The switch is the bit; you want to set it (control) and know its state (observe). Sealed behind a wall (deep logic), you can neither flip it nor see it — you'd have to demolish the room (drive a huge combinational cone) just to toggle one switch, and even then you can't tell if it worked (its effect is masked downstream).
• The scan mux is a pull-cord run out to the hallway (the scan path): pull it one way and the switch takes the room's wiring (functional-D); pull it the other and it takes your cord (scan-in) — now you set it directly. And the indicator lamp (Q threaded to the scan-out) lets you read its state from the hallway without entering the room.
• Testing the switch is then trivial: set it OFF, check the lamp is OFF; set it ON, check the lamp is ON (shift-0/observe, shift-1/observe) — that proves the switch isn't stuck. The cord costs a little friction on the room's own wiring (the setup penalty), but it turns an unreachable switch into a fully controllable, observable one.

A sealed switch you can't reach (plain FF) becomes a pull-cord-and-lamp you operate from the hallway (scan cell) — set it and read it directly; test it by toggling and watching the lamp.

6. Working Example — the RTL: plain D-FF → scan cell

Ship the RTL for one bit, before and after (representative; SV/Verilog/VHDL):

// SystemVerilog - the ATOM, before and after (REPRESENTATIVE)
// (1) plain D flip-flop - NOT controllable/observable in isolation
module dff (input logic clk, input logic d, output logic q);
  always_ff @(posedge clk) q <= d;
endmodule
 
// (2) scan (mux-D) flip-flop - controllable (SI) + observable (Q->SO)
module scan_dff (
  input  logic clk,
  input  logic d,          // functional data
  input  logic si,         // scan-in
  input  logic scan_enable,// SE: 1=shift, 0=capture
  output logic q           // functional out AND scan-out
);
  logic d_mux;
  assign d_mux = scan_enable ? si : d;   // the mux on D
  always_ff @(posedge clk) q <= d_mux;   // one FF, now scannable
endmodule

// Verilog-2001 - scan (mux-D) flip-flop (REPRESENTATIVE)
module scan_dff (clk, d, si, scan_enable, q);
  input  clk, d, si, scan_enable;
  output q;
  reg    q;
  wire   d_mux = scan_enable ? si : d;   // mux on D
  always @(posedge clk) q <= d_mux;
endmodule

-- VHDL - scan (mux-D) flip-flop (REPRESENTATIVE)
library ieee; use ieee.std_logic_1164.all;
entity scan_dff is
  port ( clk, d, si, scan_enable : in  std_logic;
         q                       : out std_logic );
end entity;
architecture rtl of scan_dff is
  signal d_mux : std_logic;
begin
  d_mux <= si when scan_enable = '1' else d;  -- mux on D
  process (clk) begin
    if rising_edge(clk) then q <= d_mux; end if;
  end process;
end architecture;

The two-pattern test detects the bit's stuck-at faults:

# One-bit test intent (stuck-at) - REPRESENTATIVE, tool-neutral:
  SCAN STRUCTURE: a 1-cell chain -> SI -> [scan_dff] -> Q(=SO)
  PATTERN 1: SE=1, shift in 0 ; SE=0, capture ; SE=1, shift out -> expect 0   -> if reads 1 -> Q STUCK-AT-1 detected
  PATTERN 2: SE=1, shift in 1 ; SE=0, capture ; SE=1, shift out -> expect 1   -> if reads 0 -> Q STUCK-AT-0 detected
  (a broken SI/mux/clock shows up as a FLUSH failure - the shifted value never appears)
# Two patterns detect Q stuck-at-0 AND stuck-at-1 for ONE bit. CONTROL (shift in) + OBSERVE (shift out) = testable.

The waveform shows shift-in, capture, shift-out for one bit:

7. Industry Flow — from a plain bit to a tested bit

The one-bit flow: identify the plain FF, insert the mux-D scan cell, generate the 2-pattern test, close the timing, debug structure-first:

8. Debugging Session — a single scan cell that won't observe its value

9. Common Mistakes

• Assuming a plain FF is testable. In isolation it's neither controllable nor observable — it needs the scan (mux-D) cell.
• Blocking the scan cell in RTL. Don't bury Q or over-constrain D so DFT can't insert a clean mux-D (4.x).
• Ignoring the scan-mux setup penalty. The mux adds delay on functional-D — a real timing cost (12.1/12.2).
• Debugging one cell's logic before its structure. A 1-cell flush failure = SE/clock/mux wiring — structure first (13.2).
• Forgetting both stuck-at values. Shift-0 detects stuck-at-1, shift-1 detects stuck-at-0 — you need both patterns.

10. Industry Best Practices

• Convert every state bit to a scan cell — control + observe is the foundation of testability (4.x).
• Keep RTL scan-friendly — don't block the D-mux insertion or bury Q (4.x).
• Budget the scan-mux setup penalty in timing (12.1/12.2) — it's small but real, per bit.
• Test each bit with shift-0/1 — detect both stuck-at values plus the SI/mux path via the flush.
• Debug the smallest cell structure-first — SE, clock, then mux (13.1/13.2).

11. Senior Engineer Thinking

• Beginner: "It's a flip-flop — of course we can test it."
• Senior: "A plain flip-flop buried in logic is unreachable — I can't force its D or read its Q. So I make it a scan cell: a mux on D for control and Q threaded out for observe. Two patterns — shift-0/1 — detect its stuck-at-0/1. I budget the scan-mux setup penalty, and if the cell won't flush, I debug it structure-first (SE, clock, mux). This one bit is the atom — a chain, a counter, an IP are just more of it, organized."

The senior sees one testable bit as control+observe made concrete — and treats it as the unit every larger structure is built from.

12. Silicon Impact

The single-bit case is the conceptual foundation of the entire capstone — and of DFT itself — because it isolates the irreducible requirement of manufacturing test: controllability and observability of a physical node. A plain D flip-flop, buried in logic, has neither in isolation — its D is unreachable behind a combinational cone and its Q is masked downstream — so its stuck-at faults are undetectable, and a defect there escapes (2.x/1.5). The scan (mux-D) cell supplies both: a mux on D (SE selects functional-D in normal mode, scan-in in shift) gives controllability (shift a known value straight in), and Q threaded to the scan-out gives observability (shift the captured value straight out) — turning an unreachable bit into a fully testable one. The test intent is the minimal, complete pair: shift-0/capture/observe (detects stuck-at-1) and shift-1/capture/observe (detects stuck-at-0), with a broken SI/mux/clock surfacing as a flush failure. The case also exposes, in miniature, the costs that scale up across the track: the scan mux adds a setup penalty on the functional-D path and a shift path with its own hold (12.1/12.2), so timing and testability trade off even at one bit. And it shows the debug method at its smallest: a 1-cell flush failure is a structure problem — scan-enable, clock, or mux polarity — debugged structure-first (13.1/13.2), never as logic. For the RTL/DV engineer, the lesson is to keep every bit scan-friendly; for the DFT engineer, it's that scan insertion (4.x) is this conversion, replicated; for the STA engineer, it's the per-bit setup penalty; and for the whole program, it's that testability is built one bit at a time, and an unreachable bit is a coverage hole. Most importantly, this bit is the atom: a scan chain (3.3) is many of these cells threaded SI-to-Q; a counter (14.2) is a handful with feedback; an FSM (14.3) adds branching logic; a clock-gated block (14.4) adds test control; a memory (14.5) needs its own BIST; and an IP (14.6) is millions of these cells with compression and ATPG. Every subsequent case study is this single testable bit — replicated, organized, and scaled — which is why the capstone starts here: understand how one bit gets control + observe, a 2-pattern test, and a structure-first debug, and you hold the key to everything that follows.

13. Engineering Checklist

• Converted the bit to a scan (mux-D) cell — control (mux on D) + observe (Q → SO).
• Kept the RTL scan-friendly — didn't block the D-mux or bury Q (4.x).
• Generated the 2-pattern test — shift-0/1 → detect both stuck-at values.
• Budgeted the scan-mux setup penalty and the shift hold (12.1/12.2).
• Debugged structure-first — a 1-cell flush failure = SE / clock / mux (13.1/13.2).

14. Try Yourself

1. Explain why a plain D flip-flop is not controllable or observable in isolation — and what test needs.
2. Write the scan (mux-D) cell in SV/Verilog/VHDL — the mux on D and Q → SO.
3. Give the two-pattern test for one bit and say which stuck-at each pattern detects.
4. Name the timing cost of the scan mux (setup penalty) and where it applies (12.1/12.2).
5. Debug a 1-cell flush failure structure-first — the three structural causes (SE / clock / mux).

The scan cell and test intent are tool-neutral; scan insertion is a DFT tool, patterns are ATPG. No paid tool required to reason about one testable bit.

15. Interview Perspective

• Weak: "You add scan to flip-flops to make them testable."
• Good: "A scan cell adds a mux on D so you can shift a value in and read it out, making the bit controllable and observable."
• Senior: "Manufacturing test needs control + observe of a physical node, and a plain flip-flop buried in logic has neither — you can't force its D or read its Q. The scan (mux-D) cell fixes both: a mux on D (SE selects functional-D vs scan-in) for control, and Q threaded to the scan-out for observe. I test one bit with two patterns — shift-0/capture/observe (stuck-at-1) and shift-1/capture/observe (stuck-at-0). It costs a scan-mux setup penalty on the functional path (12.1/12.2). And if the cell won't flush, I debug structure-first — scan-enable, clock, then mux polarity (13.2). This one bit is the atom — every chain, counter, FSM, and IP in the flow is this cell, replicated and scaled."

16. Interview / Review Questions

17. Key Takeaways

• Manufacturing test needs control + observe of a physical node, and a plain D flip-flop has neither in isolation — its D is behind deep logic, its Q is masked → its stuck-at faults are undetectable (a coverage hole/escape).
• The scan (mux-D) cell supplies both: a mux on D (SE=0 → functional-D, SE=1 → scan-in) for controllability, and Q threaded to the scan-out for observability — one bit becomes the atom of scan (3.2).
• Test intent for one bit: shift-0/capture/observe (detects stuck-at-1) and shift-1/capture/observe (detects stuck-at-0); a broken SI/mux/clock shows as a flush failure.
• Cost in miniature: the scan mux adds a setup penalty on the functional-D path and a shift path with its own hold (12.1/12.2) — testability vs timing, even at one bit.
• Debug structure-first: a 1-cell flush failure is SE / clock / mux polarity, not logic (13.1/13.2). This bit is the atom every later case — chain, counter, FSM, clock-gated block, memory, IP — replicates and scales. Next: 14.2 — counter: scan insertion & DRC.

18. Quick Revision

Case study — making one bit testable (Ch14 opener). Manufacturing test needs CONTROL + OBSERVE of a physical node ; a plain D-FF in isolation has neither (D behind deep logic, Q masked) → stuck-at undetectable. FIX = scan (mux-D) cell (3.2): a mux on D (SE=0 → functional-D, SE=1 → scan-in SI) for CONTROL + Q threaded to SO for OBSERVE → one bit = the ATOM of scan. Test intent: shift-0/capture/observe (detects stuck-at-1) + shift-1/capture/observe (detects stuck-at-0) ; a broken SI/mux/clock = a flush failure. Cost: scan-mux SETUP penalty on functional-D + shift HOLD (12.1/12.2). Debug a 1-cell flush fail STRUCTURE-FIRST: SE? clock? mux polarity? (13.1/13.2). Ships RTL (SV/Verilog/VHDL). This bit is replicated/scaled by every later case (chain→counter→FSM→IP). Next: 14.2 — counter: scan insertion & DRC.