Case Study — Counter: Scan Insertion & DRC

Chapter 14 · Section 14.2 · Industry Case Studies

Project thread — the 4-bit counter, scan-inserted and DRC-clean: the atom (14.1) stitched into a chain with feedback. 14.3 adds branching (an FSM); 14.6 scales to an IP.

1. Why Should I Learn This?

The counter case shows scan insertion + DRC on a small block with feedback — how a few flops become a loadable/observable chain, gated by the structural checks that must pass before ATPG.

• A counter = a few flops with feedback — functionally hard to control/observe (you'd clock many times).
• Scan insertion stitches the flops into a chain (SI→c0..c3→SO) → any state loadable/observable in a few shifts.
• Scan DRC is the structural gate before ATPG: same scan clock, no uncontrolled clocks/resets/loops, latches controlled.
• Test the increment by load + capture(+1) + observe; debug an uncontrolled async reset (fires in shift) by gating it in test.

2. Real Silicon Story — the counter whose chain reset itself

A block's 4-bit counter was scan-inserted, but its scan chain flushed intermittently — sometimes a clean pattern in/out, sometimes partially cleared. It looked like a flaky chain defect.

Scan DRC had already flagged it — an uncontrolled asynchronous reset. The counter's async reset was left live in test mode, and during shift (which takes many cycles), stray activity on the reset net occasionally fired the reset and cleared part of the chain — corrupting the flush non-deterministically (13.2's clock/reset chain-killer, in counter form). The team had skipped the DRC fix, treating the warning as noise. The fix was the standard DRC remedy: make the reset scan-controllable — gate it in test mode (rst_eff = arst_n | test_mode, 11.x) so the reset can't fire during shift. With the reset isolated in test, the flush became stable, and ATPG proceeded. Lesson: a counter is scan cells + feedback, and scan insertion makes it controllable/observable — but scan DRC is the structural gate: uncontrolled clocks and resets must be fixed before ATPG, or they surface as intermittent chain failures in silicon. DRC warnings are not noise — they are the structure-before-function check at design time.

3. Factory Perspective — the counter case through each lens

• What the DFT engineer sees: the scan stitch (SI→c0..c3→SO) and the DRC report — the structural gate that must be clean before ATPG (4.x).
• What the RTL/DV engineer sees: the async reset / clocking that must be made scan-controllable — a scan-friendly RTL fix (gate the reset in test).
• What the STA engineer sees: the shift hold across c0..c3 and lock-ups if domains differ (12.2), plus the per-flop scan-mux setup.
• What management cares about: that the small block is testable and DRC-clean before ATPG — a skipped DRC fix becomes an intermittent silicon chain failure (schedule risk).

4. Concept — feedback, stitching, DRC, and the increment test

The counter (a few flops + feedback):

• 4 state flops, next = current + 1 (wrapping) — a feedback loop.
• Functionally hard to test: to control a flop you'd clock many times; to observe you only see the count. The loop traps the state.

Scan insertion (the atom ×4, stitched, 3.3):

• Convert the 4 flops to scan cells (14.1) and stitch: SI → c0 → c1 → c2 → c3 → SO.
• Now any 4-bit state is loadable in 4 shifts (control) and readable in 4 shifts (observe). The feedback no longer traps you.

Scan DRC (the structural gate, 4.x) — fix before ATPG:

• (a) All state flops on the same scan clock / balanced (else shift hold / lock-ups, 12.2).
• (b) No uncontrolled clocks — a gated/derived clock must be bypassed/controlled in test.
• (c) No uncontrolled async set/reset — a reset that fires in shift corrupts the chain (13.2).
• (d) No combinational feedback loops left unbroken in scan.
• (e) Latches made transparent/controlled.
• DRC violations → fix before ATPG — structure before function at design time.

Test intent (test the increment via scan):

• Don't count to reach a state — shift it in.
• Load a state → capture one functional clock (counter does +1) → shift out → compare to state+1.
• Tests the increment (next-state/adder) logic per bit + the flops. A few states cover the carry chain; all-ones → wrap is the key corner.

Cost & the common fix:

• The scan-mux setup on each flop's D + a shift path (hold) across c0..c3.
• The async reset usually must be made scan-controllable (rst_eff = arst_n | test_mode, 11.x) — a common DRC fix.

5. Mental Model — a combination lock you can open from the back

A counter's feedback makes its state like a combination lock you can only reach by dialing through every number; scan is a back panel that lets you set the dials directly.

• Functionally, to reach state 1001 you'd dial (clock) from wherever you are, one click at a time, all the way around — slow, and you can only see the number the lock shows (the count), never the internal dials.
• Scan opens a back panel (the chain): you set each dial to any value instantly (shift a state in) and read each dial directly (shift it out) — the feedback loop that forced you to dial through is bypassed.
• Before you trust the back panel, you inspect it (DRC): are all dials on the same mechanism (one scan clock)? is there a spring that snaps them to zero if you're not careful (an uncontrolled reset) — which would wreck your setting mid-adjustment? You disable that spring while using the back panel (gate the reset in test).
• Then you test the mechanism the smart way: set the dials to a number, click once, and check it advanced by one (load, capture +1, observe) — the all-nines → rolls to zero case being the one that exercises the whole carry.

A combination lock you can only dial through (feedback) gets a back panel (scan) to set/read dials directly — but inspect the panel first (DRC: one mechanism, disable the reset-spring) before trusting it.

6. Working Example — the RTL: counter → scan-ready

Ship the counter RTL, then the scan-ready (reset-gated) version:

// SystemVerilog - 4-bit counter with async reset (REPRESENTATIVE)
module counter4 (
  input  logic clk, arst_n,        // async active-low reset
  input  logic test_mode,          // 1 in test/shift
  input  logic si, scan_enable,    // scan controls
  output logic [3:0] cnt, output logic so
);
  // DRC fix: make the async reset SCAN-CONTROLLABLE (can't fire during shift)
  logic rst_eff_n;
  assign rst_eff_n = arst_n | test_mode;   // in test, reset is held OFF -> shift is reset-safe
 
  // scan-stitched next-state: SE=1 -> take SI (shift chain) ; SE=0 -> take increment (functional +1)
  logic [3:0] nxt;
  assign nxt = scan_enable ? {cnt[2:0], si}   // shift: SI -> c0 -> c1 -> c2 -> c3
                           : cnt + 4'd1;       // functional increment (wraps at 1111)
  always_ff @(posedge clk or negedge rst_eff_n)
    if (!rst_eff_n) cnt <= 4'd0;
    else            cnt <= nxt;
  assign so = cnt[3];                          // scan-out = last cell
endmodule

// Verilog-2001 - scan-ready 4-bit counter (REPRESENTATIVE)
module counter4 (clk, arst_n, test_mode, si, scan_enable, cnt, so);
  input clk, arst_n, test_mode, si, scan_enable;
  output [3:0] cnt; output so;
  reg [3:0] cnt;
  wire rst_eff_n = arst_n | test_mode;                 // reset gated in test (DRC fix)
  wire [3:0] nxt = scan_enable ? {cnt[2:0], si} : cnt + 4'd1;
  always @(posedge clk or negedge rst_eff_n)
    if (!rst_eff_n) cnt <= 4'd0; else cnt <= nxt;
  assign so = cnt[3];
endmodule

-- VHDL - scan-ready 4-bit counter (REPRESENTATIVE)
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
entity counter4 is
  port ( clk, arst_n, test_mode, si, scan_enable : in std_logic;
         cnt : out std_logic_vector(3 downto 0); so : out std_logic );
end entity;
architecture rtl of counter4 is
  signal c : unsigned(3 downto 0);
  signal rst_eff_n : std_logic;
begin
  rst_eff_n <= arst_n or test_mode;                    -- reset gated in test (DRC fix)
  process (clk, rst_eff_n) begin
    if rst_eff_n = '0' then c <= (others => '0');
    elsif rising_edge(clk) then
      if scan_enable = '1' then c <= c(2 downto 0) & si;  -- shift
      else                      c <= c + 1;               -- increment
      end if;
    end if;
  end process;
  cnt <= std_logic_vector(c); so <= c(3);
end architecture;

# Counter scan structure + test intent - REPRESENTATIVE, tool-neutral:
  SCAN CHAIN: SI -> c0 -> c1 -> c2 -> c3 -> SO   (any 4-bit state loadable/observable in 4 shifts)
  DRC (before ATPG): same scan clock? uncontrolled clocks? uncontrolled async reset? unbroken loops? latches? -> FIX first
  TEST INTENT (test the increment via scan):
    load 0011 -> capture ONE functional clock (+1) -> shift out -> expect 0100     (increment logic + flops)
    load 1111 -> capture ONE functional clock (+1) -> shift out -> expect 0000     (WRAP - exercises the full carry chain)
  -> load a handful of states to cover the carry chain ; the all-ones->wrap corner is the key one.

The waveform shows loading a count and testing the increment:

7. Industry Flow — RTL, insert, DRC-gate, then ATPG

The counter flow: scan-insert the flops, pass the DRC structural gate (fix clocks/resets/loops/latches), then ATPG:

8. Debugging Session — the counter chain that intermittently clears

9. Common Mistakes

• Treating DRC warnings as noise. DRC is the structural gate — an uncontrolled async reset flagged and skipped becomes an intermittent chain failure (13.2).
• Leaving async resets live in test. Gate them in test mode (rst_eff_n = arst_n | test_mode, 11.x) so shift is reset-safe.
• Ignoring uncontrolled/derived clocks. A gated clock in the counter must be bypassed/controlled in test (4.x).
• Trying to count to a test state. With scan you shift the state in — don't clock your way there.
• Skipping the wrap corner. All-ones → wrap exercises the full carry chain — a key increment test.

10. Industry Best Practices

• Scan-insert every state flop and stitch a clean chain (SI→c0..c3→SO, 3.3).
• Pass scan DRC before ATPG — same scan clock, no uncontrolled clocks/resets/loops, latches controlled (4.x).
• Make async resets scan-controllable — gate them in test mode (11.x).
• Test the increment via scan — load a state, capture one functional clock (+1), observe; cover the carry chain (wrap).
• Fix DRC violations at design time — structure before function; cheapest and safest there.

11. Senior Engineer Thinking

• Beginner: "The counter chain fails sometimes — must be a flaky chain defect."
• Senior: "Intermittent points at an async cause, not a deterministic defect — and DRC already flagged an uncontrolled async reset. During the many cycles of shift, that reset can fire and clear the chain. I gate the reset in test (rst_eff_n = arst_n | test_mode), re-run DRC to clear the violation, and re-flush — stable. DRC is the structural gate; its warnings aren't noise. A counter is just scan cells + feedback — make it loadable/observable and DRC-clean before ATPG."

The senior reads intermittency as an async structural cause, respects the DRC gate, and gates resets in test before ATPG.

12. Silicon Impact

The counter case is where DFT stops being about one bit and becomes about a small block with feedback — and where scan DRC earns its place as the structural gate of the whole flow. A 4-bit counter is four state flops in a feedback loop (next = current + 1), and that feedback is precisely what makes it untestable functionally: to control an internal flop you'd clock through many states, and to observe it you only ever see the count — the loop traps the state. Scan insertion dissolves the trap by converting the four flops into scan cells (the 14.1 atom, ×4) and stitching them into a chain (SI→c0→c1→c2→c3→SO, 3.3), so any state is loadable in a few shifts (control) and readable in a few shifts (observe) — the feedback no longer matters for test. But a chain is only usable if it's structurally valid, which is the job of scan DRC (4.x): same scan clock / balanced (else shift hold/lock-ups, 12.2), no uncontrolled clocks (gated/derived clocks bypassed in test), no uncontrolled async set/reset (a reset that fires in shift corrupts the chain, 13.2), no unbroken combinational loops, and controlled latches. Crucially, DRC violations are fixed before ATPG — the structure-before-function principle applied at design time — and the case's central lesson is that DRC warnings are not noise: a skipped uncontrolled-async-reset fix surfaces as an intermittent silicon chain failure that masquerades as a flaky defect, when it's really an async, event-driven corruption during shift, fixed by the standard remedy of gating the reset in test (rst_eff_n = arst_n | test_mode, 11.x). With a DRC-clean chain, the test intent becomes elegant: you don't count to a state, you shift it in, then capture one functional clock so the counter increments, and observe the result — testing the increment/next-state logic per bit and the flops, with all-ones → wrap exercising the full carry chain. For the DFT engineer, this case is scan insertion + the DRC gate; for the RTL/DV engineer, it's scan-friendly resets/clocking; for the STA engineer, it's shift hold and lock-ups across a multi-cell chain; and for the program, it's proof that testability and structural correctness are designed in, then checked by DRC, before ATPG ever runs. The counter is the atom, stitched with feedback — the next case (14.3) adds branching (an FSM), and the arc continues up to an IP of millions (14.6). The throughline: scan makes state loadable/observable; DRC makes the scan structure valid; and skipping the DRC gate is how a structural problem becomes a silicon one.

13. Engineering Checklist

• Scan-inserted every state flop and stitched a clean chain (SI→c0..c3→SO, 3.3).
• Passed scan DRC before ATPG — same scan clock, no uncontrolled clocks/resets/loops, latches controlled (4.x).
• Made async resets scan-controllable — gated in test mode (rst_eff_n = arst_n | test_mode, 11.x).
• Tested the increment via scan — load, capture one functional clock (+1), observe; covered the wrap corner.
• Fixed DRC violations at design time — treated warnings as the structural gate, not noise.

14. Try Yourself

1. Explain why a counter's feedback makes its flops hard to control/observe functionally — and how scan fixes it.
2. Write the scan-ready counter (SV/Verilog/VHDL) with the async reset gated in test and the flops scan-stitched.
3. List the scan DRC checks (clocks / resets / loops / latches) and why each must pass before ATPG.
4. Give the increment test via scan: load a state → capture (+1) → observe — and the wrap corner.
5. Debug an intermittent flush — why an uncontrolled async reset causes it and how gating it in test fixes it.

The scan insertion, DRC, and test intent are tool-neutral; insertion/DRC are DFT tools, patterns are ATPG. No paid tool required to reason about the counter case.

15. Interview Perspective

• Weak: "You add scan to the counter's flip-flops so you can test them."
• Good: "You stitch the counter's flops into a scan chain to load and observe any state, and run DRC to check the structure."
• Senior: "A counter is scan cells + feedback. Functionally the feedback traps the state — you'd clock through many states to control a flop and only see the count to observe. So I scan-insert the flops and stitch a chain (SI→c0..c3→SO): now any state is loadable/observable in a few shifts. But before ATPG, the chain must pass scan DRC — same scan clock, no uncontrolled clocks/resets/loops, latches controlled — and the classic fix is making the async reset scan-controllable (gate it in test), because an uncontrolled async reset fires in shift and clears the chain, giving an intermittent flush failure that looks like a flaky defect. DRC is the structural gate; its warnings aren't noise. Then I test the increment by load + capture(+1) + observe, covering the wrap/carry corner."

16. Interview / Review Questions

17. Key Takeaways

• A 4-bit counter = a few state flops with feedback (next = current+1) — functionally hard to control (clock many times) and hard to observe (only the count is visible); the feedback traps the state.
• Scan insertion converts the flops to scan cells (14.1 ×4) and stitches a chain (SI→c0→c1→c2→c3→SO, 3.3) → any state loadable/observable in a few shifts — the feedback no longer traps you.
• Scan DRC is the structural gate before ATPG (4.x): same scan clock/balanced, no uncontrolled clocks, no uncontrolled async set/reset, no unbroken loops, controlled latches — fix violations at design time (structure before function).
• Test the increment via scan: load a state → capture one functional clock (+1) → shift out → compare to state+1; cover the carry chain, with all-ones → wrap the key corner.
• Debug an intermittent flush as an async structural cause: an uncontrolled async reset fires in shift and clears the chain → gate it in test (rst_eff_n = arst_n | test_mode, 11.x); DRC warnings are not noise. Next: 14.3 — FSM: ATPG & coverage closure.

18. Quick Revision

Case study — counter: scan insertion & DRC. A 4-bit counter = few flops + FEEDBACK → functionally hard to control (clock many times) / observe (only the count). SCAN INSERTION: flops → scan cells (14.1 ×4), STITCH a chain SI→c0→c1→c2→c3→SO (3.3) → any state loadable/observable in a few shifts. SCAN DRC = the STRUCTURAL GATE before ATPG (4.x): same scan clock/balanced, no uncontrolled clocks, no uncontrolled async set/reset, no unbroken loops, latches controlled → FIX at design time (structure before function). TEST INTENT: load a state → capture ONE functional clock (+1) → shift out → compare to state+1 ; cover the carry chain (all-ones→WRAP is the key corner). DEBUG: intermittent flush = an uncontrolled ASYNC RESET firing in shift → gate it in test (rst_eff_n = arst_n | test_mode, 11.x) → stable. DRC warnings are NOT noise. Ships RTL (SV/Verilog/VHDL). Next: 14.3 — FSM: ATPG & coverage closure.