Case Study — Clock-Gated Block: Test Control

Chapter 14 · Section 14.4 · Industry Case Studies

Project thread — the clock-gated block, test-controlled: the FSM/counter logic (14.2/14.3) now power-gated, made scan-safe via a glitch-free test-enabled ICG. 14.5 adds a memory; 14.6 scales to an IP.

1. Why Should I Learn This?

The clock-gated case shows how a power optimization becomes a testability hazard — and how test control (a glitch-free, test-enabled ICG) makes it scan-safe without losing the power benefit.

• Clock gating saves power but kills scan — a clock gated off in test means those flops never clock (dead chain, 13.2).
• Fix = force the ICG enable ON in test via TE: gated_en = func_enable | test_mode → clock always passes in test.
• Glitch-free is mandatory (11.2): a latch-based ICG gating on the inactive edge — a naive AND gate glitches.
• Preserve functional gating, make the enable logic testable, and cooperate with the OCC at-speed (12.4).

2. Real Silicon Story — the power-saving block that no test could clock

A block used clock gating to save power — an ICG stopped its clock when idle. In test, its flops were dead in the scan chain: the flush showed everything downstream of the block frozen, and the block's logic was entirely untestable (a big coverage hole).

The cause was the gated clock left uncontrolled in test. The ICG's enable was purely functional, so during shift (when the block was "idle") the ICG held the clock off — the block's flops never clocked (13.2's clock chain-killer). Scan DRC had flagged the uncontrolled gated clock, but it was unresolved. The fix was a test-controllable, glitch-free ICG: wire the ICG's test-enable so gated_en = func_enable | test_mode — in test the clock always passes, so the block's flops shift and capture; in functional mode the gating still saves power. Because the ICG was latch-based (gating on the inactive edge), forcing TE didn't glitch the clock. The block's flops then shifted, the flush passed, and ATPG covered the previously-dead logic. Lesson: clock gating saves power but kills scan if the clock is off in test — the fix is to force the ICG enable ON in test (via TE), glitch-free, without breaking functional gating. A gated clock is an uncontrolled clock to DRC — make it test-controllable.

3. Factory Perspective — the clock-gated case through each lens

• What the DFT engineer sees: the test-enabled ICG — TE forces the clock on in test — and the DRC on the gated clock (4.x/11.x).
• What the RTL/DV engineer sees: instantiate the ICG with its TE tied to the test signal (not a hand-rolled AND gate) so it's glitch-free and testable.
• What the STA engineer sees: the gated-clock timing, glitch-free behavior, and the OCC cooperation for at-speed capture (12.4).
• What management cares about: that the block is testable and still low-power — test control must not sacrifice the power benefit, and an untested gated block is a coverage hole/escape.

4. Concept — gated clocks, test-enable, glitch-free, and both modes

Clock gating (power) vs scan (deadly):

• An ICG stops the clock when idle (enable = 0 → clock held off) → idle flops don't toggle → power saved.
• In test: if the clock is gated OFF during shift/capture, those flops never clock → dead chain (13.2) + untestable logic.

The fix — test control (11.x):

• Force the ICG enable ON in test via the test-enable (TE) pin: gated_en = func_enable | test_mode (or | scan_enable).
• In test the clock always passes → the block's flops clock → chain works + logic testable. Standard-cell ICGs have a TE pin for this.

Glitch-free is mandatory (11.2):

• The ICG must gate on the inactive clock edge (latch-based enable) so forcing TE doesn't create a clock glitch (runt pulse) that double-clocks/corrupts.
• A naive AND-gate clock gate glitches; a proper ICG (latch + AND) is glitch-free.

Preserve functional gating + test the enable:

• Test control must force the clock on in test without breaking the power-saving gating in functional mode — you want both.
• The enable-generating logic must itself be testable (scan the enable flops).

Derived/gated clocks & DRC (4.x):

• Scan DRC flags an uncontrolled gated clock — the fix is a test-controllable ICG (bypass the gating in test, or keep the gated clock but guarantee it's ON).

At-speed nuance (12.4/11.2):

• For at-speed the OCC also gates clocks → the ICG's TE and the OCC must cooperate (the block's capture clock comes from the OCC through/around the ICG) — glitch-free.

5. Mental Model — a motion-sensor light with a manual override

A test-controllable ICG is a motion-sensor light (saves power when nobody's there) with a manual override switch you flip during maintenance (test) so the light stays on while you work.

• The motion sensor is the functional enable: when the room is idle, it turns the light off (gates the clock) to save power — exactly what you want in normal operation.
• But during maintenance (test), you can't have the light flicking off every time you hold still — you'd be working in the dark (flops not clocking, dead chain). So you flip the manual override (test-enable): the light stays on regardless of the sensor. on = motion OR override.
• Crucially, the override must turn on cleanly — no flicker/strobe as it engages (a clock glitch). A well-designed fixture switches at a safe moment (the inactive edge, latch-based) so the light comes on steady; a cheap switch might strobe (a naive AND glitches).
• And the override doesn't disable the sensor forever — flip it off after maintenance and motion-sensing resumes (functional gating preserved). You get both: power-saving in normal use, steady light for maintenance.

A motion-sensor light (power gating) with a clean manual override for maintenance (test-enable) — on = motion OR override, engaged without a strobe (glitch-free), sensor still works afterward (functional gating preserved).

6. Working Example — the RTL: naive gate (bad) → test-controllable ICG (good)

Ship the naive gated clock (bad) and the proper test-controllable, glitch-free ICG (good):

// SystemVerilog - clock gating: BAD (naive) vs GOOD (test-controllable, glitch-free) (REPRESENTATIVE)
 
// (BAD) naive AND-gate clock gate: glitches, and dead in scan (no test control)
// assign gclk_bad = clk & func_enable;   // <-- glitch on enable change; clock OFF in shift -> dead chain
 
// (GOOD) latch-based ICG with a TEST-ENABLE: glitch-free + forced on in test
module icg_te (
  input  logic clk,
  input  logic func_enable,   // functional gating (power)
  input  logic test_mode,     // TE: force clock on in test (or use scan_enable)
  output logic gclk
);
  logic en_l;
  // enable OR'd with test-enable, then LATCHED on the LOW phase (inactive edge) -> glitch-free
  always_latch if (!clk) en_l <= (func_enable | test_mode);
  assign gclk = clk & en_l;   // gated clock: always on in test; gated by func_enable in function
endmodule

// Verilog-2001 - test-controllable, glitch-free ICG (REPRESENTATIVE)
module icg_te (clk, func_enable, test_mode, gclk);
  input clk, func_enable, test_mode; output gclk;
  reg en_l;
  always @(*) if (!clk) en_l = (func_enable | test_mode);  // latch on low phase -> glitch-free
  assign gclk = clk & en_l;                                // on in test; gated in function
endmodule

-- VHDL - test-controllable, glitch-free ICG (REPRESENTATIVE)
library ieee; use ieee.std_logic_1164.all;
entity icg_te is
  port ( clk, func_enable, test_mode : in std_logic; gclk : out std_logic );
end entity;
architecture rtl of icg_te is
  signal en_l : std_logic;
begin
  process (clk, func_enable, test_mode) begin
    if clk = '0' then en_l <= (func_enable or test_mode);  -- latch on low phase -> glitch-free
    end if;
  end process;
  gclk <= clk and en_l;                                    -- on in test; gated in function
end architecture;

# Clock-gated block test control - intent - REPRESENTATIVE, tool-neutral:
  (a) TEST forces clock ON: test_mode=1 -> gated_clock always passes -> FLUSH the block's flops -> they MUST shift
  (b) FUNCTIONAL gating preserved: test_mode=0 -> clock gated by func_enable (idle=off) -> power saved (unchanged)
  (c) ENABLE LOGIC testable: the flops that generate func_enable are in the scan chain (scan them too)
  (d) GLITCH-FREE: enable latched on the INACTIVE (low) phase -> forcing TE creates NO runt pulse
  (e) AT-SPEED: the OCC and ICG cooperate -> the capture clock reaches the block glitch-free (12.4/11.2)
  DRC (4.x): an uncontrolled gated clock is FLAGGED -> the test-controllable ICG resolves it.

The waveform shows the clock gated in function but forced on in test, glitch-free:

7. Industry Flow — replace the naive gate, control it, DRC-clean it

The flow: replace a naive/uncontrolled gated clock with a test-controllable glitch-free ICG, pass DRC, and verify both modes:

8. Debugging Session — the clock-gated block dead in the chain

9. Common Mistakes

• Hand-rolling an AND-gate clock gate. It glitches and is dead in scan — instantiate a test-enabled, glitch-free ICG (11.2).
• Leaving the ICG test-enable unwired / wrong polarity. The clock stays gated off in test → dead block (13.2).
• Breaking functional gating for test. Force the clock on in test only — preserve the power-saving gating (| test_mode).
• Ignoring glitch-free. Force TE on the inactive edge (latch-based) — else a runt pulse corrupts capture (11.2).
• Forgetting the enable logic and the OCC. Scan the enable flops, and make the ICG cooperate with the OCC at-speed (12.4).

10. Industry Best Practices

• Use standard-cell test-enabled ICGs — latch-based, glitch-free, with a dedicated TE pin (11.2).
• Force the ICG enable on in test — gated_en = func_enable | test_mode — clock always passes in test.
• Preserve functional gating — test control must not cost the power benefit.
• Make the enable logic testable (scan the enable flops) and resolve the DRC on the gated clock (4.x).
• Cooperate with the OCC at-speed — the block's capture clock stays glitch-free (12.4).

11. Senior Engineer Thinking

• Beginner: "The clock-gated block's flops won't shift — must be a defect."
• Senior: "A clock-gated block is dead in the chain if the clock is gated off in test — and that's a test-control wiring issue, not a defect. The ICG's test-enable isn't forcing the clock on: I set gated_en = func_enable | test_mode, verify polarity, and use a glitch-free latch-based ICG so forcing TE doesn't glitch. Functional gating still saves power when test_mode=0. I scan the enable flops and make the ICG cooperate with the OCC at-speed. DRC flagged the uncontrolled gated clock — this is that, in silicon."

The senior treats a dead gated block as a test-control wiring fix (TE, glitch-free), preserving functional gating.

12. Silicon Impact

The clock-gated case is where two first-class design goals collide — power and testability — and it shows the discipline that lets you keep both. Clock gating is ubiquitous for dynamic-power reduction: an ICG stops the clock to idle logic (enable = 0 → clock held off), so idle flops don't toggle. But a stopped clock is fatal to scan: if the clock is gated OFF during shift or capture, those flops never clock, so the block is dead in the chain (13.2's clock chain-killer) and its logic is untestable — a coverage hole that becomes an escape. The resolution is test control (11.x): force the ICG's enable ON in test via its test-enable (TE) pin, making the effective enable gated_en = func_enable | test_mode, so in test the clock always passes (the block clocks, shifts, and is testable) while functional gating still saves power in normal operation — you get both. Two correctness constraints define the case. First, glitch-free is mandatory (11.2): the ICG must be latch-based, gating on the inactive clock edge, so engaging TE produces no runt pulse that would double-clock or corrupt the chain — a naive AND-gate clock gate glitches and must never be used. Second, functional gating must survive: test control forces the clock on only in test, preserving the power benefit. Around these, the enable-generating logic must itself be scannable, scan DRC (4.x) flags an uncontrolled gated clock precisely so this is fixed before silicon, and at-speed the OCC and ICG must cooperate to deliver a clean capture clock (12.4). The debug signature is unmistakable and structural: a block dead in the chain — flops won't shift, downstream frozen — is an unwired or wrong-polarity ICG test-enable (structure before function, 13.2), never a logic defect. For the DFT engineer, this case is the test-enabled, glitch-free ICG; for the RTL/DV engineer, it's instantiate the standard-cell ICG with TE, never a hand-rolled AND; for the STA engineer, it's glitch-free timing and OCC cooperation; and for the program, it's the proof that a power-optimized design stays fully testable only when every gated clock is made test-controllable. In the project thread, the counter/FSM logic (14.2/14.3) is now power-gated and still testable; the next case (14.5) adds a memory — which needs its own test (MBIST) rather than scan — and the arc culminates in an IP (14.6) with many gated clocks. The throughline: clock gating saves power but kills scan unless you force the ICG enable on in test, glitch-free, without sacrificing functional gating — and a dead gated block is a test-control wiring fix, caught by DRC, not a defect.

13. Engineering Checklist

• Used a test-enabled, glitch-free ICG (latch-based, TE pin) — not a hand-rolled AND gate (11.2).
• Forced the ICG enable on in test — gated_en = func_enable | test_mode, verified polarity.
• Preserved functional gating — power benefit intact when test_mode = 0.
• Made the enable logic testable (scanned the enable flops) and resolved the gated-clock DRC (4.x).
• Cooperated with the OCC at-speed — the block's capture clock is glitch-free (12.4).

14. Try Yourself

1. Explain why clock gating saves power but kills scan if the clock is gated off in test.
2. Write a test-controllable, glitch-free ICG (SV/Verilog/VHDL) with gated_en = func_enable | test_mode.
3. Explain why the ICG must be glitch-free (latch-based, inactive edge) and how a naive AND gate fails.
4. State the three test intents: TE forces clock on, functional gating preserved, enable logic testable.
5. Debug a dead gated block — why an unwired/wrong-polarity TE causes it and how to fix it.

The clock-control reasoning is tool-neutral; ICGs are standard cells, DRC/ATPG are DFT tools. No paid tool required to reason about the clock-gated case.

15. Interview Perspective

• Weak: "You turn the clock gating off in test so the block can be tested."
• Good: "You wire the ICG's test-enable so the clock is forced on in test, and use a glitch-free ICG so it doesn't glitch."
• Senior: "Clock gating saves power by stopping the clock to idle logic — but a stopped clock makes those flops unscannable, so a gated block is dead in the chain in test. The fix is test control: wire the ICG's test-enable so gated_en = func_enable | test_mode — in test the clock always passes, in function the gating still saves power. It must be glitch-free — a latch-based ICG gating on the inactive edge, never a naive AND gate (which glitches and double-clocks). I also scan the enable logic and make the ICG cooperate with the OCC at-speed (12.4). Scan DRC flags the uncontrolled gated clock — and a block dead in the chain is an unwired/wrong-polarity test-enable, a structural fix, not a defect."

16. Interview / Review Questions

17. Key Takeaways

• Clock gating saves power but kills scan — an ICG stops the clock when idle, so if the clock is gated OFF in test, those flops never clock → the block is dead in the chain (13.2) and its logic is untestable.
• Fix = force the ICG enable ON in test via the test-enable (TE): gated_en = func_enable | test_mode → the clock always passes in test (chain works + logic testable); standard-cell ICGs have a TE pin for this.
• Glitch-free is mandatory (11.2): a latch-based ICG gating on the inactive edge so forcing TE creates no runt pulse that double-clocks — a naive AND-gate clock gate glitches and must not be used.
• Preserve functional gating (power benefit intact when test_mode = 0), make the enable logic testable (scan the enable flops), and resolve the gated-clock DRC (4.x).
• At-speed: the OCC and ICG must cooperate to deliver a glitch-free capture clock (12.4). A block dead in the chain is a test-control wiring fix (unwired/wrong-polarity TE), not a defect. Next: 14.5 — memory block: MBIST signoff.

18. Quick Revision

Case study — clock-gated block: test control. Clock gating (ICG stops the clock when idle) saves POWER but KILLS scan: clock gated OFF in test → flops never clock → block DEAD in the chain (13.2) + untestable. FIX (11.x): force the ICG enable ON in test via TEST-ENABLE → gated_en = func_enable | test_mode → clock ALWAYS passes in test (chain works + testable). GLITCH-FREE mandatory (11.2): latch-based ICG, gate on the INACTIVE edge → forcing TE = no runt pulse ; a naive AND gate glitches. PRESERVE functional gating (power intact when test_mode=0) ; scan the enable logic ; resolve the gated-clock DRC (4.x) ; OCC cooperates at-speed (12.4). DEBUG: block dead in chain = ICG test-enable UNWIRED / wrong polarity → connect TE=test_mode (glitch-free) → flush passes. A dead gated block = a test-control wiring fix, NOT a defect. Ships RTL (SV/Verilog/VHDL). Next: 14.5 — memory block: MBIST signoff.