Case Study — Memory Block: MBIST Signoff

Chapter 14 · Section 14.5 · Industry Case Studies

Project thread — the memory block, MBIST-signed-off: the logic (14.1–14.4) is scan+ATPG; the array needs its own on-chip March test + repair. 14.6 integrates memory + logic in an IP.

1. Why Should I Learn This?

The memory case shows the other half of DFT: scan + ATPG can't test an array, so memories get their own on-chip, at-speed March test (MBIST) — with self-repair (BISR) to recover yield.

• Memories aren't scannable — dense arrays with own fault models (coupling, decoder, retention) → a dedicated test.
• MBIST = an on-chip controller that writes/reads/compares with a March algorithm at speed → GO/NOGO + bitmap.
• BISR swaps in spare rows/columns to repair inevitable bad bits → yield recovery (repair signature in efuse).
• Signed off separately from logic scan/ATPG, then integrated (memory = black box + collar to logic ATPG).

2. Real Silicon Story — the memory that failed a column, then passed

A chip's large SRAM failed MBIST on many dies — NOGO. Treated as logic, it was inexplicable; treated as random defects, the scrap rate was alarming. Someone proposed a respin of the memory.

The bitmap told the real story. MBIST didn't just report NOGO — it produced a failure bitmap, and the failing bits clustered on a single column across many rows. That pattern is not random — it's a structural array defect (a column line or sense-amp fault), exactly the kind large memories expect a few of. And the memory shipped with spare columns: BISR (built-in self-repair) identified the failing column, swapped in a spare, and stored the repair signature in efuse. On re-run, the memory reported GO — the die was good and shipped, no respin, no scrap. Lesson: a memory is not testable by scan — it needs its own test (MBIST, an on-chip, at-speed March), and its bitmap enables diagnosis and repair. A clustered bitmap (a column/row) is a repairable structural defect; BISR recovers the yield that random-defect thinking would have scrapped. Memory is signed off on its own terms — GO/NOGO + bitmap + repair — then integrated with the logic.

3. Factory Perspective — the memory case through each lens

• What the DFT/memory engineer sees: the MBIST controller (March, GO/NOGO, bitmap) and BISR — a dedicated test flow separate from logic scan (8.x).
• What the yield engineer sees: the bitmap (clustered = structural = repairable) and the repair rate — BISR recovers yield on arrays where bad bits are inevitable.
• What the logic-DFT engineer sees: the memory as a black box with a scan collar — logic faults around it still covered by ATPG; MBIST runs in its own mode.
• What management cares about: that memories are tested and repaired — a separate signoff that recovers yield (BISR) and prevents escapes on the densest, most defect-prone part of the die.

4. Concept — why not scan, MBIST, BISR, and integration

Why memories aren't scanned:

• An SRAM is a dense array of bit cells (not flops) — you can't scan-stitch bit cells.
• It has memory-specific fault models: stuck-at, transition, coupling (bit-to-bit), address-decoder, retention — which scan/stuck-at ATPG doesn't target.
• → Memories get a dedicated test: MBIST.

MBIST (on-chip, at-speed March):

• An on-chip controller writes and reads the array with a March algorithm, comparing reads to expected.
• Built-in (the array is too big for external per-bit patterns) and at-speed (catches timing/coupling faults).
• March C- (and variants): ascending/descending w0/r0/w1/r1 elements → detects the memory fault classes.

The controller (8.x):

• A small FSM generates addresses, march data, read-compare → a GO/NOGO plus optionally a failure bitmap (which address/bit).
• Controlled via test mode or a BIST interface (sometimes through JTAG, 10.x).

Redundancy & repair (BISR, 8.x):

• Big memories ship with spare rows/columns. BISR finds failing cells and swaps in spares, storing the repair signature (efuse).
• Recovers yield on an array where a few bad bits are inevitable. Signoff includes repair rate / remaining defects.

Signoff & integration:

• MBIST coverage = the fault models the March algorithm detects (report which); run at-speed; report GO/NOGO + bitmap + repair.
• Memory signed off separately from logic scan/ATPG, then integrated: to logic ATPG the memory is a black box (I/O wrapped/observed via a collar so logic around it is covered); MBIST runs in its own mode. Complementary: logic = scan+ATPG, memory = MBIST.

5. Mental Model — testing a parking garage vs testing offices

Logic scan and memory MBIST are like two different inspections for two different structures — you can't inspect a parking garage the way you inspect offices.

• The offices (the logic) have individually addressable rooms you can walk into and check (scan cells you load/observe). The parking garage (the memory array) is thousands of identical bays in a dense grid — you can't run a hallway to each bay (you can't scan-stitch bit cells), and it has its own failure modes (a flooded row, a jammed column gate, a space that won't hold a car overnight — coupling, decoder, retention).
• So the garage gets a dedicated inspector who drives the whole grid systematically — park in every bay, come back and check the car's still there, in a set pattern (the March algorithm) — and reports pass/fail plus a map of which bays failed (the bitmap). This inspector is built into the garage (MBIST) because checking every bay from outside would take forever.
• When the map shows a whole column of bays failing (clustered), that's not random potholes — it's a structural fault (a collapsed ramp to that column). And the garage was built with spare bays: the repair crew (BISR) reassigns the bad column's traffic to a spare column and records the reroute (efuse) — the garage opens for business anyway (yield recovered).
• You report the two inspections separately (offices vs garage) and then certify the whole building — the garage a sealed unit to the office inspector (a black box + collar), each checked the right way.

Offices you walk (logic scan) vs a parking garage you drive systematically with a built-in inspector (memory MBIST) — a failing column is a structural fault the spare bays (BISR) repair; certify each the right way, then the whole building.

6. Working Example — the MBIST controller & March C-

Ship an MBIST controller sketch and the March C- element sequence:

// SystemVerilog - MBIST controller sketch + March C- (REPRESENTATIVE, simplified)
// March C-  (arrows = address direction ; w=write, r=read ; 0/1 = data):
//   { UP w0 ; UP (r0,w1) ; UP (r1,w0) ; DN (r0,w1) ; DN (r1,w0) ; DN r0 }
module mbist_ctrl #(parameter AW=8) (
  input  logic clk, rst_n, start,
  output logic [AW-1:0] addr,
  output logic          we, wdata,       // write-enable, write-data
  input  logic          rdata,           // read-data from array
  output logic          go, nogo, done,
  output logic [AW-1:0] fail_addr        // (part of the failure bitmap)
);
  // (a small FSM sequences the March elements, generates addr/we/wdata,
  //  and on each read compares rdata to the EXPECTED value; a mismatch -> NOGO + record fail_addr)
  // ... element sequencer (UP/DN, w0/r0/w1/r1) ...
  // on read: if (rdata !== expected) begin nogo <= 1'b1; fail_addr <= addr; end   // bitmap entry
  // go <= ~nogo when done;   done marks the run complete
endmodule

# March C- element sequence + MBIST signoff - REPRESENTATIVE, tool-neutral:
  MARCH C-  (workhorse; detects the memory fault classes):
    M0: (UP)  w0                      # initialize all cells to 0
    M1: (UP)  r0, w1                  # read expect 0, then write 1     -> detects transition/coupling up-address
    M2: (UP)  r1, w0                  # read expect 1, then write 0
    M3: (DN)  r0, w1                  # descending
    M4: (DN)  r1, w0
    M5: (DN)  r0                      # final read expect 0
  detects: stuck-at, transition, coupling (bit-to-bit), address-decoder faults ; run AT-SPEED for timing/retention
  OUTPUT: GO/NOGO + failure BITMAP (address/bit) -> BISR repair if clustered ; report coverage of the fault models
# SIGNOFF: report the March algorithm + which fault models it covers + GO/NOGO + bitmap + repair rate. Run at-speed.
# INTEGRATION: to logic ATPG the memory is a BLACK BOX + scan COLLAR (logic around it covered) ; MBIST in its own mode.

March C- walks the array with a fixed read/write sequence to detect the memory fault classes:

7. Industry Flow — two complementary signoffs, integrated

The memory is signed off by MBIST separately from the logic's scan+ATPG, then the two are integrated:

8. Debugging Session — MBIST NOGO with a column-clustered bitmap

9. Common Mistakes

• Trying to scan a memory array. Bit cells aren't scannable — memories need MBIST (their own test, 8.x).
• Reading a clustered bitmap as random defects. A column/row cluster is a structural, repairable defect — BISR it, don't scrap.
• Skipping at-speed. MBIST must run at-speed to catch timing/coupling/retention faults, not just static ones.
• Not reporting which fault models are covered. MBIST coverage = the fault classes the March detects — report them.
• Forgetting the collar. To logic ATPG the memory is a black box — wrap it so logic faults around it are still covered.

10. Industry Best Practices

• Test memories with MBIST — an on-chip, at-speed March (C- or variant) — not scan/ATPG.
• Produce a failure bitmap — enables diagnosis (structural vs random) and repair.
• Repair with BISR — spare rows/columns; store the repair signature (efuse) for the field.
• Report the memory fault models covered + GO/NOGO + bitmap + repair rate; run at-speed.
• Integrate as a black box + collar — sign off memory separately, keep logic around it covered by ATPG.

11. Senior Engineer Thinking

• Beginner: "The memory fails MBIST on lots of dies — random defects, scrap them (or respin)."
• Senior: "NOGO alone isn't the story — read the bitmap. Failing bits on one column across many rows = a structural column defect (bit-line/sense-amp), not random. That's repairable: BISR swaps in a spare column and efuses the signature — re-run → GO, die shipped. I scrap only if spares are exhausted or it's a decoder fault. Memories need their own test — MBIST at-speed — and the bitmap is my diagnosis. Random-defect thinking scraps repairable yield."

The senior reads the MBIST bitmap as diagnosis, repairs structural defects with BISR, and scraps only the un-repairable.

12. Silicon Impact

The memory case is where the capstone shows that DFT is not one method but two complementary ones — scan + ATPG for logic, MBIST for memory — because a dense array is fundamentally not a bag of flops. An SRAM's bit cells can't be scan-stitched, and the array fails in ways scan/stuck-at ATPG doesn't model: coupling (a write to one cell disturbing a neighbor), address-decoder faults, retention (a cell that won't hold its value), on top of stuck-at/transition. So memories get a dedicated, built-in, at-speed test: MBIST, an on-chip controller that writes and reads the array with a March algorithm (C- the workhorse) and compares to expected — built-in because the array is far too large for external per-bit patterns, and at-speed because timing/coupling/retention faults only show at speed. The controller produces a GO/NOGO and, crucially, a failure bitmap (which address/bit) that is diagnostic: a clustered bitmap (a whole column or row) is the signature of a structural, repairable defect (bit-line, sense-amp, select), while scattered bits are random. Because large arrays inevitably carry a few such defects, they ship with spare rows/columns, and BISR (built-in self-repair) swaps in spares and stores the repair signature in efuse — recovering yield that random-defect thinking would scrap, and persisting the repair into the field. Signoff therefore reports the March algorithm and the fault models it covers, runs at-speed, and reports GO/NOGO + bitmap + repair rate — and it is done separately from the logic signoff, then integrated: to logic ATPG the memory is a black box wrapped by a scan collar (so logic faults around it stay covered), while MBIST runs in its own test mode. The debug lesson is a memory-domain echo of diagnosis (13.4): read the bitmap — a column cluster is repairable (BISR), not a scrap and not a respin; you scrap only when spares are exhausted or a decoder fault defeats repair. For the DFT/memory engineer, this case is the MBIST controller + BISR; for the yield engineer, it's the bitmap and repair rate that recover the densest, most defect-prone block; for the logic-DFT engineer, it's the black-box collar that keeps the surrounding logic covered; and for the program, it's the recognition that full-chip test = logic (scan+ATPG) AND memory (MBIST+BISR), each done the right way. In the project thread, the logic of 14.1–14.4 is scan-and-ATPG signed off; the memory is now MBIST-and-BISR signed off; and the final case (14.6) integrates memory and logic into an IP with compression and ATPG at scale. The throughline: memories need their own test — an on-chip, at-speed March — and their bitmap turns failures into diagnosis and repair, recovering yield that scan-thinking would throw away.

13. Engineering Checklist

• Tested the memory with MBIST (on-chip, at-speed March) — not scan/ATPG.
• Produced a failure bitmap and read it (clustered = structural/repairable vs random).
• Repaired with BISR — spare rows/columns; stored the repair signature (efuse) for the field.
• Reported the memory fault models covered + GO/NOGO + bitmap + repair rate; ran at-speed.
• Integrated as a black box + scan collar — memory signed off separately; logic around it still covered.

14. Try Yourself

1. Explain why an SRAM can't be scan-stitched and which memory fault models scan/ATPG doesn't target.
2. Describe MBIST — an on-chip, at-speed March controller (write/read/compare → GO/NOGO + bitmap).
3. Walk the March C- element sequence and say which fault classes it detects.
4. Explain BISR — spare rows/columns, the repair signature (efuse), and yield recovery.
5. Debug an MBIST NOGO with a column-clustered bitmap — why it's repairable (BISR), not random/scrap.

The MBIST/BISR reasoning is tool-neutral; the controller is on-chip, BISR is a memory feature. No paid tool required to reason about the memory case.

15. Interview Perspective

• Weak: "Memories are tested with BIST instead of scan."
• Good: "Memories use MBIST — an on-chip controller running a March algorithm — and BISR repairs bad bits with spares."
• Senior: "A memory is a dense array of bit cells, not flops, so you can't scan-stitch it, and it has fault models scan/ATPG doesn't target — coupling, decoder, retention. So it gets MBIST: an on-chip controller that writes/reads the array with a March algorithm at-speed and compares, producing GO/NOGO + a failure bitmap. The bitmap is diagnosis — a clustered column/row is a structural, repairable defect, and BISR swaps in spare rows/columns, efusing the repair signature to recover yield (persisting to the field). I scrap only when spares are exhausted or it's a decoder fault. The memory is signed off separately (report the fault models covered, GO/NOGO, bitmap, repair rate) and integrated as a black box + collar so logic ATPG still covers the surrounding logic. Logic = scan+ATPG, memory = MBIST — complementary."

16. Interview / Review Questions

17. Key Takeaways

• Memories aren't scannable: an SRAM is a dense array of bit cells (not flops) with memory-specific fault models (stuck-at, transition, coupling, address-decoder, retention) that scan/stuck-at ATPG doesn't target — so memories get a dedicated test.
• MBIST = an on-chip controller that writes/reads the array with a March algorithm (C- the workhorse) at-speed, comparing reads to expected → GO/NOGO + a failure bitmap (which address/bit) — built-in (the array is too big for external patterns) and at-speed (timing/coupling/retention).
• BISR uses the bitmap to swap failing rows/columns for spares, storing the repair signature in efuse → yield recovery (persists to the field) on arrays where a few bad bits are inevitable.
• The bitmap is diagnosis: a clustered column/row is a structural, repairable defect (bit-line/sense-amp) → BISR it; scatter = random; scrap only when spares are exhausted or a decoder fault defeats repair.
• Signed off separately from logic (report fault models covered + GO/NOGO + bitmap + repair rate, run at-speed), then integrated as a black box + scan collar so logic around it stays covered by ATPG. Logic = scan+ATPG, memory = MBIST — complementary. Next: 14.6 — IP: scan + compression + ATPG signoff.

18. Quick Revision

Case study — memory block: MBIST signoff. Scan+ATPG = LOGIC ; MEMORIES need their OWN test. An SRAM = a dense ARRAY of bit cells (not flops) → NOT scan-stitchable, with own fault models (stuck-at, transition, COUPLING, address-DECODER, RETENTION) scan/ATPG misses. MBIST = on-chip controller writes/reads the array with a MARCH algorithm (C- workhorse) AT-SPEED, compares → GO/NOGO + failure BITMAP (address/bit). BISR = swap failing rows/cols for SPARES, store the repair signature in efuse → YIELD RECOVERY (persists to field). Bitmap = diagnosis: clustered column/row = a structural REPAIRABLE defect (bit-line/sense-amp) → BISR ; scatter = random ; scrap only if spares exhausted / decoder fault. Signoff SEPARATE from logic (report fault models covered + GO/NOGO + bitmap + repair rate, at-speed) → INTEGRATE as a black box + scan COLLAR (logic around it covered). Logic=scan+ATPG, memory=MBIST — complementary. Ships RTL (MBIST/March). Next: 14.6 — IP: scan + compression + ATPG signoff.