DFT · Chapter 14 · Industry Case Studies

Case Study — IP: Scan + Compression + ATPG Signoff

The capstone finale integrates the whole DFT track by taking a small IP to complete signoff at scale with compression. The IP is many scan cells organized into many balanced chains, interleaved with FSMs, clock-gated blocks, and memories, all integrated. At scale, thousands of flops become too much test data and time, so compression uses a decompressor to feed many short internal chains from few channels and a compactor to fold the outputs, cutting test data and time roughly ten to a hundred times. The signoff flow integrates every prior lesson in order: scan insertion and stitching, DRC clean, compression, ATPG for stuck-at and at-speed, coverage closure, multi-mode timing, memory MBIST and repair, and a diagnostic mode. The output is a signoff package. At scale every tradeoff, such as compression versus diagnosability, is balanced rather than maximized, and the debug method scales. DFT is one coherent discipline.

Advanced17 min readDFTCase StudyCompressionSignoffIntegration

Chapter 14 · Section 14.6 · Industry Case Studies — chapter & capstone closer

Project thread — the mini-SoC, fully DFT-signed-off: the destination of the whole thread (flip-flop → IP). This closes Chapter 14 and the DFT-technique arc; Chapter 15 is interview/review prep.

1. Why Should I Learn This?

The IP case is where every DFT piece integrates — scan, compression, ATPG, coverage, timing, memory, and debug — into one signed-off, testable, manufacturable block, with every tradeoff balanced at scale.

An IP = millions of scan cells → many chains + FSMs + gated clocks + memories, integrated — full-chip DFT orchestrates all of them.
Compression (decompressor + compactor) cuts test data/time ~10–100× — essential at scale, but lowers diagnosability (→ diagnostic mode).
The 8-step signoff flow integrates every prior lesson → a signoff package (coverage, patterns, SDC, MBIST/repair, DRC, diagnostic mode).
Every tradeoff is balanced, not maximized; the debug method scales; DFT is one coherent discipline.

The five questions — the IP DFT signoff

1 — Why does it exist? Because a real chip is all the pieces at once (scan, memory, gated clocks, at-speed) at scale — DFT must integrate and balance them into one testable IP.
2 — What manufacturing problem does it solve? It makes the whole IP testable and manufacturable — high coverage at feasible test data/time (compression), repaired memories, and timing-clean in every test mode.
3 — What happens if it's omitted? Untestable/expensive-to-test silicon — a coverage hole, exploding test time without compression, or test-broken modes (12.5) that fail in the fab.
4 — Which team owns it? DFT (integrate + sign off), with RTL/DV, STA, memory, product/test — the whole chain (13.6) converges here.
5 — How does it connect up/down-stream? Every prior lesson (Ch1–13) + cases (14.1–14.5) → this integrated IP signoff → the interview/review prep of Ch15.

2. Real Silicon Story — the IP that hit coverage but couldn't be diagnosed

An IP reached its ATPG coverage target and looked ready to sign off. But two problems surfaced at integration: diagnosis was loose (real defects localized to dozens of candidates), and a few chains showed shift-hold miscompares. A respin was discussed.

Neither was a coverage or defect problem — both were scale/integration issues with known fixes. The loose diagnosis was compression (7.x): the compactor hid which cell failed, so diagnosis couldn't intersect cones tightly (13.4). The fix was to enable the diagnostic (bypass) mode — un-compact the failing patterns to restore per-cell observability — which tightened diagnosis to a few candidates. The shift-hold miscompares were chain imbalance across the integrated blocks (12.2): the fix was to rebalance the chains and add lock-up latches across the domain crossings. With both fixed — diagnostic mode + rebalanced chains — the IP re-closed cleanly: coverage held, diagnosis localized, timing was test-clean in every mode, and the memories were MBIST/BISR signed off. The IP signed off with a complete package — no respin. Lesson: at IP scale, the whole method integrates — compression trades data/time for diagnosability (restore it with a diagnostic mode), chains must be balanced (lock-ups), timing must be test-clean across modes, and memory is MBIST. DFT is one discipline, and every tradeoff is balanced into a signed-off, manufacturable IP.

3. Factory Perspective — the IP signoff through each lens

What the DFT engineer sees: the full integration — chains + compression + collared memories + test-controlled gated clocks — and the 8-step signoff flow to a package.
What the STA engineer sees: multi-mode timing (functional + shift + capture/at-speed) all clean = test-clean (12.5), plus SE/OCC at-speed (12.x).
What the product/test engineer sees: compressed patterns (feasible test time/data) + a diagnostic mode for localization + MBIST/repair — the manufacturable test program.
What management cares about: that the IP is signed off, testable, and manufacturable — high coverage at feasible cost, repaired memories, balanced tradeoffs — the destination of the whole DFT investment.

4. Concept — the integrated IP and the 8-step signoff

The IP (everything, integrated):

Many scan cells (14.1 ×millions) → many balanced chains (14.2 at scale) + FSMs (14.3) + clock-gated blocks (14.4, test-controlled) + memories (14.5, collared/MBIST). Full-chip DFT orchestrates all of them.

Compression (the scale enabler, 7.x):

Thousands of flops → hundreds of chains → too much test data/time at full external width.
A decompressor feeds many internal short chains from few external channels; a compactor folds many outputs to few → cuts test data/time ~10–100×.

The full signoff flow (integrate every prior lesson):

Scan insertion + stitching (all flops → chains, 3.x/4.x/14.1/14.2).
Scan DRC clean — clocks/resets/latches; clock-gated blocks test-controlled (14.4); memories collared (14.5) (4.x).
Compression inserted + configured (care bits, X-masking, diagnostic mode, 7.x).
ATPG — stuck-at + at-speed (transition) on the compressed netlist (5.x/12.4).
Coverage closure — test + fault coverage, classify redundant, close gaps (6.x/14.3).
Timing — multi-mode STA: functional + shift + capture/at-speed all clean = test-clean (12.5).
Memory — MBIST + BISR signed off separately, integrated (14.5).
Pattern set — compressed patterns + a diagnostic (bypass) mode for localization (13.4).

→ Signoff package: coverage report, pattern set, SDC/timing, MBIST/repair, DRC, diagnostic mode.

The tradeoffs (balanced, not maximized):

Compression vs diagnosability (→ diagnostic mode, 13.4); coverage vs pattern count/test time; at-speed vs SE/OCC timing (12.x); test-clean across all modes (12.5).
The IP is where every tradeoff is balanced.

Integration & debug at scale:

Sub-blocks signed off (logic scan+ATPG, memory MBIST) then the top integrates chains, compression, test modes, and a single test access (JTAG/1500, 10.x/11.x). A chip = sub-blocks + integration.
Debug at scale = the whole method (Ch13) — fork, structure-first, flush, golden sim, diagnosis (with a diagnostic mode to beat compression), bring-up. The method scales.

Figure 1 - the full DFT stack of an IP, integrated (representative). From the bottom: SCAN CELLS (14.1) -> stitched into many balanced CHAINS (14.2) -> COMPRESSION (decompressor feeds internal chains, compactor folds outputs; ~10-100x less data/time) (7.x) -> ATPG stuck-at + at-speed on the compressed netlist (5.x/12.4) -> COVERAGE closure (test+fault, classify redundant) (6.x) -> multi-mode TIMING (functional+shift+capture = test-clean) (12.5) -> MEMORY MBIST+BISR (collared, separate) (14.5) -> SIGNOFF PACKAGE (coverage, patterns, SDC, MBIST/repair, DRC, diagnostic mode). Every layer integrates a prior lesson ; the IP balances every tradeoff.

5. Mental Model — conducting an orchestra, not playing one instrument

Signing off an IP is conducting an orchestra — not playing one instrument brilliantly, but making every section play together, in balance.

Each earlier case mastered one instrument: the scan cell (a single note, 14.1), the counter/chain (a phrase, 14.2), the FSM (a melody, 14.3), the clock-gated block (a section that rests to save energy, 14.4), the memory (a different family of instruments entirely — percussion you can't bow, 14.5). The IP is the full score: all sections at once.
The conductor (full-chip DFT) doesn't make any one section louder forever (maximize) — that would drown the others. Compression is like fewer microphones capturing many players (less data/cost) — but with fewer mics you can't tell which player hit a wrong note (diagnosability drops), so you keep a way to solo each section (a diagnostic mode) when you need to find the mistake.
Everything must be in time together — the functional, shift, and capture tempos all clean (multi-mode timing) — or the performance falls apart even if each section is individually perfect (functional-clean is not test-clean).
And the percussion (memory) is rehearsed and tuned separately (MBIST/BISR), then brought into the full score. The art is balance: coverage vs test time, compression vs diagnosability, speed vs timing margin — all tuned together into one performance you can sign off and ship.

Conduct the whole orchestra in balance (integrate + balance every DFT piece) — don't maximize one section; keep a way to solo (diagnostic mode); keep every tempo together (multi-mode timing); rehearse percussion separately (memory MBIST) — into one signed-off performance.

6. Working Example — the IP DFT architecture & signoff package

Sketch the compressed scan architecture and the signoff package:

Azvya Education Pvt. Ltd.VLSI Mentor

Snippet

# IP DFT architecture (compressed multi-chain + memory + test modes) - REPRESENTATIVE, tool-neutral:
  EXTERNAL: few scan channels (e.g. 8 in / 8 out)  <-- ATE pins (limited)
     |  DECOMPRESSOR (spreads 8 channels -> 200 internal short chains)          (7.x)
     v
  INTERNAL: 200 balanced short chains of scan cells (14.1 x thousands each)     (3.x/4.x/14.2)
     |  ... interleaved with FSM logic (14.3), test-controlled clock-gated blocks (14.4) ...
     |  ... MEMORIES as black boxes with scan COLLARS (14.5), tested by MBIST in a separate mode ...
     v
     COMPACTOR (folds 200 chain outputs -> 8 external channels ; X-masking to protect the signature) (7.x/9.x)
  DIAGNOSTIC MODE: bypass the compactor -> per-cell observability for localization                    (13.4)
 
# THE 8-STEP SIGNOFF FLOW:
  1 scan insertion + stitching        (all flops -> 200 chains)                 [3.x/4.x/14.1/14.2]
  2 scan DRC clean                    (clocks/resets/latches; gated blocks TE'd; memories collared) [4.x/14.4/14.5]
  3 compression inserted + configured (care bits, X-masking, diagnostic mode)   [7.x]
  4 ATPG                              (stuck-at + at-speed/transition, compressed) [5.x/12.4]
  5 coverage closure                  (test + fault coverage; classify redundant) [6.x/14.3]
  6 multi-mode STA                    (functional + shift + capture/at-speed = test-clean) [12.5]
  7 memory MBIST + BISR               (signed off separately, integrated)        [14.5]
  8 pattern set + diagnostic mode     (compressed patterns + bypass for localization) [13.4]
 
# SIGNOFF PACKAGE (the deliverable): coverage report + pattern set + SDC/timing + MBIST/repair + DRC + diagnostic mode
# EVERY TRADEOFF BALANCED: compression vs diagnosability | coverage vs test time | at-speed vs SE/OCC | all modes clean

The artifact in four questions — the IP DFT signoff package

What is it? The complete IP DFT signoff package — coverage report (test + fault), pattern set (compressed stuck-at + at-speed), SDC/multi-mode timing, MBIST/repair results, scan DRC, and the diagnostic mode — everything needed to manufacture and test the IP.
Who generates it? DFT (integration + signoff), consolidating RTL/DV, STA, memory, ATPG, product/test contributions — the whole chain (13.6).
Who consumes it? tapeout/signoff (go/no-go), the ATE/HVM (the test program), integration into a larger SoC (the IP as a reusable, testable block), and debug/yield (diagnostic mode, MBIST bitmap).
Why should an RTL/DV / DFT engineer care? It's the destination of the whole track — the proof the IP is testable, manufacturable, and debuggable, with every tradeoff balanced; it's what makes a block shippable and reusable.

Compression is the scale enabler — few external channels drive many internal chains, folded back to few:

Figure 2 - compression at IP scale: few channels, many internal chains (representative). Few EXTERNAL scan channels (ATE pins are limited) feed a DECOMPRESSOR that spreads them across MANY internal SHORT chains - so thousands of flops shift in parallel on a handful of pins, cutting test TIME. On the output side a COMPACTOR folds the many chain outputs back to few external channels, cutting test DATA volume - together ~10-100x less than full external width. X-MASKING protects the compactor signature from unknowns (7.x/9.x). The cost: the compactor HIDES which exact cell failed -> lower diagnosability -> a DIAGNOSTIC (bypass) mode restores per-cell observability for localization (13.4). Memories sit alongside as collared black boxes (MBIST).

7. Industry Flow — the 8-step IP signoff

The IP signoff runs the eight integrated steps, from scan insertion to the diagnostic-mode-equipped pattern set:

Figure 3 - the IP DFT signoff flow (representative). (1) Scan INSERTION + stitching (all flops -> chains). (2) Scan DRC clean (clocks/resets/latches; gated blocks test-controlled; memories collared). (3) COMPRESSION inserted (care bits, X-masking, diagnostic mode). (4) ATPG stuck-at + at-speed on the compressed netlist. (5) COVERAGE closure (test+fault, classify redundant). (6) Multi-mode STA (functional+shift+capture = test-clean). (7) MEMORY MBIST+BISR (separate, integrated). (8) PATTERN SET + diagnostic mode. -> the SIGNOFF PACKAGE. Each step integrates a prior lesson ; the IP balances every tradeoff into a testable, manufacturable block.

8. Debugging Session — the IP that closed coverage but not diagnosis or timing

At IP scale the ATPG coverage target is met and the block looks ready to sign off, but two integration issues remain: diagnosis is loose because compression hides which cell failed so real defects localize to dozens of candidates, and a few chains show shift-hold miscompares from imbalance across the integrated blocks -- and the fix is to enable the diagnostic bypass mode to restore per-cell observability for localization and to rebalance the chains and add lock-up latches for the shift-hold, after which the IP re-closes cleanly across coverage, diagnosis, and multi-mode timing and signs off with a complete package and no respin

AN IP INTEGRATES EVERY DFT PIECE — BALANCE THE TRADEOFFS: A DIAGNOSTIC MODE FOR COMPRESSION, REBALANCED CHAINS FOR SHIFT-HOLD; THE WHOLE METHOD SCALES

Symptom

At IP scale, ATPG coverage meets target and the block looks ready to sign off — but two issues remain: diagnosis is loose (real defects localize to dozens of candidates), and a few chains show shift-hold miscompares. A respin is floated. Coverage's fine — so what's wrong?

Root Cause

Neither issue is a coverage or defect problem; both are scale/integration issues with known fixes: diagnosis is loose because compression hides which exact cell failed (the compactor collapses per-cell observability), and the shift-hold miscompares come from chain imbalance across the integrated blocks. At IP scale, DFT is an integration of every prior piece, and two of those pieces interact in ways that only appear at scale. (1) Loose diagnosis = compression (7.x/13.4): to cut test data/time ~10–100×, a compactor folds many chain outputs to few, so the datalog records which compacted signature bit miscompared, not which individual cell — collapsing the observability that diagnosis needs to intersect back-cones tightly (13.4). The result is a genuinely real defect that localizes loosely — not a tool failure and not many defects, just missing observability by design. (2) Shift-hold miscompares = chain imbalance (12.2): integrating sub-blocks that were designed separately yields chains with unequal delays / domain crossings, and shift = a HOLD problem (adjacent cells clocked together) — imbalance and missing lock-up latches across crossings produce hold violations that appear as shift miscompares. Both are the expected consequences of operating at scale — compression's diagnosability cost and integration's timing cost — and both have standard remedies. Crucially, coverage being at target does not mean signoff: an IP is test-clean only when diagnosis works (you can localize real defects) and timing is clean in every mode (shift included), not just when the coverage number is hit. Respinning would be wrong — nothing is broken by design; the tradeoffs just need balancing.

Fix

Balance the tradeoffs, don't respin: enable the diagnostic bypass mode to restore per-cell observability for localization, and rebalance the chains and add lock-up latches to fix the shift-hold, then re-close — after which the IP is clean across coverage, diagnosis, and multi-mode timing and signs off with a complete package. For diagnosis, use the diagnostic (bypass) mode built in at step 3: bypass the compactor for the failing patterns to restore per-cell observability, so diagnosis intersects cones precisely and tightens to a few candidates for PFA (13.4) — this is exactly why a diagnostic mode is part of the signoff package. For the shift-hold, rebalance the integrated chains (equalize lengths/delays) and add lock-up latches across the clock-domain crossings so shift hold is met (12.2) — a shift-run STA (12.5) confirms it. Then re-close the full flow: coverage still meets target, diagnosis now localizes, multi-mode timing (functional + shift + capture/at-speed) is all clean = test-clean, and the memories remain MBIST/BISR signed off — the IP signs off with the complete package (coverage, patterns, SDC, MBIST/repair, DRC, diagnostic mode), no respin. The principle to lock in: a real IP is the integration of every DFT technique at scale — millions of scan cells in many chains, FSMs, test-controlled clock-gated blocks, and MBIST-tested memories, with compression to make test data and time feasible — and signoff is not a single number but a balanced package, because at scale every technique carries a tradeoff: compression cuts test data and time ~10–100× but lowers diagnosability (restored by a diagnostic bypass mode), integration can imbalance chains and violate shift hold (fixed by rebalancing and lock-up latches), at-speed stresses scan-enable and OCC timing, and a design is test-clean only when all modes are clean; so you balance, not maximize, each tradeoff, you sign off on coverage AND diagnosis AND multi-mode timing AND memory repair, and you debug at scale with the very same method (fork, structure-first, flush, golden sim, diagnosis with a diagnostic mode, bring-up) that you learned on one bit — because DFT is one coherent discipline whose method scales from a single flip-flop to a full IP, and hitting a coverage number is necessary but not sufficient for a testable, manufacturable, debuggable block. (Compression and diagnostic mode are 7.x/13.4; shift-hold and multi-mode timing are 12.2/12.5; the debug method is Ch13; the memory is 14.5; the scan atom is 14.1 — this case integrates them all and closes the capstone.)

9. Common Mistakes

Treating a coverage number as signoff. An IP is test-clean only with diagnosis working + timing clean in every mode + memory repaired — not just coverage.
Maximizing one tradeoff. Over-compressing kills diagnosability; chasing coverage explodes test time — balance, don't maximize.
Forgetting the diagnostic mode. Compression hides the failing cell — build a bypass/hi-res mode for localization (13.4).
Ignoring chain balance at integration. Integrated sub-blocks → imbalanced chains / shift-hold — rebalance + lock-ups (12.2).
Skipping multi-mode timing. Functional-clean is not test-clean — close functional + shift + capture/at-speed (12.5).

10. Industry Best Practices

Integrate all pieces — chains, compression, FSMs, test-controlled gated clocks, collared memories — under one test access (JTAG/1500).
Use compression to cut test data/time ~10–100×, with X-masking and a diagnostic mode (7.x/13.4).
Run the full 8-step signoff — insertion → DRC → compression → ATPG (stuck-at + at-speed) → coverage → multi-mode STA → MBIST → patterns+diag.
Balance every tradeoff — compression vs diagnosability, coverage vs test time, at-speed vs SE/OCC, all modes clean.
Deliver the signoff package — coverage, patterns, SDC, MBIST/repair, DRC, diagnostic mode — and debug at scale with the whole method.

11. Senior Engineer Thinking

Beginner: "Coverage hit target — the IP is signed off."
Senior: "Coverage is necessary, not sufficient. At IP scale I integrate everything and balance the tradeoffs: compression cuts test data/time but loosens diagnosis — so I built a diagnostic mode to un-compact and localize. Integration imbalanced a few chains → shift-hold — I rebalance + add lock-ups (12.2). I close multi-mode timing (functional + shift + capture = test-clean), keep memories on MBIST/BISR, and deliver the full signoff package. DFT is one discipline — the same method I used on one bit scales to this IP. No respin — just balance."

The senior treats signoff as a balanced package (coverage + diagnosis + multi-mode timing + memory), and debugs at scale with the same method learned on one bit.

12. Silicon Impact

The IP case is the destination of the entire DFT track — the point where control + observe on one bit (14.1) becomes a signed-off, testable, manufacturable block containing everything: millions of scan cells in many balanced chains (14.2 at scale), FSMs (14.3), test-controlled clock-gated blocks (14.4), and MBIST/BISR memories (14.5), all integrated under a single test access (JTAG/1500). At this scale, a force absent from the small cases dominates: test data and time. Thousands of flops at full external width would need impractical ATE data and time, so compression (7.x) — a decompressor feeding many internal short chains from few external channels, and a compactor folding many outputs to few — cuts both ~10–100×, which is why compression exists. But compression carries a cost — it hides which cell failed, lowering diagnosability — and that is the case's central theme: at scale, every technique carries a tradeoff, and signoff is about balancing them, not maximizing any one. The full signoff flow integrates every prior lesson in eight steps — insertion + stitching → scan DRC (gated blocks test-controlled, memories collared) → compression (care bits, X-masking, diagnostic mode) → ATPG (stuck-at + at-speed) → coverage closure (test + fault, classify redundant) → multi-mode STA (test-clean) → memory MBIST + BISR → pattern set + diagnostic mode — producing a signoff package: coverage, patterns, SDC/timing, MBIST/repair, DRC, and the diagnostic mode. The debug lesson at scale is that coverage hitting target is necessary but not sufficient: an IP is test-clean only when diagnosis works (restore observability with a diagnostic bypass mode when compression loosens it, 13.4), timing is clean in every mode (integration can imbalance chains and violate shift hold — rebalance and add lock-ups, 12.2/12.5), and memories are repaired (MBIST/BISR). And crucially, debug at scale uses the same method learned on one bit (Ch13) — fork, structure-first, flush, golden sim, diagnosis, bring-up — because the method scales. For the DFT engineer, this case is integration + the signoff package; for the STA engineer, multi-mode test-clean timing; for the product/test engineer, compressed patterns + a diagnostic mode + MBIST = a manufacturable program; for management, a shippable, reusable, testable IP; and for the whole chain (13.6), the convergence point where every phase's work pays off — or where a skipped upstream fix surfaces. The finale message of the capstone is a single coherent claim: DFT is one discipline — control + observe scaled by chains + compression, ATPG for logic, MBIST for memory, multi-mode timing, and one debug method — all balanced into a signed-off, testable, manufacturable IP. This closes the capstone and the DFT-technique arc; Chapter 15 turns to interview and signoff-review preparation — being ready to talk and defend everything this track has built. From a single testable bit to a fully signed-off IP, the thread is complete: that is DFT.

13. Engineering Checklist

Integrated all pieces — chains, compression, FSMs, test-controlled gated clocks, collared memories — under one test access.
Ran the full 8-step signoff — insertion → DRC → compression → ATPG (stuck-at + at-speed) → coverage → multi-mode STA → MBIST → patterns+diag.
Used compression with X-masking and a diagnostic mode — cut test data/time, kept diagnosability (7.x/13.4).
Balanced every tradeoff — compression vs diagnosability, coverage vs test time, at-speed vs SE/OCC, all modes clean (12.5).
Delivered the signoff package (coverage + patterns + SDC + MBIST/repair + DRC + diagnostic mode) — and debugged at scale with the whole method.

14. Try Yourself

Describe the IP as an integration of every earlier piece (scan cells → chains, FSMs, gated clocks, memories).
Explain why compression is needed at scale and its cost (diagnosability) — and how a diagnostic mode mitigates it (7.x/13.4).
Walk the 8-step signoff flow and name the prior lesson each step integrates.
Explain why coverage hitting target is not signoff — what else must be clean (diagnosis, multi-mode timing, memory).
Show how the debug method scales — debugging an IP-scale coverage/diagnosis/timing issue with the Ch13 method.

The IP signoff reasoning is tool-neutral and integrates the whole track; the package is a DFT deliverable. No paid tool required to reason about the IP case.

15. Interview Perspective

Weak: "For an IP you run scan and ATPG and get coverage up."
Good: "An IP integrates scan chains, compression, and memory BIST, and you sign off on coverage, timing, and repair."
Senior: "A real IP is the integration of every DFT technique at scale: millions of scan cells in many chains, FSMs, test-controlled clock-gated blocks, and MBIST/BISR memories, with compression (decompressor + compactor) to cut test data/time ~10–100×. Signoff is a balanced package, not a number: I run the 8-step flow — insertion+DRC → compression → ATPG (stuck-at + at-speed) → coverage closure (test + fault, classify redundant) → multi-mode STA (functional + shift + capture = test-clean) → memory MBIST+BISR → patterns + a diagnostic mode. Every tradeoff is balanced: compression vs diagnosability (I keep a bypass mode, 13.4), coverage vs test time, at-speed vs SE/OCC (12.x). And I debug at scale with the same method I used on one bit — fork, structure-first, flush, golden sim, diagnosis, bring-up. DFT is one discipline — from a single testable bit to a fully signed-off IP."

16. Interview / Review Questions

17. Key Takeaways

An IP integrates every DFT piece at scale: millions of scan cells (14.1) → many balanced chains (14.2) + FSMs (14.3) + test-controlled clock-gated blocks (14.4) + MBIST/BISR memories (14.5), under one test access (JTAG/1500). Full-chip DFT orchestrates all of them.
Compression (decompressor + compactor) cuts test data/time ~10–100× — essential at scale — but lowers diagnosability (the compactor hides the failing cell) → keep a diagnostic (bypass) mode (7.x/13.4) and X-masking (9.x).
The 8-step signoff flow integrates every prior lesson: insertion+stitching → scan DRC → compression → ATPG (stuck-at + at-speed) → coverage closure → multi-mode STA → memory MBIST+BISR → patterns + diagnostic mode → a signoff package (coverage, patterns, SDC, MBIST/repair, DRC, diagnostic mode).
Every tradeoff is balanced, not maximized: compression vs diagnosability, coverage vs test time, at-speed vs SE/OCC timing, test-clean across all modes (12.5). Coverage hitting target is necessary but not sufficient — diagnosis, multi-mode timing, and memory repair must all be clean.
The debug method scales: an IP-scale issue is debugged with the same Ch13 method (fork, structure-first, flush, golden sim, diagnosis-with-a-diagnostic-mode, bring-up) learned on one bit. DFT is one coherent discipline — from a single testable bit to a fully signed-off, testable, manufacturable IP. Next: Chapter 15 — interview & signoff-review preparation.

18. Quick Revision

Case study — IP: scan + compression + ATPG signoff (Ch14 + capstone CLOSER). An IP integrates EVERYTHING at scale: millions of scan cells (14.1) → many balanced CHAINS (14.2) + FSMs (14.3) + test-controlled gated clocks (14.4) + MBIST/BISR memories (14.5), under one test access (JTAG/1500). COMPRESSION (decompressor feeds many internal chains from few channels ; compactor folds outputs) cuts test DATA/TIME ~10-100x — but LOWERS diagnosability → keep a DIAGNOSTIC (bypass) mode (13.4) + X-masking (9.x). 8-STEP SIGNOFF: insertion+stitch → scan DRC → compression → ATPG (stuck-at + at-speed) → coverage closure (test+fault, classify) → multi-mode STA (functional+shift+capture = test-clean, 12.5) → memory MBIST+BISR → patterns + diagnostic mode → SIGNOFF PACKAGE. BALANCE every tradeoff (compression vs diagnosability, coverage vs test time, at-speed vs SE/OCC, all modes clean) — coverage alone is NOT signoff. The debug method SCALES (Ch13). DFT is ONE discipline — from one testable bit to a fully signed-off IP. Ships the IP DFT architecture + signoff package. Next: Ch15 — interview & signoff-review prep.