DFT · Topic
Scan Insertion — DRC, Stitching & Test-Mode Control
Inserting scan into a netlist — scan design rules, stitching order, test-mode control of clocks and resets, and what breaks the flow.
Scan insertion is mostly a negotiation with the design's existing clocking and reset. Every asynchronous reset, gated clock and generated clock is a scan design-rule question, because during shift the tool must be able to clock every flop and must not let anything reset them. Pages of DRC violations almost always trace back to a handful of structures — an ungated asynchronous reset, a clock the tool cannot control, a latch in a data path.