From RTL to Scan-Ready Logic

Chapter 4 · Section 4.1 · Scan Insertion & DRC

Project thread — the counter is scannable (3.6). The project now grows an FSM (state register + next-state logic). This lesson sets the rules the FSM must follow; 4.5 inserts scan on it.

1. Why Should I Learn This?

Scan-ready RTL is the contract that lets scan insertion and ATPG succeed — and it's your responsibility as the RTL author.

• Synchronous: every flop on a defined clock edge; no combinational loops.
• Controllable clocks: no gated/internal clocks ATPG can't control (4.4).
• Controllable resets: async reset off during shift/capture (4.4).
• No uninferred latches, no bus contention — they break scan / create X (4.4).
• Shift-left: fixing in RTL is cheap; after synthesis/P&R it's expensive.

2. Real Silicon Story — the gated clock found at signoff

An RTL team used a hand-rolled gated clock to save power on a block — a common, reasonable-looking optimization. Everything simulated fine; functionally it was correct.

Then, at DFT signoff, scan DRC failed on that block: the gated clock was uncontrollable in test, so ATPG couldn't clock the scan cells behind it — those flops couldn't shift or capture, and their coverage collapsed. Worse, the discovery came after synthesis and placement, so the fix (adding test-controllable clock gating — a test-enable bypass, 4.4) meant re-running synthesis, timing, and DFT — days of iteration near a deadline.

Had the design followed the scan-ready contract — test-controllable clock gating from the start, flagged by DFT lint in RTL — the fix would have been a one-line change reviewed in minutes. Lesson: scan-hostile constructs are cheap to fix in RTL and expensive to fix late — scan-readiness is a shift-left discipline, not a signoff afterthought.

3. Factory Perspective — scan-readiness through each lens

• What the test engineer sees: whether the netlist passes scan DRC (4.3) and reaches coverage — scan-hostile RTL shows up as DRC violations and coverage holes.
• What the yield engineer sees: that coverage holes → escapes; a block that couldn't be scanned ships undetected defects → DPPM risk (1.5).
• What the RTL/DV engineer sees: the DFT-lint report on their code — gated clocks, async resets, latches, loops flagged as fix-now items, cheapest in RTL.
• What management cares about: shift-left economics — a scan-hostile construct caught in RTL review costs minutes; caught at signoff costs a respin of the flow and schedule.

4. Concept — the scan-ready rules and why each exists

Synchronous design:

• Every flop clocked by a defined clock edge; state changes only on clocks.
• No combinational feedback loops (they create unstable, un-analyzable values → ATPG can't reason).
• Why: scan/ATPG model the netlist as flops + combinational logic between them (3.1) — that model requires clean synchronous structure.

Controllable clocks:

• No gated or internally-generated clock that ATPG can't control during test.
• In test, the clock must reach and control every scan cell (test-controllable clock gating; OCC for internal clocks — 4.4).
• Why: if ATPG can't pulse a flop's clock deterministically, it can't shift or capture it → those flops are untestable.

Controllable resets:

• Asynchronous set/reset must be forced inactive during scan shift and capture (test-mode control).
• Why: a reset that fires during scan clears/sets loaded state → corrupts the stimulus/response (4.4).

No uninferred latches:

• A level-sensitive latch is not a scan cell; if present, make it transparent/controllable in test or convert to flops.
• Why: latches are not controllable/observable like flops, and transparent latches pass X and create timing ambiguity (4.4).

No bus contention / uncontrollable X:

• Tristate buses must have a defined driver in test (no float/contention); avoid uninitialized X sources.
• Why: X (unknown) captured and shifted out corrupts the signature (3.4) → coverage loss / false fails.

The shift-left economics:

• RTL fix: a code review comment, minutes. Post-synthesis fix: re-run synthesis/timing/DFT, days.
• So DFT lint runs on RTL, catching violations at their cheapest point.

5. Mental Model — building to code so the inspector passes

Think of scan-readiness like building a house to electrical/building code so the inspection (scan DRC, 4.3) passes cheaply.

• Synchronous design, controllable clocks/resets, no latches are the code requirements — follow them and the inspector signs off in one pass.
• A gated clock or async reset is like non-code wiring hidden in the walls: it works day-to-day (simulates fine) but fails inspection and forces you to open the walls (re-run synthesis/P&R) to fix it — hugely more expensive than doing it right during framing (RTL).
• DFT lint is the pre-inspection walkthrough with your own checklist — catch the violations before the official inspector, while the walls are still open (still in RTL).
• Building to code from the start is boring but cheap; retrofitting to pass inspection is painful and late.

Follow the testability code in RTL, and the scan inspection passes on the first try.

6. Working Example — scan-friendly vs scan-hostile RTL

Contrast a scan-friendly flop with common scan-hostile constructs (project FSM style):

// SystemVerilog — SCAN-FRIENDLY: synchronous flop, synchronous reset, defined clock
module good_reg (input logic clk, rst_n, d, output logic q);
  always_ff @(posedge clk)              // one defined clock edge
    if (!rst_n) q <= 1'b0;              // synchronous reset (clean for scan)
    else        q <= d;
endmodule

// Verilog-2001 — SCAN-HOSTILE examples (what DFT lint flags)
// (1) hand-gated clock ATPG can't control:
  wire gclk = clk & enable;            // gated clock -> uncontrollable in test (fix: test-controllable gating, 4.4)
  always @(posedge gclk) q <= d;
// (2) async reset that can fire during scan:
  always @(posedge clk or negedge arst_n)
    if (!arst_n) q <= 1'b0;            // async reset -> must be OFF in scan (fix: gate reset in test, 4.4)
    else         q <= d;
// (3) an inferred latch:
  always @(*) if (en) q = d;          // level-sensitive latch -> not a scan cell (fix: flop or test-transparent, 4.4)

# DFT-lint / scan-readiness report — REPRESENTATIVE, SIMPLIFIED, tool-neutral:
  RULE clock_control   : FAIL  block U_pwr : gated clock 'gclk' not test-controllable   -> fix in RTL (4.4)
  RULE async_reset     : FAIL  reg  q_arst : async reset active in scan mode            -> gate reset in test (4.4)
  RULE no_latch        : FAIL  sig  q_latch: inferred level-sensitive latch             -> convert to flop (4.4)
  RULE comb_loop       : PASS
  RULE bus_contention  : PASS
# Each FAIL would become a scan DRC violation (4.3) + coverage loss if shipped to insertion. Fix NOW (cheap) in RTL.

7. Industry Flow — scan-readiness is the first gate

Scan-ready RTL gates the entire structural-test flow — before insertion:

8. Debugging Session — coverage hole traced to scan-hostile RTL

9. Common Mistakes

• Hand-gating clocks without test control. ATPG can't clock those flops → untestable (use test-controllable gating, 4.4).
• Async resets left active in scan. They corrupt loaded state → gate them off in test (4.4).
• Inferred latches. Not scan cells → convert to flops or make test-transparent (4.4).
• Combinational loops / bus contention. Create X and un-analyzable logic → remove them.
• Deferring DFT checks to signoff. A scan-hostile construct is cheap in RTL, expensive late — shift-left.

10. Industry Best Practices

• Run DFT lint on RTL — catch scan-hostility at its cheapest point.
• Design synchronous — defined clocks, no loops, clean reset discipline.
• Make clock gating and resets test-controllable from the start (4.4).
• Ban uninferred latches in synthesizable RTL (or handle them explicitly).
• Treat testability as a design property — a shift-left owner on the RTL/DV team.

11. Senior Engineer Thinking

• Beginner: "Coverage is low on this block — the ATPG tool must be weak."
• Senior: "Late coverage holes usually mean a scan-hostile construct — a gated clock, an async reset, a latch — that broke scan on those flops. ATPG can't fix a design that isn't scannable. I trace it to the rule violation, fix it test-controllable (4.4), and add the check to DFT lint in RTL so it's caught in minutes next time, not days at signoff."

The senior treats coverage holes as scan-readiness issues and shifts the check left into RTL.

12. Silicon Impact

Scan-readiness is the cheapest, highest-leverage point in the entire DFT flow, because it's where a testability problem costs minutes instead of days. The rules are simple — synchronous design, controllable clocks and resets, no uninferred latches, no loops or contention — but each one directly protects a downstream stage: clean synchronous structure is what makes ATPG's flops-plus-combinational-logic model valid (3.1), controllable clocks/resets are what let scan shift and capture deterministically (3.3–3.4), and no latches/X-sources is what keeps the captured response clean (3.4). Violate any of them and the cost compounds downstream: a scan-hostile construct becomes a scan DRC failure (4.3), then an untestable region and a coverage hole, then an escape and a DPPM hit (1.5) — and if it's discovered after synthesis or place-and-route, the fix means re-running the flow, a real schedule risk. That is the shift-left argument in one sentence: testability is a design property, and the RTL author is its first owner. For the RTL/DV engineer, the practical payoff is concrete — write synchronous, test-controllable RTL and run DFT lint, and your blocks flow cleanly through insertion (4.2), DRC (4.3), and ATPG (Ch5) to the coverage the part's quality contract depends on. The project's new FSM is the test case: build it scan-ready now, and 4.5's scan insertion on it is uneventful — exactly what you want.

13. Engineering Checklist

• Design is synchronous — defined clock edges, no combinational loops.
• Clocks controllable in test (test-controllable gating / OCC for internal clocks — 4.4).
• Async resets forced inactive during scan shift/capture (4.4).
• No uninferred latches (or made test-transparent / converted to flops).
• DFT lint run on RTL; violations fixed in RTL (shift-left), not at signoff.

14. Try Yourself

1. Write a scan-friendly flop (synchronous, synchronous or test-controllable reset, defined clock).
2. Write three scan-hostile snippets: a gated clock, an async reset, an inferred latch — predict the DFT-lint FAILs.
3. For each, state what breaks in scan (can't clock / corrupts state / not a scan cell) and the test-mode fix (4.4).
4. Argue the shift-left economics: cost to fix in RTL review vs at DFT signoff.
5. Note that the project FSM must obey these rules so 4.5's insertion is clean.

The rules are tool-neutral. Real checks come from a DFT-lint/testability tool; fixes are in RTL. No paid tool required to reason about scan-readiness.

15. Interview Perspective

• Weak: "Scan-ready means the design can be scanned."
• Good: "It means synchronous design with controllable clocks and resets and no latches, so scan insertion works."
• Senior: "Scan-ready RTL honors a contract so scan insertion and ATPG — which assume a synchronous, controllable netlist — succeed. Concretely: synchronous (defined clock edges, no combinational loops), controllable clocks (no gated/internal clock ATPG can't control — test-controllable gating, OCC), controllable resets (async reset forced inactive during shift/capture), no uninferred latches (not scan cells), and no bus contention/X sources. Each rule prevents a specific failure — can't-clock, corrupted capture, uncontrollable state, X corruption. And it's shift-left: a violation costs minutes in RTL via DFT lint but days after synthesis/P&R — so testability is a design property the RTL author owns first."

16. Interview / Review Questions

17. Key Takeaways

• Scan-ready RTL is the design-for-scan contract that lets scan insertion and ATPG — which assume a synchronous, controllable netlist — achieve high coverage.
• The rules: synchronous (defined clock edges, no combinational loops), controllable clocks (no uncontrollable gated/internal clocks — 4.4), controllable resets (async reset inactive during shift/capture — 4.4), no uninferred latches (not scan cells — 4.4), and no bus contention / X sources.
• Each rule prevents a specific failure — can't clock, corrupted capture, uncontrollable state, X corruption — and violations become scan DRC failures (4.3), untestable logic, and coverage holes.
• Testability is a design property, best enforced early with DFT lint on RTL — a shift-left discipline.
• Fixing in RTL costs minutes; fixing after synthesis/P&R costs days — so scan-readiness is a first-class RTL/DV responsibility, and the project FSM must be written scan-ready for a clean 4.5 insertion. Next: 4.2 — scan stitching & chain ordering.

18. Quick Revision

From RTL to scan-ready (Ch4 opener). Scan insertion + ATPG assume a synchronous, controllable netlist → scan-ready RTL is the CONTRACT. Rules: synchronous (defined clock edges, no combinational loops), controllable clocks (no gated/internal clock ATPG can't control — 4.4), controllable resets (async reset OFF during shift/capture — 4.4), no uninferred latches (not scan cells — 4.4), no bus contention/X. Violations → scan DRC failures (4.3), untestable logic, coverage holes. SHIFT-LEFT: fix in RTL (minutes, via DFT lint) not after synthesis/P&R (days). Testability = a design property the RTL author owns. Project FSM must be scan-ready → clean 4.5 insertion. Next: 4.2 — scan stitching & chain ordering.