Uncontrolled Clocks, Resets & Latches

Chapter 4 · Section 4.4 · Scan Insertion & DRC

Project thread — these are the fixes that make the FSM's clock/reset test-clean in 4.5, so its scan DRC (4.3) passes and ATPG (Ch5) succeeds.

1. Why Should I Learn This?

Uncontrolled clocks, resets, and latches are the top three scan DRC violations — and each has a standard test-mode fix you must know.

• Uncontrolled clocks (gated/derived) → can't shift/capture → fix with test-enabled clock gating / OCC.
• Uncontrolled resets (async, fire in scan) → corrupt state → fix by gating them inactive in test.
• Latches (not scan cells) → uncontrollable / X → fix by test-transparent or convert to flops.
• Every fix is test-mode only — mission behavior is unchanged.

2. Real Silicon Story — the power gate that killed a domain's coverage

To meet a power target, a team added clock gating across a domain — a plain clk & enable in RTL — and it worked beautifully for power. But at DFT, that domain's scan coverage collapsed: scan DRC failed with an uncontrolled-clock violation, and ATPG couldn't clock the gated flops to shift or capture — their faults came back untestable.

The instinct in the room was to remove the clock gating to 'fix DFT.' That would have thrown away the power savings. The right fix was tiny: use an integrated clock-gating (ICG) cell with a test-enable (TE) — OR the gate's enable with scan-enable so the clock passes freely in test while still gating in mission mode. Coverage returned to target, and the power savings stayed.

Lesson: an uncontrolled clock is not a reason to delete the optimization — it's a reason to make the gating test-controllable. The test-mode fix (ICG TE / OCC) restores scan without touching mission behavior. The same pattern holds for resets (gate inactive in test) and latches (transparent in test).

3. Factory Perspective — the fixes through each lens

• What the test engineer sees: whether clocks are controllable and resets inactive in test — the difference between reachable and untestable flops; OCC also gives at-speed capability (2.3).
• What the yield engineer sees: that fixing these restores coverage on power-gated / reset-heavy blocks → fewer escapes on exactly the logic that was dark.
• What the RTL/DV engineer sees: the idioms — ICG with TE, reset gated by scan_mode, latch transparent in test — that keep mission behavior identical while satisfying scan.
• What management cares about: that these fixes preserve power/area optimizations (clock gating stays!) and restore coverage/DPPM (1.5) — no trade-off, just the right idiom.

4. Concept — three hostilities, three test-mode fixes

(1) Uncontrolled clocks — the fix is test-controllable clocking:

• Problem: a gated clock (clk & enable) or a derived/internal clock (divider, PLL) that ATPG can't control → can't shift/capture → untestable / wrong golden.
• Fix A — test-enabled clock gating (ICG): OR the gate's enable with scan/test-enable so the clock passes freely in test; ICG library cells have a TE pin for exactly this. Mission mode still gates for power.
• Fix B — on-chip clock control (OCC): for internal/derived clocks, an OCC block lets ATPG select a controllable clock in test (and generate at-speed launch/capture, 2.3).
• Fix C — test-clock mux: mux a top-level test clock onto the domain in test mode.

(2) Uncontrolled resets — the fix is gate them inactive in test:

• Problem: an async set/reset that can fire during scan shift/capture → clears/sets loaded flops → corrupts stimulus/response.
• Fix: force the reset inactive in scan mode — e.g. reset_to_flops = arst_n OR scan_mode (deassert during test), so loaded state is preserved. Keep the reset controllable/observable enough that its own faults are still tested (often via a separate test-mode path).

(3) Latches — the fix is make them scan-visible:

• Problem: a level-sensitive latch is not a scan cell → uncontrollable/unobservable, passes X, timing ambiguity.
• Fix A — transparent in test: hold the latch enable asserted in test so it passes data; ATPG then sees through it as combinational.
• Fix B — convert to a flop (make it a scan cell).
• Fix C — LSSD methodology (level-sensitive scan design) where latches are the scan elements by design.

The unifying principle — test-mode only:

• Each fix adds a test-mode control (scan_mode / test_enable) that only affects test behavior.
• Mission mode is unchanged — the power gate still gates, the reset still resets, the latch still latches in the field.

5. Mental Model — a building with a 'maintenance mode'

Picture a smart building whose energy-saving features fight the maintenance crew (ATPG) — until you add a maintenance mode (test mode).

• Motion-activated lights (clock gating) are great for power but leave the crew in the dark in unused rooms. Maintenance mode overrides them to stay on (ICG test-enable) — the crew can work everywhere, while normal days still save power.
• Auto-sprinklers (async reset) could soak the crew mid-job. Maintenance mode disables them (reset gated inactive in test) so work isn't ruined — but they still protect the building normally.
• A one-way turnstile (a latch) the crew can't set or read. Maintenance mode props it open (latch transparent in test) so they can pass through and inspect.
• Crucially, maintenance mode changes nothing about normal operation — lights still auto-dim, sprinklers still guard, turnstiles still turn when the public is in.

Add a maintenance mode (test mode) and the building's smart features stop fighting inspection — without giving them up.

6. Working Example — fixing a gated clock and an async reset

The idioms in three languages — test-mode control only, mission unchanged:

// SystemVerilog — TEST-CONTROLLABLE clock gating (ICG idiom) + reset gated inactive in test
module scan_friendly (
  input  logic clk, arst_n,
  input  logic enable,        // functional clock-gate enable (power)
  input  logic scan_mode,     // 1 in test
  input  logic d, output logic q
);
  // (1) Clock gating with TEST-ENABLE: clock passes in test OR when functionally enabled
  logic gate_en = enable | scan_mode;         // ICG cell would latch this; shown behaviorally
  logic gclk    = clk & gate_en;              // mission: gates for power ; test: passes freely
  // (2) Async reset GATED INACTIVE in scan: reset can't fire during test (loaded state preserved)
  logic rst_eff = arst_n | scan_mode;         // scan_mode=1 -> rst_eff=1 -> reset deasserted in test
  always_ff @(posedge gclk or negedge rst_eff)
    if (!rst_eff) q <= 1'b0;
    else          q <= d;
endmodule

// Verilog-2001 — same idioms
module scan_friendly (clk, arst_n, enable, scan_mode, d, q);
  input clk, arst_n, enable, scan_mode, d; output reg q;
  wire gate_en = enable | scan_mode;          // clock passes in test
  wire gclk    = clk & gate_en;
  wire rst_eff = arst_n | scan_mode;          // reset inactive in test
  always @(posedge gclk or negedge rst_eff)
    if (!rst_eff) q <= 1'b0;
    else          q <= d;
endmodule

-- VHDL — same idioms
library ieee; use ieee.std_logic_1164.all;
entity scan_friendly is
  port (clk, arst_n, enable, scan_mode, d : in std_logic; q : out std_logic);
end entity;
architecture rtl of scan_friendly is
  signal gate_en, gclk, rst_eff, q_i : std_logic;
begin
  gate_en <= enable or scan_mode;   -- clock passes in test
  gclk    <= clk and gate_en;
  rst_eff <= arst_n or scan_mode;   -- reset inactive in test
  process (gclk, rst_eff) begin
    if rst_eff = '0' then q_i <= '0';
    elsif rising_edge(gclk) then q_i <= d; end if;
  end process;
  q <= q_i;
end architecture;

# What changed, and what did NOT — REPRESENTATIVE, tool-neutral:
  MISSION mode (scan_mode=0): gate_en=enable (gates for power) ; rst_eff=arst_n (reset works) -> IDENTICAL to original
  TEST   mode (scan_mode=1): gate_en=1 (clock passes -> ATPG can shift/capture) ; rst_eff=1 (reset OFF -> state preserved)
  -> scan DRC clock+reset violations CLEARED ; power gating + reset kept for the field.
# For DERIVED/internal clocks, use OCC (also gives at-speed capture, 2.3). For latches: hold enable asserted in test.

7. Industry Flow — from violation to test-mode fix to clean DRC

Each hostility is identified by DRC (4.3) and cleared by a test-mode idiom:

8. Debugging Session — clock gating collapses a domain's coverage

9. Common Mistakes

• Removing clock gating to 'fix DFT.' Use an ICG with test-enable / OCC — keep the power savings.
• Leaving async reset active in scan. It corrupts loaded state → gate it inactive in test.
• Ignoring derived/internal clocks. Dividers/PLLs need OCC for control (and at-speed, 2.3).
• Leaving latches uncontrolled. Make them transparent in test or convert to flops.
• Letting test-mode logic leak into mission mode. Fixes must be test-mode only — mission unchanged.

10. Industry Best Practices

• Use ICG cells with test-enable for all clock gating — controllable in test, gating in mission.
• Use OCC for derived/internal clocks — controllability and at-speed capture (2.3).
• Gate async resets inactive in scan — preserve loaded state; keep the reset testable.
• Make latches transparent in test or convert to flops (or adopt LSSD).
• Keep all fixes test-mode only — verify mission mode is byte-for-byte unchanged.

11. Senior Engineer Thinking

• Beginner: "Clock gating broke scan coverage — remove the gating."
• Senior: "The gate's enable isn't test-controllable, so ATPG can't clock those flops. I don't remove the optimization — I use an ICG with test-enable (or OCC for derived clocks) so the clock passes in test and gates in mission. Same idea for reset (gate inactive in test) and latches (transparent in test). Test-mode fixes, mission unchanged."

The senior keeps the optimization and adds a test-mode control — never trading power/area for testability.

12. Silicon Impact

Uncontrolled clocks, resets, and latches are the top three practical scan DRC violations, and this lesson is the toolbox that clears the vast majority of them. The unifying, load-bearing insight is that testability and the optimizations that fight it are not in conflict — you don't remove clock gating, async reset, or latches; you add a test-mode control (scan_mode / test_enable) that makes them scan-friendly only in test, leaving mission behavior identical. Concretely: an ICG cell's test-enable (or OCC for derived clocks) restores clock controllability so ATPG can shift and capture — and OCC doubles as the at-speed enabler (2.3); gating the async reset inactive in scan preserves the loaded stimulus/response so patterns stay valid; and making latches transparent in test (or converting to flops) lets ATPG see through them as combinational. The payoff is coverage restored on exactly the logic that tends to go dark — power-gated domains, reset-heavy control, latch-based datapaths — which is where escapes and DPPM (1.5) would otherwise hide. For the RTL/DV engineer, these few idioms (ICG TE, reset-gate, latch-transparent, OCC) are the concrete 'how' behind scan-ready RTL (4.1): apply them from the start and your power/area optimizations survive while scan DRC (4.3) stays clean and ATPG (Ch5) reaches target coverage — precisely what makes the FSM insertion in 4.5 uneventful.

13. Engineering Checklist

• All clock gating uses ICG cells with test-enable (controllable in test, gating in mission).
• Derived/internal clocks handled by OCC (controllability + at-speed, 2.3).
• Async resets gated inactive in scan (state preserved) — and still testable.
• Latches made transparent in test or converted to flops (or LSSD).
• All fixes are test-mode only — mission mode verified unchanged.

14. Try Yourself

1. Write a raw gated clock (clk & enable) and show why ATPG can't control it; fix it with an ICG test-enable (enable | scan_mode).
2. Add an async reset and show it can fire in scan; fix it with rst_eff = arst_n | scan_mode (inactive in test).
3. Confirm mission mode (scan_mode=0) is identical to the original for both.
4. Sketch an inferred latch and make it transparent in test (enable held asserted); explain why ATPG then sees it as combinational.
5. Name when you'd need OCC instead of an ICG (derived/PLL clocks) and its at-speed bonus (2.3).

The idioms are tool-neutral. Real designs instantiate ICG/OCC library cells; a free simulator can show test-mode vs mission-mode behavior. No paid tool required.

15. Interview Perspective

• Weak: "You remove clock gating and async resets so scan works."
• Good: "You make clock gating test-controllable and hold resets inactive in test, and handle latches."
• Senior: "The top three scan-hostility sources each get a test-mode fix, not removal. Uncontrolled clocks (gated clk & enable, or derived/PLL) → ICG cell with test-enable so the clock passes in test and gates in mission, or OCC for derived clocks (which also gives at-speed, 2.3). Async resets that fire in scan → gate them inactive in scan mode (arst_n | scan_mode) so loaded state is preserved, while keeping the reset testable. Latches → transparent in test (hold enable) so ATPG sees through them, or convert to flops, or LSSD. The key is that every fix is controlled by scan_mode/test_enable, so mission behavior is unchanged — you keep the power gating, reset, and latches, and only their test behavior becomes scannable. These clear most scan DRC violations."

16. Interview / Review Questions

17. Key Takeaways

• Uncontrolled clocks, active async resets, and latches are the top three scan-hostility sources — each breaks scan in a specific way and has a standard test-mode fix.
• Uncontrolled clocks (gated clk & enable, or derived/PLL) prevent deterministic shift/capture → fix with test-enabled clock gating (ICG TE) or OCC (which also enables at-speed, 2.3), or a test-clock mux.
• Async resets that fire during scan corrupt loaded state → gate them inactive in scan mode (arst_n | scan_mode), preserving state, while keeping the reset testable.
• Latches are not scan cells (uncontrollable / X) → make them transparent in test (hold enable), convert to flops, or use LSSD.
• Every fix is a test-mode control (scan_mode/test_enable) that changes only test behavior — the power gating, reset, and latches keep working unchanged in mission mode — so you keep the optimization and the coverage. Next: 4.5 — a working example: scan insertion on an FSM.

18. Quick Revision

Uncontrolled clocks, resets & latches — the fixes. Top 3 scan DRC violations, each fixed by a TEST-MODE control (mission unchanged). CLOCK (gated/derived, ATPG can't control) → ICG cell with TEST-ENABLE (enable | scan_mode, clock passes in test, gates in mission) or OCC for derived clocks (also at-speed, 2.3). ASYNC RESET (fires in scan → corrupts state) → gate inactive in scan (arst_n | scan_mode, deasserted in test; still testable). LATCH (not a scan cell → uncontrollable/X) → transparent in test (hold enable) or convert to flop / LSSD. Don't REMOVE the optimization — add test-mode control → scan DRC (4.3) clean, mission identical. Next: 4.5 — scan insertion on an FSM.